1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
23 // Transformation Function - get Imm - 32.
24 def Subtract32 : SDNodeXForm<imm, [{
25 return getImm(N, (unsigned)N->getZExtValue() - 32);
28 // shamt must fit in 6 bits.
29 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
31 //===----------------------------------------------------------------------===//
32 // Instructions specific format
33 //===----------------------------------------------------------------------===//
34 let usesCustomInserter = 1 in {
35 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
36 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
37 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
38 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
39 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
40 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
41 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
42 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
45 /// Pseudo instructions for loading and storing accumulator registers.
46 let isPseudo = 1, isCodeGenOnly = 1 in {
47 def LOAD_ACC128 : Load<"", ACC128>;
48 def STORE_ACC128 : Store<"", ACC128>;
51 //===----------------------------------------------------------------------===//
52 // Instruction definition
53 //===----------------------------------------------------------------------===//
54 let DecoderNamespace = "Mips64" in {
55 /// Arithmetic Instructions (ALU Immediate)
56 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
57 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith,
59 ADDI_FM<0x19>, IsAsCheapAsAMove;
61 let isCodeGenOnly = 1 in {
62 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
64 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
66 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, IILogic, immZExt16,
69 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
72 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
75 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
78 /// Arithmetic Instructions (3-Operand, R-Type)
79 def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
80 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>,
82 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>,
85 let isCodeGenOnly = 1 in {
86 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
87 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
88 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
89 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
90 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
91 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
94 /// Shift Instructions
95 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, shl, immZExt6>,
97 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, srl, immZExt6>,
99 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, sra, immZExt6>,
101 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>;
102 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>;
103 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>;
104 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd>, SRA_FM<0x3c, 0>;
105 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 0>;
106 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd>, SRA_FM<0x3f, 0>;
108 // Rotate Instructions
109 let Predicates = [HasMips64r2, HasStdEnc] in {
110 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, rotr, immZExt6>,
112 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
114 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>;
117 /// Load and Store Instructions
119 let isCodeGenOnly = 1 in {
120 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>;
121 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>;
122 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>;
123 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>;
124 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>;
125 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>;
126 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>;
127 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>;
130 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>;
131 def LD : Load<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>;
132 def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
134 /// load/store left/right
135 let isCodeGenOnly = 1 in {
136 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>;
137 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>;
138 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>;
139 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>;
142 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>;
143 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>;
144 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>;
145 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>;
147 /// Load-linked, Store-conditional
148 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
149 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
151 /// Jump and Branch Instructions
152 let isCodeGenOnly = 1 in {
153 def JR64 : IndirectBranch<GPR64Opnd>, MTLO_FM<8>;
154 def BEQ64 : CBranch<"beq", seteq, GPR64Opnd>, BEQ_FM<4>;
155 def BNE64 : CBranch<"bne", setne, GPR64Opnd>, BEQ_FM<5>;
156 def BGEZ64 : CBranchZero<"bgez", setge, GPR64Opnd>, BGEZ_FM<1, 1>;
157 def BGTZ64 : CBranchZero<"bgtz", setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
158 def BLEZ64 : CBranchZero<"blez", setle, GPR64Opnd>, BGEZ_FM<6, 0>;
159 def BLTZ64 : CBranchZero<"bltz", setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
160 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
161 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
162 def TAILCALL64_R : JumpFR<GPR64Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
165 /// Multiply and Divide Instructions.
166 def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
168 def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
170 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
172 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
174 def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>;
175 def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>;
176 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
178 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
181 let isCodeGenOnly = 1 in {
182 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
183 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
184 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
185 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
186 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
187 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
189 /// Sign Ext In Register Instructions.
190 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>;
191 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>;
195 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
196 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
198 /// Double Word Swap Bytes/HalfWords
199 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
200 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
202 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
204 let isCodeGenOnly = 1 in
205 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
207 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
208 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
209 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
211 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
212 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
213 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
215 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
216 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
217 "dsll\t$rd, $rt, 32", [], IIArith>;
218 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
219 "sll\t$rd, $rt, 0", [], IIArith>;
220 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
221 "sll\t$rd, $rt, 0", [], IIArith>;
224 //===----------------------------------------------------------------------===//
225 // Arbitrary patterns that map to one or more instructions
226 //===----------------------------------------------------------------------===//
229 let Predicates = [HasStdEnc] in {
230 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
231 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
232 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
233 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
237 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
238 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
239 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
240 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
241 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
242 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
244 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
245 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
246 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
247 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
248 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
249 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
250 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
252 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
253 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
254 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
255 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
256 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
257 (DADDiu GPR64:$hi, tjumptable:$lo)>;
258 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
259 (DADDiu GPR64:$hi, tconstpool:$lo)>;
260 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
261 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
263 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
264 def : WrapperPat<tconstpool, DADDiu, GPR64>;
265 def : WrapperPat<texternalsym, DADDiu, GPR64>;
266 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
267 def : WrapperPat<tjumptable, DADDiu, GPR64>;
268 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
270 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
273 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
274 (BLEZ64 i64:$lhs, bb:$dst)>;
275 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
276 (BGEZ64 i64:$lhs, bb:$dst)>;
279 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
280 defm : SetlePats<GPR64, SLT64, SLTu64>;
281 defm : SetgtPats<GPR64, SLT64, SLTu64>;
282 defm : SetgePats<GPR64, SLT64, SLTu64>;
283 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
286 def : MipsPat<(i32 (trunc GPR64:$src)),
287 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
288 Requires<[HasStdEnc]>;
290 // 32-to-64-bit extension
291 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
292 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
293 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
295 // Sign extend in register
296 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
297 (SLL64_64 GPR64:$src)>;
300 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
302 //===----------------------------------------------------------------------===//
303 // Instruction aliases
304 //===----------------------------------------------------------------------===//
305 def : InstAlias<"move $dst, $src",
306 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
307 Requires<[HasMips64]>;
308 def : InstAlias<"daddu $rs, $rt, $imm",
309 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
311 def : InstAlias<"dadd $rs, $rt, $imm",
312 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
315 /// Move between CPU and coprocessor registers
316 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
317 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
318 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
319 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
320 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
323 // Two operand (implicit 0 selector) versions:
324 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
325 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
326 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
327 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;