1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
24 def simm10_64 : Operand<i64>;
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 // Node immediate fits as 10-bit sign extended on target immediate.
36 def immSExt10_64 : PatLeaf<(i64 imm),
37 [{ return isInt<10>(N->getSExtValue()); }]>;
39 def immZExt16_64 : PatLeaf<(i64 imm),
40 [{ return isInt<16>(N->getZExtValue()); }]>;
42 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
44 // Transformation function: get log2 of low 32 bits of immediate
45 def Log2LO : SDNodeXForm<imm, [{
46 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
49 // Transformation function: get log2 of high 32 bits of immediate
50 def Log2HI : SDNodeXForm<imm, [{
51 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
54 // Predicate: True if immediate is a power of 2 and fits 32 bits
55 def PowerOf2LO : PatLeaf<(imm), [{
56 if (N->getValueType(0) == MVT::i64) {
57 uint64_t Imm = N->getZExtValue();
58 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
64 // Predicate: True if immediate is a power of 2 and exceeds 32 bits
65 def PowerOf2HI : PatLeaf<(imm), [{
66 if (N->getValueType(0) == MVT::i64) {
67 uint64_t Imm = N->getZExtValue();
68 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
74 //===----------------------------------------------------------------------===//
75 // Instructions specific format
76 //===----------------------------------------------------------------------===//
77 let usesCustomInserter = 1 in {
78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
88 /// Pseudo instructions for loading and storing accumulator registers.
89 let isPseudo = 1, isCodeGenOnly = 1 in {
90 def LOAD_ACC128 : Load<"", ACC128>;
91 def STORE_ACC128 : Store<"", ACC128>;
94 //===----------------------------------------------------------------------===//
95 // Instruction definition
96 //===----------------------------------------------------------------------===//
97 let DecoderNamespace = "Mips64" in {
98 /// Arithmetic Instructions (ALU Immediate)
99 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
100 ISA_MIPS3_NOT_32R6_64R6;
101 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
103 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
105 let isCodeGenOnly = 1 in {
106 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
108 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
110 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
112 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
114 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
116 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
119 /// Arithmetic Instructions (3-Operand, R-Type)
120 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
122 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
124 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
126 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
129 let isCodeGenOnly = 1 in {
130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
131 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
132 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
133 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
134 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
135 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
138 /// Shift Instructions
139 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
140 SRA_FM<0x38, 0>, ISA_MIPS3;
141 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
142 SRA_FM<0x3a, 0>, ISA_MIPS3;
143 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
144 SRA_FM<0x3b, 0>, ISA_MIPS3;
145 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
146 SRLV_FM<0x14, 0>, ISA_MIPS3;
147 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
148 SRLV_FM<0x16, 0>, ISA_MIPS3;
149 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
150 SRLV_FM<0x17, 0>, ISA_MIPS3;
151 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
152 SRA_FM<0x3c, 0>, ISA_MIPS3;
153 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
154 SRA_FM<0x3e, 0>, ISA_MIPS3;
155 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
156 SRA_FM<0x3f, 0>, ISA_MIPS3;
158 // Rotate Instructions
159 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
161 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
162 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
163 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
164 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
165 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
167 /// Load and Store Instructions
169 let isCodeGenOnly = 1 in {
170 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
171 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
172 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
173 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
174 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
175 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
176 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
177 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
180 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
181 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
182 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
184 /// load/store left/right
185 let isCodeGenOnly = 1 in {
186 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
187 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
188 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
189 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
192 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
193 ISA_MIPS3_NOT_32R6_64R6;
194 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
195 ISA_MIPS3_NOT_32R6_64R6;
196 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
197 ISA_MIPS3_NOT_32R6_64R6;
198 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
199 ISA_MIPS3_NOT_32R6_64R6;
201 /// Load-linked, Store-conditional
202 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
203 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
205 /// Jump and Branch Instructions
206 let isCodeGenOnly = 1 in {
207 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
208 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
209 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
210 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
211 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
212 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
213 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
214 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
215 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
216 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
219 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
220 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
222 /// Multiply and Divide Instructions.
223 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
224 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
225 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
226 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
227 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
228 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
229 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
230 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
231 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
232 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
233 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
234 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
235 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
236 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
237 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
238 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
240 let isCodeGenOnly = 1 in {
241 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
242 ISA_MIPS3_NOT_32R6_64R6;
243 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
244 ISA_MIPS3_NOT_32R6_64R6;
245 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
246 ISA_MIPS3_NOT_32R6_64R6;
247 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
248 ISA_MIPS3_NOT_32R6_64R6;
249 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
250 ISA_MIPS3_NOT_32R6_64R6;
251 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
252 ISA_MIPS3_NOT_32R6_64R6;
253 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
255 /// Sign Ext In Register Instructions.
256 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
258 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
263 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
264 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
266 /// Double Word Swap Bytes/HalfWords
267 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
268 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
270 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
272 let isCodeGenOnly = 1 in
273 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
275 let AdditionalPredicates = [NotInMicroMips] in {
276 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
277 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
278 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32>, EXT_FM<2>;
281 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
282 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32>, EXT_FM<6>;
283 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
285 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
286 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
287 "dsll\t$rd, $rt, 32", [], II_DSLL>;
288 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
289 "sll\t$rd, $rt, 0", [], II_SLL>;
290 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
291 "sll\t$rd, $rt, 0", [], II_SLL>;
294 // We need the following pseudo instruction to avoid offset calculation for
295 // long branches. See the comment in file MipsLongBranch.cpp for detailed
298 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
299 // where %PART may be %hi or %lo, depending on the relocation kind
300 // that $tgt is annotated with.
301 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
302 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
304 // Cavium Octeon cnMIPS instructions
305 let DecoderNamespace = "CnMips",
306 EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
307 AdditionalPredicates = [HasCnMips] in {
309 class Count1s<string opstr, RegisterOperand RO>:
310 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
311 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
312 let TwoOperandAliasConstraint = "$rd = $rs";
315 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
316 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
317 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
318 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
319 NoItinerary, FrmR, opstr> {
320 let TwoOperandAliasConstraint = "$rt = $rs";
323 class SetCC64_R<string opstr, PatFrag cond_op> :
324 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
325 !strconcat(opstr, "\t$rd, $rs, $rt"),
326 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
328 II_SEQ_SNE, FrmR, opstr> {
329 let TwoOperandAliasConstraint = "$rd = $rs";
332 class SetCC64_I<string opstr, PatFrag cond_op>:
333 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
334 !strconcat(opstr, "\t$rt, $rs, $imm10"),
335 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
336 immSExt10_64:$imm10)))],
337 II_SEQI_SNEI, FrmI, opstr> {
338 let TwoOperandAliasConstraint = "$rt = $rs";
341 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
342 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
343 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
344 !strconcat(opstr, "\t$rs, $p, $offset"),
345 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
346 bb:$offset)], II_BBIT, FrmI, opstr> {
348 let isTerminator = 1;
349 let hasDelaySlot = 1;
353 class MFC2OP<string asmstr, RegisterOperand RO> :
354 InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
355 !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
358 let Pattern = [(set GPR64Opnd:$rd,
359 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
360 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
363 // Branch on Bit Clear /+32
364 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
365 uimm5_64_report_uimm6>, BBIT_FM<0x32>;
366 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
370 // Branch on Bit Set /+32
371 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
372 uimm5_64_report_uimm6>, BBIT_FM<0x3a>;
373 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
374 0x100000000>, BBIT_FM<0x3e>;
376 // Multiply Doubleword to GPR
377 let Defs = [HI0, LO0, P0, P1, P2] in
378 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
381 // Extract a signed bit field /+32
382 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
383 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
385 // Clear and insert a bit field /+32
386 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
387 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
389 // Move to multiplier/product register
390 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
391 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
392 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
393 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
394 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
395 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
397 // Count Ones in a Word/Doubleword
398 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
399 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
401 // Set on equal/not equal
402 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
403 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
404 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
405 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
407 // 192-bit x 64-bit Unsigned Multiply and Add
408 let Defs = [P0, P1, P2] in
409 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
412 // 64-bit Unsigned Multiply and Add Move
413 let Defs = [MPL0, P0, P1, P2] in
414 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
417 // 64-bit Unsigned Multiply and Add
418 let Defs = [MPL1, MPL2, P0, P1, P2] in
419 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
422 // Move between CPU and coprocessor registers
423 def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>;
424 def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
429 /// Move between CPU and coprocessor registers
430 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
431 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>, ISA_MIPS3;
432 def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
433 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
434 def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
437 //===----------------------------------------------------------------------===//
438 // Arbitrary patterns that map to one or more instructions
439 //===----------------------------------------------------------------------===//
442 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
443 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
444 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
445 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
448 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
449 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
450 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
451 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
452 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
453 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
455 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
456 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
457 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
458 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
459 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
460 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
461 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
463 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
464 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
465 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
466 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
467 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
468 (DADDiu GPR64:$hi, tjumptable:$lo)>;
469 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
470 (DADDiu GPR64:$hi, tconstpool:$lo)>;
471 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
472 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
474 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
475 def : WrapperPat<tconstpool, DADDiu, GPR64>;
476 def : WrapperPat<texternalsym, DADDiu, GPR64>;
477 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
478 def : WrapperPat<tjumptable, DADDiu, GPR64>;
479 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
481 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
484 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
485 (BLEZ64 i64:$lhs, bb:$dst)>;
486 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
487 (BGEZ64 i64:$lhs, bb:$dst)>;
490 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
491 defm : SetlePats<GPR64, SLT64, SLTu64>;
492 defm : SetgtPats<GPR64, SLT64, SLTu64>;
493 defm : SetgePats<GPR64, SLT64, SLTu64>;
494 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
497 def : MipsPat<(trunc (assertsext GPR64:$src)),
498 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
499 def : MipsPat<(trunc (assertzext GPR64:$src)),
500 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
501 def : MipsPat<(i32 (trunc GPR64:$src)),
502 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
504 // variable shift instructions patterns
505 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
506 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
507 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
508 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
509 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
510 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
511 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
512 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
514 // 32-to-64-bit extension
515 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
516 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
517 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
519 // Sign extend in register
520 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
521 (SLL64_64 GPR64:$src)>;
524 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
527 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
528 (DSUBu GPR64:$lhs, GPR64:$rhs)>;
529 let AdditionalPredicates = [NotDSP] in {
530 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
531 (DADDu GPR64:$lhs, GPR64:$rhs)>;
532 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
533 (DADDiu GPR64:$lhs, imm:$imm)>;
536 // Octeon bbit0/bbit1 MipsPattern
537 let Predicates = [HasMips64, HasCnMips] in {
538 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
539 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
540 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
541 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
542 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
543 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
544 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
545 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
548 // Atomic load patterns.
549 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
550 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
551 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
552 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
554 // Atomic store patterns.
555 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
556 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
557 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
558 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
560 //===----------------------------------------------------------------------===//
561 // Instruction aliases
562 //===----------------------------------------------------------------------===//
563 def : MipsInstAlias<"move $dst, $src",
564 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
566 def : MipsInstAlias<"move $dst, $src",
567 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
569 def : MipsInstAlias<"daddu $rs, $rt, $imm",
570 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
572 def : MipsInstAlias<"dadd $rs, $rt, $imm",
573 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
574 0>, ISA_MIPS3_NOT_32R6_64R6;
575 def : MipsInstAlias<"daddu $rs, $imm",
576 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
578 def : MipsInstAlias<"dadd $rs, $imm",
579 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
580 0>, ISA_MIPS3_NOT_32R6_64R6;
581 def : MipsInstAlias<"dsll $rd, $rt, $rs",
582 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
584 def : MipsInstAlias<"dneg $rt, $rs",
585 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
587 def : MipsInstAlias<"dneg $rt",
588 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
590 def : MipsInstAlias<"dnegu $rt, $rs",
591 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
593 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
594 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
595 InvertedImOperand64:$imm), 0>, ISA_MIPS3;
596 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
597 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
598 InvertedImOperand64:$imm),
599 0>, ISA_MIPS3_NOT_32R6_64R6;
600 def : MipsInstAlias<"dsubi $rs, $imm",
601 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
602 InvertedImOperand64:$imm),
603 0>, ISA_MIPS3_NOT_32R6_64R6;
604 def : MipsInstAlias<"dsub $rs, $rt, $imm",
605 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
606 InvertedImOperand64:$imm),
607 0>, ISA_MIPS3_NOT_32R6_64R6;
608 def : MipsInstAlias<"dsub $rs, $imm",
609 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
610 InvertedImOperand64:$imm),
611 0>, ISA_MIPS3_NOT_32R6_64R6;
612 def : MipsInstAlias<"dsubu $rs, $imm",
613 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
614 InvertedImOperand64:$imm),
616 def : MipsInstAlias<"dsra $rd, $rt, $rs",
617 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
619 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
620 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
623 // Two operand (implicit 0 selector) versions:
624 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
625 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
626 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
627 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
629 let Predicates = [HasMips64, HasCnMips] in {
630 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
631 def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
632 def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
633 def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
638 // bbit* with $p 32-63 converted to bbit*32 with $p 0-31
639 def : MipsInstAlias<"bbit0 $rs, $p, $offset",
640 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p,
641 brtarget:$offset), 0>,
643 def : MipsInstAlias<"bbit1 $rs, $p, $offset",
644 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p,
645 brtarget:$offset), 0>,
648 // exts with $pos 32-63 in converted to exts32 with $pos 0-31
649 def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1",
650 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs,
651 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
653 def : MipsInstAlias<"exts $rt, $pos, $lenm1",
654 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt,
655 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
658 // cins with $pos 32-63 in converted to cins32 with $pos 0-31
659 def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1",
660 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs,
661 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
663 def : MipsInstAlias<"cins $rt, $pos, $lenm1",
664 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt,
665 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
668 //===----------------------------------------------------------------------===//
669 // Assembler Pseudo Instructions
670 //===----------------------------------------------------------------------===//
672 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
673 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
674 !strconcat(instr_asm, "\t$rt, $imm64")> ;
675 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;
677 def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr),
679 def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64),