1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
37 let DecoderNamespace = "Mips64" in {
39 multiclass Atomic2Ops64<PatFrag Op> {
40 def NAME : Atomic2Ops<Op, GPR64, GPR32>, Requires<[NotN64, HasStdEnc]>;
41 def _P8 : Atomic2Ops<Op, GPR64, GPR64>, Requires<[IsN64, HasStdEnc]>;
44 multiclass AtomicCmpSwap64<PatFrag Op> {
45 def NAME : AtomicCmpSwap<Op, GPR64, GPR32>,
46 Requires<[NotN64, HasStdEnc]>;
47 def _P8 : AtomicCmpSwap<Op, GPR64, GPR64>,
48 Requires<[IsN64, HasStdEnc]>;
51 let usesCustomInserter = 1, Predicates = [HasStdEnc],
52 DecoderNamespace = "Mips64" in {
53 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
54 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
55 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
56 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
57 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
58 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
59 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
60 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
63 /// Pseudo instructions for loading and storing accumulator registers.
64 let isPseudo = 1, isCodeGenOnly = 1 in {
65 defm LOAD_ACC128 : LoadM<"", ACC128>;
66 defm STORE_ACC128 : StoreM<"", ACC128>;
69 //===----------------------------------------------------------------------===//
70 // Instruction definition
71 //===----------------------------------------------------------------------===//
72 let DecoderNamespace = "Mips64" in {
73 /// Arithmetic Instructions (ALU Immediate)
74 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
75 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith,
77 ADDI_FM<0x19>, IsAsCheapAsAMove;
79 let isCodeGenOnly = 1 in {
80 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
82 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
84 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, IILogic, immZExt16,
87 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
90 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
93 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
96 /// Arithmetic Instructions (3-Operand, R-Type)
97 def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
98 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>,
100 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>,
103 let isCodeGenOnly = 1 in {
104 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
105 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
106 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
107 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
108 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
109 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
112 /// Shift Instructions
113 def DSLL : shift_rotate_imm<"dsll", shamt, GPR64Opnd, shl, immZExt6>,
115 def DSRL : shift_rotate_imm<"dsrl", shamt, GPR64Opnd, srl, immZExt6>,
117 def DSRA : shift_rotate_imm<"dsra", shamt, GPR64Opnd, sra, immZExt6>,
119 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>;
120 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>;
121 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>;
122 def DSLL32 : shift_rotate_imm<"dsll32", shamt, GPR64Opnd>, SRA_FM<0x3c, 0>;
123 def DSRL32 : shift_rotate_imm<"dsrl32", shamt, GPR64Opnd>, SRA_FM<0x3e, 0>;
124 def DSRA32 : shift_rotate_imm<"dsra32", shamt, GPR64Opnd>, SRA_FM<0x3f, 0>;
126 // Rotate Instructions
127 let Predicates = [HasMips64r2, HasStdEnc] in {
128 def DROTR : shift_rotate_imm<"drotr", shamt, GPR64Opnd, rotr, immZExt6>,
130 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
134 /// Load and Store Instructions
136 let isCodeGenOnly = 1 in {
137 defm LB64 : LoadM<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>;
138 defm LBu64 : LoadM<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>;
139 defm LH64 : LoadM<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>;
140 defm LHu64 : LoadM<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>;
141 defm LW64 : LoadM<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>;
142 defm SB64 : StoreM<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>;
143 defm SH64 : StoreM<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>;
144 defm SW64 : StoreM<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>;
147 defm LWu : LoadM<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>;
148 defm LD : LoadM<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>;
149 defm SD : StoreM<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
151 /// load/store left/right
152 let isCodeGenOnly = 1 in {
153 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, GPR64Opnd>, LW_FM<0x22>;
154 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, GPR64Opnd>, LW_FM<0x26>;
155 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>;
156 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, GPR64Opnd>, LW_FM<0x2e>;
159 defm LDL : LoadLeftRightM<"ldl", MipsLDL, GPR64Opnd>, LW_FM<0x1a>;
160 defm LDR : LoadLeftRightM<"ldr", MipsLDR, GPR64Opnd>, LW_FM<0x1b>;
161 defm SDL : StoreLeftRightM<"sdl", MipsSDL, GPR64Opnd>, LW_FM<0x2c>;
162 defm SDR : StoreLeftRightM<"sdr", MipsSDR, GPR64Opnd>, LW_FM<0x2d>;
164 /// Load-linked, Store-conditional
165 let Predicates = [NotN64, HasStdEnc] in {
166 def LLD : LLBase<"lld", GPR64Opnd, mem>, LW_FM<0x34>;
167 def SCD : SCBase<"scd", GPR64Opnd, mem>, LW_FM<0x3c>;
170 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
171 def LLD_P8 : LLBase<"lld", GPR64Opnd, mem64>, LW_FM<0x34>;
172 def SCD_P8 : SCBase<"scd", GPR64Opnd, mem64>, LW_FM<0x3c>;
175 /// Jump and Branch Instructions
176 let isCodeGenOnly = 1 in {
177 def JR64 : IndirectBranch<GPR64Opnd>, MTLO_FM<8>;
178 def BEQ64 : CBranch<"beq", seteq, GPR64Opnd>, BEQ_FM<4>;
179 def BNE64 : CBranch<"bne", setne, GPR64Opnd>, BEQ_FM<5>;
180 def BGEZ64 : CBranchZero<"bgez", setge, GPR64Opnd>, BGEZ_FM<1, 1>;
181 def BGTZ64 : CBranchZero<"bgtz", setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
182 def BLEZ64 : CBranchZero<"blez", setle, GPR64Opnd>, BGEZ_FM<6, 0>;
183 def BLTZ64 : CBranchZero<"bltz", setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
184 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
185 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
186 def TAILCALL64_R : JumpFR<GPR64Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
189 /// Multiply and Divide Instructions.
190 def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI64, LO64]>,
192 def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI64, LO64]>,
194 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
196 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
198 def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
199 def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
200 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
202 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
205 let isCodeGenOnly = 1 in {
206 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI64]>, MTLO_FM<0x11>;
207 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO64]>, MTLO_FM<0x13>;
208 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, [HI64]>, MFLO_FM<0x10>;
209 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, [LO64]>, MFLO_FM<0x12>;
211 /// Sign Ext In Register Instructions.
212 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>;
213 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>;
217 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
218 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
220 /// Double Word Swap Bytes/HalfWords
221 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
222 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
224 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd, mem_ea_64>, LW_FM<0x19>;
226 let isCodeGenOnly = 1 in
227 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
229 def DEXT : ExtBase<"dext", GPR64Opnd>, EXT_FM<3>;
230 let Pattern = []<dag> in {
231 def DEXTU : ExtBase<"dextu", GPR64Opnd>, EXT_FM<2>;
232 def DEXTM : ExtBase<"dextm", GPR64Opnd>, EXT_FM<1>;
234 def DINS : InsBase<"dins", GPR64Opnd>, EXT_FM<7>;
235 let Pattern = []<dag> in {
236 def DINSU : InsBase<"dinsu", GPR64Opnd>, EXT_FM<6>;
237 def DINSM : InsBase<"dinsm", GPR64Opnd>, EXT_FM<5>;
240 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
241 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
242 "dsll\t$rd, $rt, 32", [], IIArith>;
243 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
244 "sll\t$rd, $rt, 0", [], IIArith>;
245 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
246 "sll\t$rd, $rt, 0", [], IIArith>;
249 //===----------------------------------------------------------------------===//
250 // Arbitrary patterns that map to one or more instructions
251 //===----------------------------------------------------------------------===//
254 let Predicates = [NotN64, HasStdEnc] in {
255 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
256 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
257 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
258 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
260 let Predicates = [IsN64, HasStdEnc] in {
261 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
262 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
263 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
264 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
268 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
269 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
270 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
271 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
272 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
273 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
275 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
276 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
277 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
278 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
279 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
280 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
281 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
283 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
284 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
285 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
286 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
287 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
288 (DADDiu GPR64:$hi, tjumptable:$lo)>;
289 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
290 (DADDiu GPR64:$hi, tconstpool:$lo)>;
291 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
292 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
294 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
295 def : WrapperPat<tconstpool, DADDiu, GPR64>;
296 def : WrapperPat<texternalsym, DADDiu, GPR64>;
297 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
298 def : WrapperPat<tjumptable, DADDiu, GPR64>;
299 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
301 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
304 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
305 (BLEZ64 i64:$lhs, bb:$dst)>;
306 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
307 (BGEZ64 i64:$lhs, bb:$dst)>;
310 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
311 defm : SetlePats<GPR64, SLT64, SLTu64>;
312 defm : SetgtPats<GPR64, SLT64, SLTu64>;
313 defm : SetgePats<GPR64, SLT64, SLTu64>;
314 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
317 def : MipsPat<(i32 (trunc GPR64:$src)),
318 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
319 Requires<[IsN64, HasStdEnc]>;
321 // 32-to-64-bit extension
322 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
323 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
324 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
326 // Sign extend in register
327 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
328 (SLL64_64 GPR64:$src)>;
331 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
334 def : MipsPat<(i64 (ExtractLOHI ACC128:$ac, imm:$lohi_idx)),
335 (EXTRACT_SUBREG ACC128:$ac, imm:$lohi_idx)>;
337 //===----------------------------------------------------------------------===//
338 // Instruction aliases
339 //===----------------------------------------------------------------------===//
340 def : InstAlias<"move $dst, $src",
341 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
342 Requires<[HasMips64]>;
343 def : InstAlias<"daddu $rs, $rt, $imm",
344 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
346 def : InstAlias<"dadd $rs, $rt, $imm",
347 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
350 /// Move between CPU and coprocessor registers
351 let DecoderNamespace = "Mips64" in {
352 def DMFC0_3OP64 : MFC3OP<(outs GPR64Opnd:$rt),
353 (ins GPR64Opnd:$rd, uimm16:$sel),
354 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
355 def DMTC0_3OP64 : MFC3OP<(outs GPR64Opnd:$rd, uimm16:$sel),
357 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
358 def DMFC2_3OP64 : MFC3OP<(outs GPR64Opnd:$rt),
359 (ins GPR64Opnd:$rd, uimm16:$sel),
360 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
361 def DMTC2_3OP64 : MFC3OP<(outs GPR64Opnd:$rd, uimm16:$sel),
363 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
366 // Two operand (implicit 0 selector) versions:
367 def : InstAlias<"dmfc0 $rt, $rd",
368 (DMFC0_3OP64 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
369 def : InstAlias<"dmtc0 $rt, $rd",
370 (DMTC0_3OP64 GPR64Opnd:$rd, 0, GPR64Opnd:$rt), 0>;
371 def : InstAlias<"dmfc2 $rt, $rd",
372 (DMFC2_3OP64 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
373 def : InstAlias<"dmtc2 $rt, $rd",
374 (DMTC2_3OP64 GPR64Opnd:$rd, 0, GPR64Opnd:$rt), 0>;