1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
41 // Rencoded: [ls][wd]c2
43 def brtarget21 : Operand<OtherVT> {
44 let EncoderMethod = "getBranchTarget21OpValue";
45 let OperandType = "OPERAND_PCREL";
46 let DecoderMethod = "DecodeBranchTarget21";
47 let ParserMatchClass = MipsJumpTargetAsmOperand;
50 def brtarget26 : Operand<OtherVT> {
51 let EncoderMethod = "getBranchTarget26OpValue";
52 let OperandType = "OPERAND_PCREL";
53 let DecoderMethod = "DecodeBranchTarget26";
54 let ParserMatchClass = MipsJumpTargetAsmOperand;
57 def jmpoffset16 : Operand<OtherVT> {
58 let EncoderMethod = "getJumpOffset16OpValue";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def calloffset16 : Operand<iPTR> {
63 let EncoderMethod = "getJumpOffset16OpValue";
64 let ParserMatchClass = MipsJumpTargetAsmOperand;
67 //===----------------------------------------------------------------------===//
69 // Instruction Encodings
71 //===----------------------------------------------------------------------===//
73 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
74 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
75 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
76 class AUI_ENC : AUI_FM;
77 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
79 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
80 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
81 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
82 DecodeDisambiguates<"AddiGroupBranch">;
83 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
84 DecodeDisambiguatedBy<"DaddiGroupBranch">;
85 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
86 DecodeDisambiguates<"DaddiGroupBranch">;
87 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
88 DecodeDisambiguatedBy<"DaddiGroupBranch">;
90 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
91 DecodeDisambiguates<"BgtzlGroupBranch">;
92 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
93 DecodeDisambiguatedBy<"BlezlGroupBranch">;
94 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
95 DecodeDisambiguatedBy<"BlezGroupBranch">;
96 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
97 DecodeDisambiguates<"BlezlGroupBranch">;
98 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
99 DecodeDisambiguatedBy<"BgtzGroupBranch">;
101 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
102 DecodeDisambiguatedBy<"BlezlGroupBranch">;
103 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
104 DecodeDisambiguates<"BgtzGroupBranch">;
105 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
106 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
108 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
109 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
110 DecodeDisambiguates<"BlezGroupBranch">;
111 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
113 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
114 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
115 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
116 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
118 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
119 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
120 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
121 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
122 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
123 DecodeDisambiguatedBy<"BlezGroupBranch">;
124 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
125 DecodeDisambiguatedBy<"DaddiGroupBranch">;
126 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
127 DecodeDisambiguatedBy<"AddiGroupBranch">;
128 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
129 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
130 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
131 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
132 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
133 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
134 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
135 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
137 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
138 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
139 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
140 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
142 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
143 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
145 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
146 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
148 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
149 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
151 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
152 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
153 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
154 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
156 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
157 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
158 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
159 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
161 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
162 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
163 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
164 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
166 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
167 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
168 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
169 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
171 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
172 RegisterOperand FGROpnd,
173 SDPatternOperator Op = null_frag> {
174 dag OutOperandList = (outs FGRCCOpnd:$fd);
175 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
176 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
177 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
180 //===----------------------------------------------------------------------===//
182 // Instruction Multiclasses
184 //===----------------------------------------------------------------------===//
186 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
187 RegisterOperand FGROpnd>{
188 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
189 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
191 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
192 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
194 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
195 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
197 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
198 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
200 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
201 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
203 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
204 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
206 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
207 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
209 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
210 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
212 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
213 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
215 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
216 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
218 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
219 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
221 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
222 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
224 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
225 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
227 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
228 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
230 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
231 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
233 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
234 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
238 //===----------------------------------------------------------------------===//
240 // Instruction Descriptions
242 //===----------------------------------------------------------------------===//
244 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
246 dag OutOperandList = (outs GPROpnd:$rs);
247 dag InOperandList = (ins ImmOpnd:$imm);
248 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
249 list<dag> Pattern = [];
252 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
253 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
254 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
256 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
258 dag OutOperandList = (outs GPROpnd:$rd);
259 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
260 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
261 list<dag> Pattern = [];
264 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
266 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
267 dag OutOperandList = (outs GPROpnd:$rs);
268 dag InOperandList = (ins simm16:$imm);
269 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
270 list<dag> Pattern = [];
273 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
274 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
276 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
277 dag OutOperandList = (outs GPROpnd:$rs);
278 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
279 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
280 list<dag> Pattern = [];
283 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
285 class BRANCH_DESC_BASE {
287 bit isTerminator = 1;
288 bit hasDelaySlot = 0;
291 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
292 dag InOperandList = (ins opnd:$offset);
293 dag OutOperandList = (outs);
294 string AsmString = !strconcat(instr_asm, "\t$offset");
298 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
299 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
300 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
301 dag OutOperandList = (outs);
302 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
303 list<Register> Defs = [AT];
306 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
307 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
308 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
309 dag OutOperandList = (outs);
310 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
311 list<Register> Defs = [AT];
314 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
315 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
316 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
317 dag OutOperandList = (outs);
318 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
319 list<Register> Defs = [AT];
322 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
324 list<Register> Defs = [RA];
327 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
328 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
329 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
330 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
331 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
333 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
334 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
336 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
337 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
339 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
340 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
342 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
343 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
344 dag OutOperandList = (outs);
345 string AsmString = instr_asm;
346 bit hasDelaySlot = 1;
349 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
350 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
352 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
353 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
354 dag OutOperandList = (outs);
355 string AsmString = instr_asm;
356 bit hasDelaySlot = 1;
359 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
360 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
362 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
363 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
365 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
366 RegisterOperand GPROpnd> {
367 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
368 string AsmString = !strconcat(opstr, "\t$rt, $offset");
369 list<dag> Pattern = [];
370 bit isTerminator = 1;
371 bit hasDelaySlot = 0;
372 string DecoderMethod = "DecodeSimm16";
375 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
378 list<Register> Defs = [RA];
381 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
383 list<Register> Defs = [AT];
386 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
388 bit isIndirectBranch = 1;
389 bit hasDelaySlot = 1;
394 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
395 dag OutOperandList = (outs GPROpnd:$rd);
396 dag InOperandList = (ins GPROpnd:$rt);
397 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
398 list<dag> Pattern = [];
401 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
403 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
404 SDPatternOperator Op=null_frag> {
405 dag OutOperandList = (outs GPROpnd:$rd);
406 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
407 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
408 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
410 // This instruction doesn't trap division by zero itself. We must insert
411 // teq instructions as well.
412 bit usesCustomInserter = 1;
415 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
416 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
417 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
418 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
420 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
421 list<Register> Defs = [RA];
424 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
425 list<Register> Defs = [RA];
428 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
429 list<Register> Defs = [RA];
432 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
433 list<Register> Defs = [RA];
436 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
437 list<Register> Defs = [RA];
440 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
441 list<Register> Defs = [RA];
444 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
445 SDPatternOperator Op=null_frag> {
446 dag OutOperandList = (outs GPROpnd:$rd);
447 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
448 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
449 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
452 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
453 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
454 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
455 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
457 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
458 dag OutOperandList = (outs FGROpnd:$fd);
459 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
460 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
461 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
464 string Constraints = "$fd_in = $fd";
467 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
468 // We must insert a SUBREG_TO_REG around $fd_in
469 bit usesCustomInserter = 1;
471 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
473 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
474 dag OutOperandList = (outs GPROpnd:$rd);
475 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
476 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
477 list<dag> Pattern = [];
480 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
481 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
483 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
484 dag OutOperandList = (outs FGROpnd:$fd);
485 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
486 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
487 list<dag> Pattern = [];
488 string Constraints = "$fd_in = $fd";
491 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
492 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
493 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
494 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
496 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
497 dag OutOperandList = (outs FGROpnd:$fd);
498 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
499 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
500 list<dag> Pattern = [];
503 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
504 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
505 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
506 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
508 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
509 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
510 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
511 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
513 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
514 dag OutOperandList = (outs FGROpnd:$fd);
515 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
516 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
517 list<dag> Pattern = [];
520 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
521 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
522 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
523 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
525 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
526 dag OutOperandList = (outs FGROpnd:$fd);
527 dag InOperandList = (ins FGROpnd:$fs);
528 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
529 list<dag> Pattern = [];
532 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
533 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
534 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
535 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
537 //===----------------------------------------------------------------------===//
539 // Instruction Definitions
541 //===----------------------------------------------------------------------===//
543 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
544 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
545 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
546 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
547 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
548 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
549 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
550 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
551 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
552 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
553 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
554 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
555 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
556 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
557 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
558 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
559 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
560 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
561 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
562 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
563 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
564 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
565 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
566 def BLTC; // Also aliased to bgtc with operands swapped
567 def BLTUC; // Also aliased to bgtuc with operands swapped
568 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
569 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
570 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
571 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
572 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
573 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
574 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
575 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
576 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
577 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
578 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
579 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
580 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
581 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
582 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
583 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
584 // def LSA; // See MSA
585 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
586 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
587 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
588 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
589 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
590 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
591 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
592 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
593 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
594 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
595 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
596 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
597 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
598 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
599 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
600 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
601 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
602 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
603 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
604 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
605 def NAL; // BAL with rd=0
606 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
607 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
608 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
609 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
610 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
611 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
612 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
613 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
614 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
615 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
617 //===----------------------------------------------------------------------===//
619 // Patterns and Pseudo Instructions
621 //===----------------------------------------------------------------------===//
623 // f32 comparisons supported via another comparison
624 def : MipsPat<(setone f32:$lhs, f32:$rhs),
625 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
626 def : MipsPat<(seto f32:$lhs, f32:$rhs),
627 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
628 def : MipsPat<(setune f32:$lhs, f32:$rhs),
629 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
630 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
632 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
634 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
636 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
638 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
640 def : MipsPat<(setne f32:$lhs, f32:$rhs),
641 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
643 // f64 comparisons supported via another comparison
644 def : MipsPat<(setone f64:$lhs, f64:$rhs),
645 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
646 def : MipsPat<(seto f64:$lhs, f64:$rhs),
647 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
648 def : MipsPat<(setune f64:$lhs, f64:$rhs),
649 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
650 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
652 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
654 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
656 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
658 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
660 def : MipsPat<(setne f64:$lhs, f64:$rhs),
661 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
664 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
665 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
667 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
668 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
670 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
671 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
673 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
674 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
675 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
677 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
678 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
679 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
681 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
683 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
684 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
686 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
688 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
689 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
692 def : MipsPat<(select i32:$cond, i32:$t, immz),
693 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
694 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
695 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
696 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
697 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
698 def : MipsPat<(select i32:$cond, immz, i32:$f),
699 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
700 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
701 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
702 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
703 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;