1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
31 // Rencoded: [ls][wd]c2
33 def brtarget21 : Operand<OtherVT> {
34 let EncoderMethod = "getBranchTarget21OpValue";
35 let OperandType = "OPERAND_PCREL";
36 let DecoderMethod = "DecodeBranchTarget21";
37 let ParserMatchClass = MipsJumpTargetAsmOperand;
40 def brtarget26 : Operand<OtherVT> {
41 let EncoderMethod = "getBranchTarget26OpValue";
42 let OperandType = "OPERAND_PCREL";
43 let DecoderMethod = "DecodeBranchTarget26";
44 let ParserMatchClass = MipsJumpTargetAsmOperand;
47 def jmpoffset16 : Operand<OtherVT> {
48 let EncoderMethod = "getJumpOffset16OpValue";
49 let ParserMatchClass = MipsJumpTargetAsmOperand;
52 def calloffset16 : Operand<iPTR> {
53 let EncoderMethod = "getJumpOffset16OpValue";
54 let ParserMatchClass = MipsJumpTargetAsmOperand;
57 //===----------------------------------------------------------------------===//
59 // Instruction Encodings
61 //===----------------------------------------------------------------------===//
63 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
64 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
65 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
66 class AUI_ENC : AUI_FM;
67 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
69 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
70 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
71 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
72 DecodeDisambiguates<"AddiGroupBranch">;
73 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
74 DecodeDisambiguatedBy<"DaddiGroupBranch">;
75 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
76 DecodeDisambiguates<"DaddiGroupBranch">;
77 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
78 DecodeDisambiguatedBy<"DaddiGroupBranch">;
80 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
81 DecodeDisambiguates<"BgtzlGroupBranch">;
82 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
83 DecodeDisambiguatedBy<"BlezlGroupBranch">;
84 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
85 DecodeDisambiguatedBy<"BlezGroupBranch">;
86 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
87 DecodeDisambiguates<"BlezlGroupBranch">;
88 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
89 DecodeDisambiguatedBy<"BgtzGroupBranch">;
91 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
92 DecodeDisambiguatedBy<"BlezlGroupBranch">;
93 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
94 DecodeDisambiguates<"BgtzGroupBranch">;
95 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
96 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
98 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
99 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
100 DecodeDisambiguates<"BlezGroupBranch">;
101 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
103 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
104 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
105 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
106 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
108 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
109 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
110 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
111 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
112 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
113 DecodeDisambiguatedBy<"BlezGroupBranch">;
114 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
115 DecodeDisambiguatedBy<"DaddiGroupBranch">;
116 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
117 DecodeDisambiguatedBy<"AddiGroupBranch">;
118 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
119 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
120 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
121 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
122 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
123 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
124 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
125 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
127 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
128 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
129 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
130 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
132 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
133 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
135 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
136 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
138 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
139 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
141 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
142 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
143 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
144 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
146 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
147 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
148 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
149 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
151 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
152 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
153 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
154 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
156 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
157 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
158 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
159 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
161 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
162 RegisterOperand FGROpnd,
163 SDPatternOperator Op = null_frag> {
164 dag OutOperandList = (outs FGRCCOpnd:$fd);
165 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
166 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
167 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
170 //===----------------------------------------------------------------------===//
172 // Instruction Multiclasses
174 //===----------------------------------------------------------------------===//
176 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
177 RegisterOperand FGROpnd>{
178 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
179 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
181 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
182 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
184 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
185 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
187 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
188 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
190 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
191 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
193 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
194 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
196 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
197 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
199 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
200 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
202 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
203 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
205 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
206 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
208 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
209 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
211 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
212 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
214 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
215 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
217 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
218 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
220 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
221 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
223 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
224 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
228 //===----------------------------------------------------------------------===//
230 // Instruction Descriptions
232 //===----------------------------------------------------------------------===//
234 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
236 dag OutOperandList = (outs GPROpnd:$rs);
237 dag InOperandList = (ins ImmOpnd:$imm);
238 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
239 list<dag> Pattern = [];
242 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
243 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
244 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
246 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
248 dag OutOperandList = (outs GPROpnd:$rd);
249 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
250 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
251 list<dag> Pattern = [];
254 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
256 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
257 dag OutOperandList = (outs GPROpnd:$rs);
258 dag InOperandList = (ins simm16:$imm);
259 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
260 list<dag> Pattern = [];
263 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
264 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
266 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
267 dag OutOperandList = (outs GPROpnd:$rs);
268 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
269 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
270 list<dag> Pattern = [];
273 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
275 class BRANCH_DESC_BASE {
277 bit isTerminator = 1;
278 bit hasDelaySlot = 0;
281 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
282 dag InOperandList = (ins opnd:$offset);
283 dag OutOperandList = (outs);
284 string AsmString = !strconcat(instr_asm, "\t$offset");
288 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
289 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
290 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
291 dag OutOperandList = (outs);
292 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
293 list<Register> Defs = [AT];
296 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
297 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
298 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
299 dag OutOperandList = (outs);
300 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
301 list<Register> Defs = [AT];
304 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
305 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
306 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
307 dag OutOperandList = (outs);
308 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
309 list<Register> Defs = [AT];
312 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
314 list<Register> Defs = [RA];
317 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
318 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
319 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
320 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
321 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
323 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
324 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
326 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
327 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
329 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
330 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
332 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
333 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
334 dag OutOperandList = (outs);
335 string AsmString = instr_asm;
336 bit hasDelaySlot = 1;
339 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
340 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
342 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
343 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
344 dag OutOperandList = (outs);
345 string AsmString = instr_asm;
346 bit hasDelaySlot = 1;
349 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
350 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
352 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
353 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
355 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
356 RegisterOperand GPROpnd> {
357 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
358 string AsmString = !strconcat(opstr, "\t$rt, $offset");
359 list<dag> Pattern = [];
360 bit isTerminator = 1;
361 bit hasDelaySlot = 0;
362 string DecoderMethod = "DecodeSimm16";
365 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
368 list<Register> Defs = [RA];
371 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
373 list<Register> Defs = [AT];
376 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
378 bit isIndirectBranch = 1;
379 bit hasDelaySlot = 1;
384 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
385 dag OutOperandList = (outs GPROpnd:$rd);
386 dag InOperandList = (ins GPROpnd:$rt);
387 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
388 list<dag> Pattern = [];
391 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
393 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
394 SDPatternOperator Op=null_frag> {
395 dag OutOperandList = (outs GPROpnd:$rd);
396 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
397 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
398 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
400 // This instruction doesn't trap division by zero itself. We must insert
401 // teq instructions as well.
402 bit usesCustomInserter = 1;
405 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
406 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
407 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
408 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
410 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
411 list<Register> Defs = [RA];
414 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
415 list<Register> Defs = [RA];
418 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
419 list<Register> Defs = [RA];
422 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
423 list<Register> Defs = [RA];
426 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
427 list<Register> Defs = [RA];
430 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
431 list<Register> Defs = [RA];
434 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
435 SDPatternOperator Op=null_frag> {
436 dag OutOperandList = (outs GPROpnd:$rd);
437 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
438 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
439 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
442 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
443 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
444 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
445 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
447 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
448 dag OutOperandList = (outs FGROpnd:$fd);
449 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
450 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
451 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
454 string Constraints = "$fd_in = $fd";
457 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
458 // We must insert a SUBREG_TO_REG around $fd_in
459 bit usesCustomInserter = 1;
461 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
463 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
464 dag OutOperandList = (outs GPROpnd:$rd);
465 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
466 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
467 list<dag> Pattern = [];
470 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
471 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
473 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
474 dag OutOperandList = (outs FGROpnd:$fd);
475 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
476 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
477 list<dag> Pattern = [];
478 string Constraints = "$fd_in = $fd";
481 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
482 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
483 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
484 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
486 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
487 dag OutOperandList = (outs FGROpnd:$fd);
488 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
489 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
490 list<dag> Pattern = [];
493 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
494 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
495 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
496 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
498 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
499 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
500 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
501 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
503 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
504 dag OutOperandList = (outs FGROpnd:$fd);
505 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
506 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
507 list<dag> Pattern = [];
510 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
511 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
512 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
513 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
515 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
516 dag OutOperandList = (outs FGROpnd:$fd);
517 dag InOperandList = (ins FGROpnd:$fs);
518 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
519 list<dag> Pattern = [];
522 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
523 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
524 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
525 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
527 //===----------------------------------------------------------------------===//
529 // Instruction Definitions
531 //===----------------------------------------------------------------------===//
533 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
534 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
535 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
536 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
537 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
538 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
539 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
540 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
541 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
542 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
543 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
544 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
545 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
546 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
547 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
548 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
549 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
550 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
551 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
552 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
553 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
554 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
555 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
556 def BLTC; // Also aliased to bgtc with operands swapped
557 def BLTUC; // Also aliased to bgtuc with operands swapped
558 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
559 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
560 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
561 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
562 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
563 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
564 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
565 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
566 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
567 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
568 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
569 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
570 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
571 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
572 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
573 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
574 // def LSA; // See MSA
575 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
576 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
577 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
578 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
579 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
580 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
581 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
582 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
583 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
584 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
585 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
586 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
587 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
588 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
589 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
590 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
591 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
592 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
593 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
594 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
595 def NAL; // BAL with rd=0
596 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
597 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
598 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
599 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
600 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
601 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
602 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
603 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
604 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
605 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
607 //===----------------------------------------------------------------------===//
609 // Patterns and Pseudo Instructions
611 //===----------------------------------------------------------------------===//
613 // f32 comparisons supported via another comparison
614 def : MipsPat<(setone f32:$lhs, f32:$rhs),
615 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
616 def : MipsPat<(seto f32:$lhs, f32:$rhs),
617 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
618 def : MipsPat<(setune f32:$lhs, f32:$rhs),
619 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
620 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
622 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
624 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
626 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
628 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
630 def : MipsPat<(setne f32:$lhs, f32:$rhs),
631 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
633 // f64 comparisons supported via another comparison
634 def : MipsPat<(setone f64:$lhs, f64:$rhs),
635 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
636 def : MipsPat<(seto f64:$lhs, f64:$rhs),
637 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
638 def : MipsPat<(setune f64:$lhs, f64:$rhs),
639 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
640 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
642 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
644 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
646 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
648 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
650 def : MipsPat<(setne f64:$lhs, f64:$rhs),
651 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
654 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
655 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
657 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
658 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
660 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
661 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
663 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
664 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
665 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
667 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
668 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
669 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
671 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
673 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
674 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
676 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
678 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
679 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
682 def : MipsPat<(select i32:$cond, i32:$t, immz),
683 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
684 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
685 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
686 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
687 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
688 def : MipsPat<(select i32:$cond, immz, i32:$f),
689 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
690 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
691 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
692 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
693 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;