1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
33 // Removed: bc[12][ft]l, bgezl, bgtzl, bgtzl, blezl, bltzall, bltzl, bnel, bgezall,
37 // Removed: c.cond.fmt, bc1[ft]
42 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
44 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
45 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
46 // Removed: movf, movt
47 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
48 // Removed: movn, movz
49 // Removed: mult, multu
54 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
55 // Rencoded: [ls][wd]c2
57 //===----------------------------------------------------------------------===//
59 // Instruction Encodings
61 //===----------------------------------------------------------------------===//
63 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
64 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
65 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
66 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
67 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
68 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
69 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
70 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
72 //===----------------------------------------------------------------------===//
74 // Instruction Descriptions
76 //===----------------------------------------------------------------------===//
78 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
79 dag OutOperandList = (outs GPROpnd:$rd);
80 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
81 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
82 list<dag> Pattern = [];
85 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
86 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
87 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
88 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
90 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
91 dag OutOperandList = (outs GPROpnd:$rd);
92 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
93 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
94 list<dag> Pattern = [];
97 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
98 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
99 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
100 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
102 //===----------------------------------------------------------------------===//
104 // Instruction Definitions
106 //===----------------------------------------------------------------------===//
109 def ALIGN; // Known as as BALIGN in DSP ASE
122 def BGEC; // Also aliased to blec with operands swapped
123 def BGEUC; // Also aliased to bleuc with operands swapped
128 def BITSWAP; // Known as BITREV in DSP ASE
131 def BLTC; // Also aliased to bgtc with operands swapped
132 def BLTUC; // Also aliased to bgtuc with operands swapped
144 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
145 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
148 // def LSA; // See MSA
159 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
160 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
162 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
163 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
164 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
165 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
166 def NAL; // BAL with rd=0