1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
67 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
68 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
69 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
70 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
71 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
72 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
73 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
74 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
75 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
76 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
78 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
79 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
80 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
81 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
83 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
84 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
85 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
86 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
88 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
89 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
90 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
91 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
93 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
94 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
95 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
96 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
98 //===----------------------------------------------------------------------===//
100 // Instruction Descriptions
102 //===----------------------------------------------------------------------===//
104 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
105 dag OutOperandList = (outs GPROpnd:$rs);
106 dag InOperandList = (ins simm19_lsl2:$imm);
107 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
108 list<dag> Pattern = [];
111 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
113 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
115 dag OutOperandList = (outs GPROpnd:$rd);
116 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
117 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
118 list<dag> Pattern = [];
121 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
123 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
124 dag OutOperandList = (outs GPROpnd:$rs);
125 dag InOperandList = (ins simm16:$imm);
126 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
127 list<dag> Pattern = [];
130 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
131 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
133 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
134 dag OutOperandList = (outs GPROpnd:$rs);
135 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
136 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
137 list<dag> Pattern = [];
140 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
142 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
143 dag OutOperandList = (outs GPROpnd:$rd);
144 dag InOperandList = (ins GPROpnd:$rt);
145 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
146 list<dag> Pattern = [];
149 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
151 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
152 dag OutOperandList = (outs GPROpnd:$rd);
153 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
154 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
155 list<dag> Pattern = [];
158 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
159 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
160 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
161 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
163 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
164 dag OutOperandList = (outs GPROpnd:$rd);
165 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
166 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
167 list<dag> Pattern = [];
170 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
171 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
172 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
173 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
175 class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
176 dag OutOperandList = (outs FGROpnd:$fd);
177 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
178 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
179 list<dag> Pattern = [];
180 string Constraints = "$fd_in = $fd";
183 class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
184 class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
186 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
187 dag OutOperandList = (outs FGROpnd:$fd);
188 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
189 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
190 list<dag> Pattern = [];
193 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
194 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
195 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
196 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
198 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
199 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
200 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
201 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
203 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
204 dag OutOperandList = (outs FGROpnd:$fd);
205 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
206 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
207 list<dag> Pattern = [];
210 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
211 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
212 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
213 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
215 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
216 dag OutOperandList = (outs FGROpnd:$fd);
217 dag InOperandList = (ins FGROpnd:$fs);
218 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
219 list<dag> Pattern = [];
222 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
223 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
224 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
225 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
227 //===----------------------------------------------------------------------===//
229 // Instruction Definitions
231 //===----------------------------------------------------------------------===//
233 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
234 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
235 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
236 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
237 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
247 def BGEC; // Also aliased to blec with operands swapped
248 def BGEUC; // Also aliased to bleuc with operands swapped
253 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
256 def BLTC; // Also aliased to bgtc with operands swapped
257 def BLTUC; // Also aliased to bgtuc with operands swapped
265 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
266 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
269 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
270 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
273 // def LSA; // See MSA
277 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
278 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
279 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
280 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
281 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
282 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
283 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
284 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
285 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
286 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
288 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
289 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
290 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
291 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
292 def NAL; // BAL with rd=0
293 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
294 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
296 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
297 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
299 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
300 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
301 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
302 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;