2 //===-- Mips16RegisterInfo.cpp - MIPS16 Register Information -== ----------===//
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the MIPS16 implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "Mips16RegisterInfo.h"
16 #include "Mips16InstrInfo.h"
18 #include "Mips16InstrInfo.h"
19 #include "MipsAnalyzeImmediate.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsSubtarget.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/DebugInfo.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetFrameLowering.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
45 Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST,
46 const Mips16InstrInfo &I)
47 : MipsRegisterInfo(ST), TII(I) {}
49 bool Mips16RegisterInfo::requiresRegisterScavenging
50 (const MachineFunction &MF) const {
53 bool Mips16RegisterInfo::requiresFrameIndexScavenging
54 (const MachineFunction &MF) const {
58 bool Mips16RegisterInfo::useFPForScavengingIndex
59 (const MachineFunction &MF) const {
63 bool Mips16RegisterInfo::saveScavengerRegister
64 (MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator I,
66 MachineBasicBlock::iterator &UseMI,
67 const TargetRegisterClass *RC,
70 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
71 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
75 void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
76 unsigned OpNo, int FrameIndex,
78 int64_t SPOffset) const {
79 MachineInstr &MI = *II;
80 MachineFunction &MF = *MI.getParent()->getParent();
81 MachineFrameInfo *MFI = MF.getFrameInfo();
83 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
88 MinCSFI = CSI[0].getFrameIdx();
89 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
92 // The following stack frame objects are always
93 // referenced relative to $sp:
94 // 1. Outgoing arguments.
95 // 2. Pointer to dynamically allocated stack space.
96 // 3. Locations for callee-saved registers.
97 // Everything else is referenced relative to whatever register
98 // getFrameRegister() returns.
101 if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
104 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
105 if (TFI->hasFP(MF)) {
109 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
110 FrameReg = MI.getOperand(OpNo+2).getReg();
115 // Calculate final offset.
116 // - There is no need to change the offset if the frame object
118 // following: an outgoing argument, pointer to a dynamically allocated
119 // stack space or a $gp restore location,
120 // - If the frame object is any of the following,
121 // its offset must be adjusted
122 // by adding the size of the stack:
123 // incoming argument, callee-saved register location or local variable.
126 Offset = SPOffset + (int64_t)StackSize;
127 Offset += MI.getOperand(OpNo + 1).getImm();
130 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
132 if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) ||
133 ((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) {
134 MachineBasicBlock &MBB = *MI.getParent();
135 DebugLoc DL = II->getDebugLoc();
137 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
138 Offset = SignExtend64<16>(NewImm);
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
142 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);