1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class F2RI16_ins<bits<5> _op, string asmstr,
65 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
66 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
67 let Constraints = "$rx_ = $rx";
71 // Compare a register and immediate and place result in CC
74 // EXT-CCRR Instruction format
76 class FEXT_CCRXI16_ins<string asmstr>:
77 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
78 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
82 // JAL and JALX instruction format
84 class FJAL16_ins<bits<1> _X, string asmstr,
86 FJAL16<_X, (outs), (ins simm20:$imm),
87 !strconcat(asmstr, "\t$imm\n\tnop"),[],
92 // EXT-I instruction format
94 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
95 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
96 !strconcat(asmstr, "\t$imm16"),[], itin>;
99 // EXT-I8 instruction format
102 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
103 string asmstr2, InstrItinClass itin>:
104 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
107 class FEXT_I816_ins<bits<3> _func, string asmstr,
108 InstrItinClass itin>:
109 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
111 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
112 InstrItinClass itin>:
113 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
116 // Assembler formats in alphabetical order.
117 // Natural and pseudos are mixed together.
119 // Compare two registers and place result in CC
120 // Implicit use of T8
122 // CC-RR Instruction format
124 class FCCRR16_ins<string asmstr> :
125 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
126 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
131 // EXT-RI instruction format
134 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
135 InstrItinClass itin>:
136 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
137 !strconcat(asmstr, asmstr2), [], itin>;
139 class FEXT_RI16_ins<bits<5> _op, string asmstr,
140 InstrItinClass itin>:
141 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
143 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
144 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
146 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
147 InstrItinClass itin>:
148 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
149 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
151 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
152 InstrItinClass itin>:
153 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
154 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
155 let Constraints = "$rx_ = $rx";
159 // this has an explicit sp argument that we ignore to work around a problem
161 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
162 InstrItinClass itin>:
163 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
164 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
167 // EXT-RRI instruction format
170 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
171 InstrItinClass itin>:
172 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
173 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
175 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
176 InstrItinClass itin>:
177 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
178 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
182 // EXT-RRI-A instruction format
185 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
186 InstrItinClass itin>:
187 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
188 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
191 // EXT-SHIFT instruction format
193 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
194 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
195 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
200 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
202 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
203 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
204 !strconcat(asmstr, "\t$imm"))),[]> {
211 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
213 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
214 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
215 !strconcat(asmstr, "\t$targ"))), []> {
222 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
224 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
225 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
226 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
229 // I8_MOV32R instruction format (used only by MOV32R instruction)
232 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
233 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
234 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
237 // This are pseudo formats for multiply
238 // This first one can be changed to non pseudo now.
242 class FMULT16_ins<string asmstr, InstrItinClass itin> :
243 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
244 !strconcat(asmstr, "\t$rx, $ry"), []>;
249 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
250 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
251 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
256 // RR-type instruction format
259 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
260 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
261 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
264 class FRRTR16_ins<string asmstr> :
265 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
266 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
269 // maybe refactor but need a $zero as a dummy first parameter
271 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
272 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
273 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
275 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
276 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
277 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
280 class FRR16_M_ins<bits<5> f, string asmstr,
281 InstrItinClass itin> :
282 FRR16<f, (outs CPU16Regs:$rx), (ins),
283 !strconcat(asmstr, "\t$rx"), [], itin>;
285 class FRxRxRy16_ins<bits<5> f, string asmstr,
286 InstrItinClass itin> :
287 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
288 !strconcat(asmstr, "\t$rz, $ry"),
290 let Constraints = "$rx = $rz";
294 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
295 string asmstr, InstrItinClass itin>:
296 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
300 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
301 string asmstr, InstrItinClass itin>:
302 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
303 !strconcat(asmstr, "\t $rx"), [], itin> ;
306 // RRR-type instruction format
309 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
310 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
311 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
314 // These Sel patterns support the generation of conditional move
315 // pseudo instructions.
317 // The nomenclature uses the components making up the pseudo and may
318 // be a bit counter intuitive when compared with the end result we seek.
319 // For example using a bqez in the example directly below results in the
320 // conditional move being done if the tested register is not zero.
321 // I considered in easier to check by keeping the pseudo consistent with
322 // it's components but it could have been done differently.
324 // The simplest case is when can test and operand directly and do the
325 // conditional move based on a simple mips16 conditional
326 // branch instruction.
328 // if $op == beqz or bnez:
333 // if $op == beqz, then if $rt != 0, then the conditional assignment
334 // $rd = $rs is done.
336 // if $op == bnez, then if $rt == 0, then the conditional assignment
337 // $rd = $rs is done.
339 // So this pseudo class only has one operand, i.e. op
341 class Sel<string op>:
342 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
344 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
345 //let isCodeGenOnly=1;
346 let Constraints = "$rd = $rd_";
350 // The next two instruction classes allow for an operand which tests
351 // two operands and returns a value in register T8 and
352 //then does a conditional branch based on the value of T8
355 // op2 can be cmpi or slti/sltiu
356 // op1 can bteqz or btnez
357 // the operands for op2 are a register and a signed constant
359 // $op2 $t, $imm ;test register t and branch conditionally
360 // $op1 .+4 ;op1 is a conditional branch
364 class SeliT<string op1, string op2>:
365 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
366 CPU16Regs:$rl, simm16:$imm),
368 !strconcat("\t$rl, $imm\n\t",
369 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
371 let Constraints = "$rd = $rd_";
375 // op2 can be cmp or slt/sltu
376 // op1 can be bteqz or btnez
377 // the operands for op2 are two registers
378 // op1 is a conditional branch
381 // $op2 $rl, $rr ;test registers rl,rr
382 // $op1 .+4 ;op2 is a conditional branch
386 class SelT<string op1, string op2>:
387 MipsPseudo16<(outs CPU16Regs:$rd_),
388 (ins CPU16Regs:$rd, CPU16Regs:$rs,
389 CPU16Regs:$rl, CPU16Regs:$rr),
391 !strconcat("\t$rl, $rr\n\t",
392 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
394 let Constraints = "$rd = $rd_";
400 def imm32: Operand<i32>;
403 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
406 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
407 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
411 // Some general instruction class info
415 class ArithLogic16Defs<bit isCom=0> {
417 bit isCommutable = isCom;
418 bit isReMaterializable = 1;
419 bit neverHasSideEffects = 1;
424 bit isTerminator = 1;
430 bit isTerminator = 1;
443 // Format: ADDIU rx, immediate MIPS16e
444 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
445 // To add a constant to a 32-bit integer.
447 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
449 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
450 ArithLogic16Defs<0> {
451 let AddedComplexity = 5;
453 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
454 ArithLogic16Defs<0> {
455 let isCodeGenOnly = 1;
458 def AddiuRxRyOffMemX16:
459 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
463 // Format: ADDIU rx, pc, immediate MIPS16e
464 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
465 // To add a constant to the program counter.
467 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
470 // Format: ADDIU sp, immediate MIPS16e
471 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
472 // To add a constant to the stack pointer.
475 : FI816_SP_ins<0b011, "addiu", IIAlu> {
478 let AddedComplexity = 5;
482 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
488 // Format: ADDU rz, rx, ry MIPS16e
489 // Purpose: Add Unsigned Word (3-Operand)
490 // To add 32-bit integers.
493 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
496 // Format: AND rx, ry MIPS16e
498 // To do a bitwise logical AND.
500 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
504 // Format: BEQZ rx, offset MIPS16e
505 // Purpose: Branch on Equal to Zero (Extended)
506 // To test a GPR then do a PC-relative conditional branch.
508 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
510 // Format: B offset MIPS16e
511 // Purpose: Unconditional Branch
512 // To do an unconditional PC-relative branch.
514 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
517 // Format: BNEZ rx, offset MIPS16e
518 // Purpose: Branch on Not Equal to Zero (Extended)
519 // To test a GPR then do a PC-relative conditional branch.
521 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
524 // Format: BTEQZ offset MIPS16e
525 // Purpose: Branch on T Equal to Zero (Extended)
526 // To test special register T then do a PC-relative conditional branch.
528 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
532 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
534 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
537 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
539 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
541 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
543 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
547 // Format: BTNEZ offset MIPS16e
548 // Purpose: Branch on T Not Equal to Zero (Extended)
549 // To test special register T then do a PC-relative conditional branch.
551 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
555 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
557 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
559 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
561 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
563 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
565 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
569 // Format: CMP rx, ry MIPS16e
571 // To compare the contents of two GPRs.
573 def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> {
578 // Format: CMPI rx, immediate MIPS16e
579 // Purpose: Compare Immediate
580 // To compare a constant with the contents of a GPR.
582 def CmpiRxImm16: FRI16_ins<0b01110, "cmpi", IIAlu> {
587 // Format: CMPI rx, immediate MIPS16e
588 // Purpose: Compare Immediate (Extended)
589 // To compare a constant with the contents of a GPR.
591 def CmpiRxImmX16: FEXT_RI16_ins<0b01110, "cmpi", IIAlu> {
597 // Format: DIV rx, ry MIPS16e
598 // Purpose: Divide Word
599 // To divide 32-bit signed integers.
601 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
606 // Format: DIVU rx, ry MIPS16e
607 // Purpose: Divide Unsigned Word
608 // To divide 32-bit unsigned integers.
610 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
614 // Format: JAL target MIPS16e
615 // Purpose: Jump and Link
616 // To execute a procedure call within the current 256 MB-aligned
617 // region and preserve the current ISA.
620 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
622 let hasDelaySlot = 0; // not true, but we add the nop for now
628 // Format: JR ra MIPS16e
629 // Purpose: Jump Register Through Register ra
630 // To execute a branch to the instruction address in the return
634 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
636 let isIndirectBranch = 1;
637 let hasDelaySlot = 1;
642 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
644 let isIndirectBranch = 1;
649 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
651 let isIndirectBranch = 1;
656 // Format: LB ry, offset(rx) MIPS16e
657 // Purpose: Load Byte (Extended)
658 // To load a byte from memory as a signed value.
660 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
661 let isCodeGenOnly = 1;
665 // Format: LBU ry, offset(rx) MIPS16e
666 // Purpose: Load Byte Unsigned (Extended)
667 // To load a byte from memory as a unsigned value.
669 def LbuRxRyOffMemX16:
670 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
671 let isCodeGenOnly = 1;
675 // Format: LH ry, offset(rx) MIPS16e
676 // Purpose: Load Halfword signed (Extended)
677 // To load a halfword from memory as a signed value.
679 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
680 let isCodeGenOnly = 1;
684 // Format: LHU ry, offset(rx) MIPS16e
685 // Purpose: Load Halfword unsigned (Extended)
686 // To load a halfword from memory as an unsigned value.
688 def LhuRxRyOffMemX16:
689 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
690 let isCodeGenOnly = 1;
694 // Format: LI rx, immediate MIPS16e
695 // Purpose: Load Immediate (Extended)
696 // To load a constant into a GPR.
698 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
701 // Format: LW ry, offset(rx) MIPS16e
702 // Purpose: Load Word (Extended)
703 // To load a word from memory as a signed value.
705 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
706 let isCodeGenOnly = 1;
709 // Format: LW rx, offset(sp) MIPS16e
710 // Purpose: Load Word (SP-Relative, Extended)
711 // To load an SP-relative word from memory as a signed value.
713 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
718 // Format: MOVE r32, rz MIPS16e
720 // To move the contents of a GPR to a GPR.
722 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
725 // Format: MOVE ry, r32 MIPS16e
727 // To move the contents of a GPR to a GPR.
729 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
732 // Format: MFHI rx MIPS16e
733 // Purpose: Move From HI Register
734 // To copy the special purpose HI register to a GPR.
736 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
738 let neverHasSideEffects = 1;
742 // Format: MFLO rx MIPS16e
743 // Purpose: Move From LO Register
744 // To copy the special purpose LO register to a GPR.
746 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
748 let neverHasSideEffects = 1;
752 // Pseudo Instruction for mult
754 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
755 let isCommutable = 1;
756 let neverHasSideEffects = 1;
760 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
761 let isCommutable = 1;
762 let neverHasSideEffects = 1;
767 // Format: MULT rx, ry MIPS16e
768 // Purpose: Multiply Word
769 // To multiply 32-bit signed integers.
771 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
772 let isCommutable = 1;
773 let neverHasSideEffects = 1;
778 // Format: MULTU rx, ry MIPS16e
779 // Purpose: Multiply Unsigned Word
780 // To multiply 32-bit unsigned integers.
782 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
783 let isCommutable = 1;
784 let neverHasSideEffects = 1;
789 // Format: NEG rx, ry MIPS16e
791 // To negate an integer value.
793 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
796 // Format: NOT rx, ry MIPS16e
798 // To complement an integer value
800 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
803 // Format: OR rx, ry MIPS16e
805 // To do a bitwise logical OR.
807 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
810 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
811 // (All args are optional) MIPS16e
812 // Purpose: Restore Registers and Deallocate Stack Frame
813 // To deallocate a stack frame before exit from a subroutine,
814 // restoring return address and static registers, and adjusting
818 // fixed form for restoring RA and the frame
819 // for direct object emitter, encoding needs to be adjusted for the
822 let ra=1, s=0,s0=1,s1=1 in
824 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
825 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
826 let isCodeGenOnly = 1;
827 let Defs = [S0, S1, RA, SP];
831 // Use Restore to increment SP since SP is not a Mip 16 register, this
832 // is an easy way to do that which does not require a register.
834 let ra=0, s=0,s0=0,s1=0 in
836 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
837 "restore\t$frame_size", [], IILoad >, MayLoad {
838 let isCodeGenOnly = 1;
844 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
846 // Purpose: Save Registers and Set Up Stack Frame
847 // To set up a stack frame on entry to a subroutine,
848 // saving return address and static registers, and adjusting stack
850 let ra=1, s=1,s0=1,s1=1 in
852 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
853 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
854 let isCodeGenOnly = 1;
855 let Uses = [RA, SP, S0, S1];
860 // Use Save to decrement the SP by a constant since SP is not
861 // a Mips16 register.
863 let ra=0, s=0,s0=0,s1=0 in
865 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
866 "save\t$frame_size", [], IIStore >, MayStore {
867 let isCodeGenOnly = 1;
872 // Format: SB ry, offset(rx) MIPS16e
873 // Purpose: Store Byte (Extended)
874 // To store a byte to memory.
877 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
880 // The Sel(T) instructions are pseudos
881 // T means that they use T8 implicitly.
884 // Format: SelBeqZ rd, rs, rt
885 // Purpose: if rt==0, do nothing
888 def SelBeqZ: Sel<"beqz">;
891 // Format: SelTBteqZCmp rd, rs, rl, rr
892 // Purpose: b = Cmp rl, rr.
893 // If b==0 then do nothing.
894 // if b!=0 then rd = rs
896 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
899 // Format: SelTBteqZCmpi rd, rs, rl, rr
900 // Purpose: b = Cmpi rl, imm.
901 // If b==0 then do nothing.
902 // if b!=0 then rd = rs
904 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
907 // Format: SelTBteqZSlt rd, rs, rl, rr
908 // Purpose: b = Slt rl, rr.
909 // If b==0 then do nothing.
910 // if b!=0 then rd = rs
912 def SelTBteqZSlt: SelT<"bteqz", "slt">;
915 // Format: SelTBteqZSlti rd, rs, rl, rr
916 // Purpose: b = Slti rl, imm.
917 // If b==0 then do nothing.
918 // if b!=0 then rd = rs
920 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
923 // Format: SelTBteqZSltu rd, rs, rl, rr
924 // Purpose: b = Sltu rl, rr.
925 // If b==0 then do nothing.
926 // if b!=0 then rd = rs
928 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
931 // Format: SelTBteqZSltiu rd, rs, rl, rr
932 // Purpose: b = Sltiu rl, imm.
933 // If b==0 then do nothing.
934 // if b!=0 then rd = rs
936 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
939 // Format: SelBnez rd, rs, rt
940 // Purpose: if rt!=0, do nothing
943 def SelBneZ: Sel<"bnez">;
946 // Format: SelTBtneZCmp rd, rs, rl, rr
947 // Purpose: b = Cmp rl, rr.
948 // If b!=0 then do nothing.
949 // if b0=0 then rd = rs
951 def SelTBtneZCmp: SelT<"btnez", "cmp">;
954 // Format: SelTBtnezCmpi rd, rs, rl, rr
955 // Purpose: b = Cmpi rl, imm.
956 // If b!=0 then do nothing.
957 // if b==0 then rd = rs
959 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
962 // Format: SelTBtneZSlt rd, rs, rl, rr
963 // Purpose: b = Slt rl, rr.
964 // If b!=0 then do nothing.
965 // if b==0 then rd = rs
967 def SelTBtneZSlt: SelT<"btnez", "slt">;
970 // Format: SelTBtneZSlti rd, rs, rl, rr
971 // Purpose: b = Slti rl, imm.
972 // If b!=0 then do nothing.
973 // if b==0 then rd = rs
975 def SelTBtneZSlti: SeliT<"btnez", "slti">;
978 // Format: SelTBtneZSltu rd, rs, rl, rr
979 // Purpose: b = Sltu rl, rr.
980 // If b!=0 then do nothing.
981 // if b==0 then rd = rs
983 def SelTBtneZSltu: SelT<"btnez", "sltu">;
986 // Format: SelTBtneZSltiu rd, rs, rl, rr
987 // Purpose: b = Slti rl, imm.
988 // If b!=0 then do nothing.
989 // if b==0 then rd = rs
991 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
994 // Format: SH ry, offset(rx) MIPS16e
995 // Purpose: Store Halfword (Extended)
996 // To store a halfword to memory.
999 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1002 // Format: SLL rx, ry, sa MIPS16e
1003 // Purpose: Shift Word Left Logical (Extended)
1004 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1006 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1009 // Format: SLLV ry, rx MIPS16e
1010 // Purpose: Shift Word Left Logical Variable
1011 // To execute a left-shift of a word by a variable number of bits.
1013 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1016 // Format: SLTI rx, immediate MIPS16e
1017 // Purpose: Set on Less Than Immediate (Extended)
1018 // To record the result of a less-than comparison with a constant.
1020 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1023 // Format: SLTIU rx, immediate MIPS16e
1024 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1025 // To record the result of a less-than comparison with a constant.
1027 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1030 // Format: SLT rx, ry MIPS16e
1031 // Purpose: Set on Less Than
1032 // To record the result of a less-than comparison.
1034 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
1036 def SltCCRxRy16: FCCRR16_ins<"slt">;
1038 // Format: SLTU rx, ry MIPS16e
1039 // Purpose: Set on Less Than Unsigned
1040 // To record the result of an unsigned less-than comparison.
1042 def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
1044 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1045 let isCodeGenOnly=1;
1049 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1051 // Format: SRAV ry, rx MIPS16e
1052 // Purpose: Shift Word Right Arithmetic Variable
1053 // To execute an arithmetic right-shift of a word by a variable
1056 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1060 // Format: SRA rx, ry, sa MIPS16e
1061 // Purpose: Shift Word Right Arithmetic (Extended)
1062 // To execute an arithmetic right-shift of a word by a fixed
1063 // number of bits—1 to 8 bits.
1065 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1069 // Format: SRLV ry, rx MIPS16e
1070 // Purpose: Shift Word Right Logical Variable
1071 // To execute a logical right-shift of a word by a variable
1074 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1078 // Format: SRL rx, ry, sa MIPS16e
1079 // Purpose: Shift Word Right Logical (Extended)
1080 // To execute a logical right-shift of a word by a fixed
1081 // number of bits—1 to 31 bits.
1083 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1086 // Format: SUBU rz, rx, ry MIPS16e
1087 // Purpose: Subtract Unsigned Word
1088 // To subtract 32-bit integers
1090 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1093 // Format: SW ry, offset(rx) MIPS16e
1094 // Purpose: Store Word (Extended)
1095 // To store a word to memory.
1097 def SwRxRyOffMemX16:
1098 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1101 // Format: SW rx, offset(sp) MIPS16e
1102 // Purpose: Store Word rx (SP-Relative)
1103 // To store an SP-relative word to memory.
1105 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1109 // Format: XOR rx, ry MIPS16e
1111 // To do a bitwise logical XOR.
1113 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1115 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1116 let Predicates = [InMips16Mode];
1119 // Unary Arith/Logic
1121 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1122 Mips16Pat<(OpNode CPU16Regs:$r),
1125 def: ArithLogicU_pat<not, NotRxRy16>;
1126 def: ArithLogicU_pat<ineg, NegRxRy16>;
1128 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1129 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1130 (I CPU16Regs:$l, CPU16Regs:$r)>;
1132 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1133 def: ArithLogic16_pat<and, AndRxRxRy16>;
1134 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1135 def: ArithLogic16_pat<or, OrRxRxRy16>;
1136 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1137 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1139 // Arithmetic and logical instructions with 2 register operands.
1141 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1142 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1143 (I CPU16Regs:$in, imm_type:$imm)>;
1145 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1146 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1147 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1148 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1149 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1151 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1152 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1153 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1155 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1156 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1157 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1159 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1160 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1162 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1163 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1164 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1165 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1166 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1168 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1169 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1170 (I CPU16Regs:$r, addr16:$addr)>;
1172 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1173 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1174 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1176 // Unconditional branch
1177 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1178 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1179 let Predicates = [InMips16Mode];
1182 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1183 (Jal16 tglobaladdr:$dst)>;
1185 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1186 (Jal16 texternalsym:$dst)>;
1190 (brind CPU16Regs:$rs),
1191 (JrcRx16 CPU16Regs:$rs)>;
1193 // Jump and Link (Call)
1194 let isCall=1, hasDelaySlot=0 in
1196 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1197 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1200 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1201 hasExtraSrcRegAllocReq = 1 in
1202 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1207 class SetCC_R16<PatFrag cond_op, Instruction I>:
1208 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1209 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1211 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1212 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1213 (I CPU16Regs:$rx, imm_type:$imm16)>;
1216 def: Mips16Pat<(i32 addr16:$addr),
1217 (AddiuRxRyOffMemX16 addr16:$addr)>;
1220 // Large (>16 bit) immediate loads
1221 def : Mips16Pat<(i32 imm:$imm),
1222 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1223 (LiRxImmX16 (LO16 imm:$imm)))>;
1225 // Carry MipsPatterns
1226 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1227 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1228 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1229 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1230 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1231 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1234 // Some branch conditional patterns are not generated by llvm at this time.
1235 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1236 // comparison they are used and for unsigned a different pattern is used.
1237 // I am pushing upstream from the full mips16 port and it seemed that I needed
1238 // these earlier and the mips32 port has these but now I cannot create test
1239 // cases that use these patterns. While I sort this all out I will leave these
1240 // extra patterns commented out and if I can be sure they are really not used,
1241 // I will delete the code. I don't want to check the code in uncommented without
1242 // a valid test case. In some cases, the compiler is generating patterns with
1243 // setcc instead and earlier I had implemented setcc first so may have masked
1244 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1245 // figure out how to enable the brcond patterns or else possibly new
1246 // combinations of of brcond and setcc.
1252 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1253 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1258 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1259 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1263 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1264 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1268 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1271 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1272 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1279 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1280 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1284 // never called because compiler transforms a >= k to a > (k-1)
1286 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1287 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1294 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1295 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1299 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1300 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1307 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1308 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1315 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1316 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1320 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1321 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1325 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1326 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1330 // This needs to be there but I forget which code will generate it
1333 <(brcond CPU16Regs:$rx, bb:$targ16),
1334 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1343 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1344 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1351 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1352 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1360 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1361 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1364 def: UncondBranch16_pat<br, BimmX16>;
1367 def: Mips16Pat<(i32 immSExt16:$in),
1368 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1370 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1376 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1377 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1383 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1384 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1389 // if !(a < b) x = y
1391 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1392 CPU16Regs:$x, CPU16Regs:$y),
1393 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1394 CPU16Regs:$a, CPU16Regs:$b)>;
1401 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1402 CPU16Regs:$x, CPU16Regs:$y),
1403 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1404 CPU16Regs:$b, CPU16Regs:$a)>;
1409 // if !(a < b) x = y;
1412 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1413 CPU16Regs:$x, CPU16Regs:$y),
1414 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1415 CPU16Regs:$a, CPU16Regs:$b)>;
1422 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1423 CPU16Regs:$x, CPU16Regs:$y),
1424 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1425 CPU16Regs:$b, CPU16Regs:$a)>;
1429 // due to an llvm optimization, i don't think that this will ever
1430 // be used. This is transformed into x = (a > k-1)?x:y
1435 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1436 // CPU16Regs:$T, CPU16Regs:$F),
1437 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1438 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1441 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1442 // CPU16Regs:$T, CPU16Regs:$F),
1443 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1444 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1449 // if !(a < k) x = y;
1452 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1453 CPU16Regs:$x, CPU16Regs:$y),
1454 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1455 CPU16Regs:$a, immSExt16:$b)>;
1461 // x = (a <= b)? x : y
1465 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1466 CPU16Regs:$x, CPU16Regs:$y),
1467 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1468 CPU16Regs:$b, CPU16Regs:$a)>;
1472 // x = (a <= b)? x : y
1476 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1477 CPU16Regs:$x, CPU16Regs:$y),
1478 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1479 CPU16Regs:$b, CPU16Regs:$a)>;
1483 // x = (a == b)? x : y
1485 // if (a != b) x = y
1487 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1488 CPU16Regs:$x, CPU16Regs:$y),
1489 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1490 CPU16Regs:$b, CPU16Regs:$a)>;
1494 // x = (a == 0)? x : y
1496 // if (a != 0) x = y
1498 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1499 CPU16Regs:$x, CPU16Regs:$y),
1500 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1506 // x = (a == k)? x : y
1508 // if (a != k) x = y
1510 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1511 CPU16Regs:$x, CPU16Regs:$y),
1512 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1513 CPU16Regs:$a, immZExt16:$k)>;
1518 // x = (a != b)? x : y
1520 // if (a == b) x = y
1523 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1524 CPU16Regs:$x, CPU16Regs:$y),
1525 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1526 CPU16Regs:$b, CPU16Regs:$a)>;
1530 // x = (a != 0)? x : y
1532 // if (a == 0) x = y
1534 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1535 CPU16Regs:$x, CPU16Regs:$y),
1536 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1544 def : Mips16Pat<(select CPU16Regs:$a,
1545 CPU16Regs:$x, CPU16Regs:$y),
1546 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1552 // x = (a != k)? x : y
1554 // if (a == k) x = y
1556 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1557 CPU16Regs:$x, CPU16Regs:$y),
1558 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1559 CPU16Regs:$a, immZExt16:$k)>;
1562 // When writing C code to test setxx these patterns,
1563 // some will be transformed into
1564 // other things. So we test using C code but using -O3 and -O0
1569 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1570 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1573 <(seteq CPU16Regs:$lhs, 0),
1574 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1582 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1583 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1587 // For constants, llvm transforms this to:
1588 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1589 // is not used now by the compiler. (Presumably checking that k-1 does not
1590 // overflow). The compiler never uses this at a the current time, due to
1591 // other optimizations.
1594 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1595 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1596 // (LiRxImmX16 1))>;
1598 // This catches the x >= -32768 case by transforming it to x > -32769
1601 <(setgt CPU16Regs:$lhs, -32769),
1602 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1611 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1612 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1618 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1619 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1624 def: SetCC_R16<setlt, SltCCRxRy16>;
1626 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1632 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1633 (SltuCCRxRy16 (LiRxImmX16 0),
1634 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1641 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1642 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1645 // this pattern will never be used because the compiler will transform
1646 // x >= k to x > (k - 1) and then use SLT
1649 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1650 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1651 // (LiRxImmX16 1))>;
1657 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1658 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1664 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1665 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1670 def: SetCC_R16<setult, SltuCCRxRy16>;
1672 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1674 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1675 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1679 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1680 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1681 def : Mips16Pat<(MipsHi tjumptable:$in),
1682 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1683 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1684 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1687 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1688 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1689 (ADDiuOp RC:$gp, node:$in)>;
1692 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1693 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1695 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1696 (LbuRxRyOffMemX16 addr16:$src)>;
1697 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1698 (LhuRxRyOffMemX16 addr16:$src)>;