1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
14 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
15 isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in
16 def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target),
17 "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
19 // As stack alignment is always done with addiu, we need a 16-bit immediate
20 let Defs = [SP], Uses = [SP] in {
21 def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
22 "!ADJCALLSTACKDOWN $amt",
23 [(callseq_start timm:$amt)]>;
24 def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
25 "!ADJCALLSTACKUP $amt1",
26 [(callseq_end timm:$amt1, timm:$amt2)]>;
30 // Jump and Link (Call)
31 let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
33 FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
34 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;