1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // I-type instruction format
37 // this is only used by bimm. the actual assembly value is a 12 bit signed
40 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
41 FI16<op, (outs), (ins brtarget:$imm16),
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
46 // I8 instruction format
49 class FI816_ins_base<bits<3> _func, string asmstr,
50 string asmstr2, InstrItinClass itin>:
51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
54 class FI816_ins<bits<3> _func, string asmstr,
56 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
58 class FI816_SP_ins<bits<3> _func, string asmstr,
60 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
63 // RI instruction format
67 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
69 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
70 !strconcat(asmstr, asmstr2), [], itin>;
72 class FRI16_ins<bits<5> op, string asmstr,
74 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
76 class FRI16_TCP_ins<bits<5> _op, string asmstr,
78 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
79 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
81 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
83 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
84 !strconcat(asmstr, asmstr2), [], itin>;
86 class FRI16R_ins<bits<5> op, string asmstr,
88 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
90 class F2RI16_ins<bits<5> _op, string asmstr,
92 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
93 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
94 let Constraints = "$rx_ = $rx";
97 class FRI16_B_ins<bits<5> _op, string asmstr,
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
100 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
102 // Compare a register and immediate and place result in CC
103 // Implicit use of T8
105 // EXT-CCRR Instruction format
107 class FEXT_CCRXI16_ins<string asmstr>:
108 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
109 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
111 let usesCustomInserter = 1;
114 // JAL and JALX instruction format
116 class FJAL16_ins<bits<1> _X, string asmstr,
117 InstrItinClass itin>:
118 FJAL16<_X, (outs), (ins simm20:$imm),
119 !strconcat(asmstr, "\t$imm\n\tnop"),[],
124 // EXT-I instruction format
126 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
127 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
128 !strconcat(asmstr, "\t$imm16"),[], itin>;
131 // EXT-I8 instruction format
134 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
135 string asmstr2, InstrItinClass itin>:
136 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
139 class FEXT_I816_ins<bits<3> _func, string asmstr,
140 InstrItinClass itin>:
141 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
143 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
144 InstrItinClass itin>:
145 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
148 // Assembler formats in alphabetical order.
149 // Natural and pseudos are mixed together.
151 // Compare two registers and place result in CC
152 // Implicit use of T8
154 // CC-RR Instruction format
156 class FCCRR16_ins<string asmstr> :
157 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
158 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
160 let usesCustomInserter = 1;
164 // EXT-RI instruction format
167 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
168 InstrItinClass itin>:
169 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
170 !strconcat(asmstr, asmstr2), [], itin>;
172 class FEXT_RI16_ins<bits<5> _op, string asmstr,
173 InstrItinClass itin>:
174 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
176 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
177 InstrItinClass itin>:
178 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
179 !strconcat(asmstr, asmstr2), [], itin>;
181 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
182 InstrItinClass itin>:
183 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
185 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
186 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
188 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
189 InstrItinClass itin>:
190 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
191 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
193 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
194 InstrItinClass itin>:
195 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
196 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
198 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
199 InstrItinClass itin>:
200 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
201 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
202 let Constraints = "$rx_ = $rx";
206 // this has an explicit sp argument that we ignore to work around a problem
208 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
209 InstrItinClass itin>:
210 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
211 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
213 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
214 InstrItinClass itin>:
215 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
216 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
219 // EXT-RRI instruction format
222 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
223 InstrItinClass itin>:
224 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
225 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
227 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
228 InstrItinClass itin>:
229 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
230 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
234 // EXT-RRI-A instruction format
237 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
238 InstrItinClass itin>:
239 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
240 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
243 // EXT-SHIFT instruction format
245 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
246 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
247 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
252 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
254 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
255 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
256 !strconcat(asmstr, "\t$imm"))),[]> {
258 let usesCustomInserter = 1;
264 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
266 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
267 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
268 !strconcat(asmstr, "\t$targ"))), []> {
270 let usesCustomInserter = 1;
276 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
278 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
279 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
280 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
283 // I8_MOV32R instruction format (used only by MOV32R instruction)
286 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
287 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
288 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
291 // This are pseudo formats for multiply
292 // This first one can be changed to non pseudo now.
296 class FMULT16_ins<string asmstr, InstrItinClass itin> :
297 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
298 !strconcat(asmstr, "\t$rx, $ry"), []>;
303 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
304 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
305 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
310 // RR-type instruction format
313 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
314 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
315 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
318 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
319 FRRBreak16<(outs), (ins), asmstr, [], itin> {
323 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
324 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
325 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
328 class FRRTR16_ins<string asmstr> :
329 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
330 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
333 // maybe refactor but need a $zero as a dummy first parameter
335 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
336 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
337 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
339 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
340 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
341 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
344 class FRR16_M_ins<bits<5> f, string asmstr,
345 InstrItinClass itin> :
346 FRR16<f, (outs CPU16Regs:$rx), (ins),
347 !strconcat(asmstr, "\t$rx"), [], itin>;
349 class FRxRxRy16_ins<bits<5> f, string asmstr,
350 InstrItinClass itin> :
351 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rz, $ry"),
354 let Constraints = "$rx = $rz";
358 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
359 string asmstr, InstrItinClass itin>:
360 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
364 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
365 string asmstr, InstrItinClass itin>:
366 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
367 !strconcat(asmstr, "\t $rx"), [], itin> ;
370 <bits<5> _funct, bits<3> _subfunc,
371 string asmstr, InstrItinClass itin>:
372 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
373 !strconcat(asmstr, "\t $rx"),
375 let Constraints = "$rx_ = $rx";
378 // RRR-type instruction format
381 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
382 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
383 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
386 // These Sel patterns support the generation of conditional move
387 // pseudo instructions.
389 // The nomenclature uses the components making up the pseudo and may
390 // be a bit counter intuitive when compared with the end result we seek.
391 // For example using a bqez in the example directly below results in the
392 // conditional move being done if the tested register is not zero.
393 // I considered in easier to check by keeping the pseudo consistent with
394 // it's components but it could have been done differently.
396 // The simplest case is when can test and operand directly and do the
397 // conditional move based on a simple mips16 conditional
398 // branch instruction.
400 // if $op == beqz or bnez:
405 // if $op == beqz, then if $rt != 0, then the conditional assignment
406 // $rd = $rs is done.
408 // if $op == bnez, then if $rt == 0, then the conditional assignment
409 // $rd = $rs is done.
411 // So this pseudo class only has one operand, i.e. op
413 class Sel<string op>:
414 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
416 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
417 //let isCodeGenOnly=1;
418 let Constraints = "$rd = $rd_";
419 let usesCustomInserter = 1;
423 // The next two instruction classes allow for an operand which tests
424 // two operands and returns a value in register T8 and
425 //then does a conditional branch based on the value of T8
428 // op2 can be cmpi or slti/sltiu
429 // op1 can bteqz or btnez
430 // the operands for op2 are a register and a signed constant
432 // $op2 $t, $imm ;test register t and branch conditionally
433 // $op1 .+4 ;op1 is a conditional branch
437 class SeliT<string op1, string op2>:
438 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
439 CPU16Regs:$rl, simm16:$imm),
441 !strconcat("\t$rl, $imm\n\t",
442 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
444 let Constraints = "$rd = $rd_";
445 let usesCustomInserter = 1;
449 // op2 can be cmp or slt/sltu
450 // op1 can be bteqz or btnez
451 // the operands for op2 are two registers
452 // op1 is a conditional branch
455 // $op2 $rl, $rr ;test registers rl,rr
456 // $op1 .+4 ;op2 is a conditional branch
460 class SelT<string op1, string op2>:
461 MipsPseudo16<(outs CPU16Regs:$rd_),
462 (ins CPU16Regs:$rd, CPU16Regs:$rs,
463 CPU16Regs:$rl, CPU16Regs:$rr),
465 !strconcat("\t$rl, $rr\n\t",
466 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
468 let Constraints = "$rd = $rd_";
469 let usesCustomInserter = 1;
475 def imm32: Operand<i32>;
478 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
481 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
482 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
486 // Some general instruction class info
490 class ArithLogic16Defs<bit isCom=0> {
492 bit isCommutable = isCom;
493 bit isReMaterializable = 1;
494 bit neverHasSideEffects = 1;
499 bit isTerminator = 1;
505 bit isTerminator = 1;
518 // Format: ADDIU rx, immediate MIPS16e
519 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
520 // To add a constant to a 32-bit integer.
522 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
524 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
525 ArithLogic16Defs<0> {
526 let AddedComplexity = 5;
528 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
529 ArithLogic16Defs<0> {
530 let isCodeGenOnly = 1;
533 def AddiuRxRyOffMemX16:
534 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
538 // Format: ADDIU rx, pc, immediate MIPS16e
539 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
540 // To add a constant to the program counter.
542 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
545 // Format: ADDIU sp, immediate MIPS16e
546 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
547 // To add a constant to the stack pointer.
550 : FI816_SP_ins<0b011, "addiu", IIAlu> {
553 let AddedComplexity = 5;
557 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
563 // Format: ADDU rz, rx, ry MIPS16e
564 // Purpose: Add Unsigned Word (3-Operand)
565 // To add 32-bit integers.
568 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
571 // Format: AND rx, ry MIPS16e
573 // To do a bitwise logical AND.
575 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
579 // Format: BEQZ rx, offset MIPS16e
580 // Purpose: Branch on Equal to Zero
581 // To test a GPR then do a PC-relative conditional branch.
583 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
587 // Format: BEQZ rx, offset MIPS16e
588 // Purpose: Branch on Equal to Zero (Extended)
589 // To test a GPR then do a PC-relative conditional branch.
591 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
594 // Format: B offset MIPS16e
595 // Purpose: Unconditional Branch (Extended)
596 // To do an unconditional PC-relative branch.
599 def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16;
601 // Format: B offset MIPS16e
602 // Purpose: Unconditional Branch
603 // To do an unconditional PC-relative branch.
605 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
608 // Format: BNEZ rx, offset MIPS16e
609 // Purpose: Branch on Not Equal to Zero
610 // To test a GPR then do a PC-relative conditional branch.
612 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
615 // Format: BNEZ rx, offset MIPS16e
616 // Purpose: Branch on Not Equal to Zero (Extended)
617 // To test a GPR then do a PC-relative conditional branch.
619 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
623 //Format: BREAK immediate
624 // Purpose: Breakpoint
625 // To cause a Breakpoint exception.
627 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
629 // Format: BTEQZ offset MIPS16e
630 // Purpose: Branch on T Equal to Zero (Extended)
631 // To test special register T then do a PC-relative conditional branch.
633 def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
637 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
641 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
643 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
646 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
648 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
650 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
652 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
656 // Format: BTNEZ offset MIPS16e
657 // Purpose: Branch on T Not Equal to Zero (Extended)
658 // To test special register T then do a PC-relative conditional branch.
661 def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 {
665 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
669 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
671 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
673 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
675 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
677 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
679 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
683 // Format: CMP rx, ry MIPS16e
685 // To compare the contents of two GPRs.
687 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
692 // Format: CMPI rx, immediate MIPS16e
693 // Purpose: Compare Immediate
694 // To compare a constant with the contents of a GPR.
696 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
701 // Format: CMPI rx, immediate MIPS16e
702 // Purpose: Compare Immediate (Extended)
703 // To compare a constant with the contents of a GPR.
705 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
711 // Format: DIV rx, ry MIPS16e
712 // Purpose: Divide Word
713 // To divide 32-bit signed integers.
715 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
716 let Defs = [HI0, LO0];
720 // Format: DIVU rx, ry MIPS16e
721 // Purpose: Divide Unsigned Word
722 // To divide 32-bit unsigned integers.
724 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
725 let Defs = [HI0, LO0];
728 // Format: JAL target MIPS16e
729 // Purpose: Jump and Link
730 // To execute a procedure call within the current 256 MB-aligned
731 // region and preserve the current ISA.
734 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
735 let hasDelaySlot = 0; // not true, but we add the nop for now
740 // Format: JR ra MIPS16e
741 // Purpose: Jump Register Through Register ra
742 // To execute a branch to the instruction address in the return
746 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
748 let isIndirectBranch = 1;
749 let hasDelaySlot = 1;
754 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
756 let isIndirectBranch = 1;
761 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
763 let isIndirectBranch = 1;
768 // Format: LB ry, offset(rx) MIPS16e
769 // Purpose: Load Byte (Extended)
770 // To load a byte from memory as a signed value.
772 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
773 let isCodeGenOnly = 1;
777 // Format: LBU ry, offset(rx) MIPS16e
778 // Purpose: Load Byte Unsigned (Extended)
779 // To load a byte from memory as a unsigned value.
781 def LbuRxRyOffMemX16:
782 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
783 let isCodeGenOnly = 1;
787 // Format: LH ry, offset(rx) MIPS16e
788 // Purpose: Load Halfword signed (Extended)
789 // To load a halfword from memory as a signed value.
791 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
792 let isCodeGenOnly = 1;
796 // Format: LHU ry, offset(rx) MIPS16e
797 // Purpose: Load Halfword unsigned (Extended)
798 // To load a halfword from memory as an unsigned value.
800 def LhuRxRyOffMemX16:
801 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
802 let isCodeGenOnly = 1;
806 // Format: LI rx, immediate MIPS16e
807 // Purpose: Load Immediate
808 // To load a constant into a GPR.
810 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
813 // Format: LI rx, immediate MIPS16e
814 // Purpose: Load Immediate (Extended)
815 // To load a constant into a GPR.
817 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
819 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
820 let isCodeGenOnly = 1;
824 // Format: LW ry, offset(rx) MIPS16e
825 // Purpose: Load Word (Extended)
826 // To load a word from memory as a signed value.
828 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
829 let isCodeGenOnly = 1;
832 // Format: LW rx, offset(sp) MIPS16e
833 // Purpose: Load Word (SP-Relative, Extended)
834 // To load an SP-relative word from memory as a signed value.
836 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{
840 def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
842 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
844 // Format: MOVE r32, rz MIPS16e
846 // To move the contents of a GPR to a GPR.
848 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
851 // Format: MOVE ry, r32 MIPS16e
853 // To move the contents of a GPR to a GPR.
855 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
858 // Format: MFHI rx MIPS16e
859 // Purpose: Move From HI Register
860 // To copy the special purpose HI register to a GPR.
862 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
864 let neverHasSideEffects = 1;
868 // Format: MFLO rx MIPS16e
869 // Purpose: Move From LO Register
870 // To copy the special purpose LO register to a GPR.
872 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
874 let neverHasSideEffects = 1;
878 // Pseudo Instruction for mult
880 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
881 let isCommutable = 1;
882 let neverHasSideEffects = 1;
883 let Defs = [HI0, LO0];
886 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
887 let isCommutable = 1;
888 let neverHasSideEffects = 1;
889 let Defs = [HI0, LO0];
893 // Format: MULT rx, ry MIPS16e
894 // Purpose: Multiply Word
895 // To multiply 32-bit signed integers.
897 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
898 let isCommutable = 1;
899 let neverHasSideEffects = 1;
900 let Defs = [HI0, LO0];
904 // Format: MULTU rx, ry MIPS16e
905 // Purpose: Multiply Unsigned Word
906 // To multiply 32-bit unsigned integers.
908 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
909 let isCommutable = 1;
910 let neverHasSideEffects = 1;
911 let Defs = [HI0, LO0];
915 // Format: NEG rx, ry MIPS16e
917 // To negate an integer value.
919 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
922 // Format: NOT rx, ry MIPS16e
924 // To complement an integer value
926 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
929 // Format: OR rx, ry MIPS16e
931 // To do a bitwise logical OR.
933 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
936 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
937 // (All args are optional) MIPS16e
938 // Purpose: Restore Registers and Deallocate Stack Frame
939 // To deallocate a stack frame before exit from a subroutine,
940 // restoring return address and static registers, and adjusting
944 // fixed form for restoring RA and the frame
945 // for direct object emitter, encoding needs to be adjusted for the
948 let ra=1, s=0,s0=1,s1=1 in
950 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
951 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
952 let isCodeGenOnly = 1;
953 let Defs = [S0, S1, S2, RA, SP];
957 // Use Restore to increment SP since SP is not a Mip 16 register, this
958 // is an easy way to do that which does not require a register.
960 let ra=0, s=0,s0=0,s1=0 in
962 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
963 "restore\t$frame_size", [], IILoad >, MayLoad {
964 let isCodeGenOnly = 1;
970 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
972 // Purpose: Save Registers and Set Up Stack Frame
973 // To set up a stack frame on entry to a subroutine,
974 // saving return address and static registers, and adjusting stack
976 let ra=1, s=1,s0=1,s1=1 in
978 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
979 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
980 let isCodeGenOnly = 1;
981 let Uses = [RA, SP, S0, S1, S2];
986 // Use Save to decrement the SP by a constant since SP is not
987 // a Mips16 register.
989 let ra=0, s=0,s0=0,s1=0 in
991 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
992 "save\t$frame_size", [], IIStore >, MayStore {
993 let isCodeGenOnly = 1;
998 // Format: SB ry, offset(rx) MIPS16e
999 // Purpose: Store Byte (Extended)
1000 // To store a byte to memory.
1002 def SbRxRyOffMemX16:
1003 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
1006 // Format: SEB rx MIPS16e
1007 // Purpose: Sign-Extend Byte
1008 // Sign-extend least significant byte in register rx.
1011 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
1014 // Format: SEH rx MIPS16e
1015 // Purpose: Sign-Extend Halfword
1016 // Sign-extend least significant word in register rx.
1019 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
1022 // The Sel(T) instructions are pseudos
1023 // T means that they use T8 implicitly.
1026 // Format: SelBeqZ rd, rs, rt
1027 // Purpose: if rt==0, do nothing
1030 def SelBeqZ: Sel<"beqz">;
1033 // Format: SelTBteqZCmp rd, rs, rl, rr
1034 // Purpose: b = Cmp rl, rr.
1035 // If b==0 then do nothing.
1036 // if b!=0 then rd = rs
1038 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1041 // Format: SelTBteqZCmpi rd, rs, rl, rr
1042 // Purpose: b = Cmpi rl, imm.
1043 // If b==0 then do nothing.
1044 // if b!=0 then rd = rs
1046 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1049 // Format: SelTBteqZSlt rd, rs, rl, rr
1050 // Purpose: b = Slt rl, rr.
1051 // If b==0 then do nothing.
1052 // if b!=0 then rd = rs
1054 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1057 // Format: SelTBteqZSlti rd, rs, rl, rr
1058 // Purpose: b = Slti rl, imm.
1059 // If b==0 then do nothing.
1060 // if b!=0 then rd = rs
1062 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1065 // Format: SelTBteqZSltu rd, rs, rl, rr
1066 // Purpose: b = Sltu rl, rr.
1067 // If b==0 then do nothing.
1068 // if b!=0 then rd = rs
1070 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1073 // Format: SelTBteqZSltiu rd, rs, rl, rr
1074 // Purpose: b = Sltiu rl, imm.
1075 // If b==0 then do nothing.
1076 // if b!=0 then rd = rs
1078 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1081 // Format: SelBnez rd, rs, rt
1082 // Purpose: if rt!=0, do nothing
1085 def SelBneZ: Sel<"bnez">;
1088 // Format: SelTBtneZCmp rd, rs, rl, rr
1089 // Purpose: b = Cmp rl, rr.
1090 // If b!=0 then do nothing.
1091 // if b0=0 then rd = rs
1093 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1096 // Format: SelTBtnezCmpi rd, rs, rl, rr
1097 // Purpose: b = Cmpi rl, imm.
1098 // If b!=0 then do nothing.
1099 // if b==0 then rd = rs
1101 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1104 // Format: SelTBtneZSlt rd, rs, rl, rr
1105 // Purpose: b = Slt rl, rr.
1106 // If b!=0 then do nothing.
1107 // if b==0 then rd = rs
1109 def SelTBtneZSlt: SelT<"btnez", "slt">;
1112 // Format: SelTBtneZSlti rd, rs, rl, rr
1113 // Purpose: b = Slti rl, imm.
1114 // If b!=0 then do nothing.
1115 // if b==0 then rd = rs
1117 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1120 // Format: SelTBtneZSltu rd, rs, rl, rr
1121 // Purpose: b = Sltu rl, rr.
1122 // If b!=0 then do nothing.
1123 // if b==0 then rd = rs
1125 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1128 // Format: SelTBtneZSltiu rd, rs, rl, rr
1129 // Purpose: b = Slti rl, imm.
1130 // If b!=0 then do nothing.
1131 // if b==0 then rd = rs
1133 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1136 // Format: SH ry, offset(rx) MIPS16e
1137 // Purpose: Store Halfword (Extended)
1138 // To store a halfword to memory.
1140 def ShRxRyOffMemX16:
1141 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1144 // Format: SLL rx, ry, sa MIPS16e
1145 // Purpose: Shift Word Left Logical (Extended)
1146 // To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
1148 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1151 // Format: SLLV ry, rx MIPS16e
1152 // Purpose: Shift Word Left Logical Variable
1153 // To execute a left-shift of a word by a variable number of bits.
1155 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1157 // Format: SLTI rx, immediate MIPS16e
1158 // Purpose: Set on Less Than Immediate
1159 // To record the result of a less-than comparison with a constant.
1162 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1167 // Format: SLTI rx, immediate MIPS16e
1168 // Purpose: Set on Less Than Immediate (Extended)
1169 // To record the result of a less-than comparison with a constant.
1172 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1176 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1178 // Format: SLTIU rx, immediate MIPS16e
1179 // Purpose: Set on Less Than Immediate Unsigned
1180 // To record the result of a less-than comparison with a constant.
1183 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1188 // Format: SLTI rx, immediate MIPS16e
1189 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1190 // To record the result of a less-than comparison with a constant.
1193 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1197 // Format: SLTIU rx, immediate MIPS16e
1198 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1199 // To record the result of a less-than comparison with a constant.
1201 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1204 // Format: SLT rx, ry MIPS16e
1205 // Purpose: Set on Less Than
1206 // To record the result of a less-than comparison.
1208 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1212 def SltCCRxRy16: FCCRR16_ins<"slt">;
1214 // Format: SLTU rx, ry MIPS16e
1215 // Purpose: Set on Less Than Unsigned
1216 // To record the result of an unsigned less-than comparison.
1218 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1222 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1223 let isCodeGenOnly=1;
1228 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1230 // Format: SRAV ry, rx MIPS16e
1231 // Purpose: Shift Word Right Arithmetic Variable
1232 // To execute an arithmetic right-shift of a word by a variable
1235 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1239 // Format: SRA rx, ry, sa MIPS16e
1240 // Purpose: Shift Word Right Arithmetic (Extended)
1241 // To execute an arithmetic right-shift of a word by a fixed
1242 // number of bits-1 to 8 bits.
1244 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1248 // Format: SRLV ry, rx MIPS16e
1249 // Purpose: Shift Word Right Logical Variable
1250 // To execute a logical right-shift of a word by a variable
1253 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1257 // Format: SRL rx, ry, sa MIPS16e
1258 // Purpose: Shift Word Right Logical (Extended)
1259 // To execute a logical right-shift of a word by a fixed
1260 // number of bits-1 to 31 bits.
1262 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1265 // Format: SUBU rz, rx, ry MIPS16e
1266 // Purpose: Subtract Unsigned Word
1267 // To subtract 32-bit integers
1269 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1272 // Format: SW ry, offset(rx) MIPS16e
1273 // Purpose: Store Word (Extended)
1274 // To store a word to memory.
1276 def SwRxRyOffMemX16:
1277 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1280 // Format: SW rx, offset(sp) MIPS16e
1281 // Purpose: Store Word rx (SP-Relative)
1282 // To store an SP-relative word to memory.
1284 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1285 <0b11010, "sw", IIStore>, MayStore;
1289 // Format: XOR rx, ry MIPS16e
1291 // To do a bitwise logical XOR.
1293 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1295 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1296 let Predicates = [InMips16Mode];
1299 // Unary Arith/Logic
1301 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1302 Mips16Pat<(OpNode CPU16Regs:$r),
1305 def: ArithLogicU_pat<not, NotRxRy16>;
1306 def: ArithLogicU_pat<ineg, NegRxRy16>;
1308 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1309 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1310 (I CPU16Regs:$l, CPU16Regs:$r)>;
1312 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1313 def: ArithLogic16_pat<and, AndRxRxRy16>;
1314 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1315 def: ArithLogic16_pat<or, OrRxRxRy16>;
1316 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1317 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1319 // Arithmetic and logical instructions with 2 register operands.
1321 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1322 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1323 (I CPU16Regs:$in, imm_type:$imm)>;
1325 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1326 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1327 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1328 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1329 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1331 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1332 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1333 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1335 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1336 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1337 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1339 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1340 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1342 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1343 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1344 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1345 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1346 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1348 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1349 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1350 (I CPU16Regs:$r, addr16:$addr)>;
1352 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1353 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1354 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1356 // Unconditional branch
1357 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1358 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1359 let Predicates = [InMips16Mode];
1362 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1363 (Jal16 tglobaladdr:$dst)>;
1365 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1366 (Jal16 texternalsym:$dst)>;
1370 (brind CPU16Regs:$rs),
1371 (JrcRx16 CPU16Regs:$rs)>;
1373 // Jump and Link (Call)
1374 let isCall=1, hasDelaySlot=0 in
1376 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1377 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1380 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1381 hasExtraSrcRegAllocReq = 1 in
1382 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1387 class SetCC_R16<PatFrag cond_op, Instruction I>:
1388 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1389 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1391 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1392 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1393 (I CPU16Regs:$rx, imm_type:$imm16)>;
1396 def: Mips16Pat<(i32 addr16:$addr),
1397 (AddiuRxRyOffMemX16 addr16:$addr)>;
1400 // Large (>16 bit) immediate loads
1401 def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1403 // Carry MipsPatterns
1404 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1405 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1406 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1407 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1408 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1409 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1412 // Some branch conditional patterns are not generated by llvm at this time.
1413 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1414 // comparison they are used and for unsigned a different pattern is used.
1415 // I am pushing upstream from the full mips16 port and it seemed that I needed
1416 // these earlier and the mips32 port has these but now I cannot create test
1417 // cases that use these patterns. While I sort this all out I will leave these
1418 // extra patterns commented out and if I can be sure they are really not used,
1419 // I will delete the code. I don't want to check the code in uncommented without
1420 // a valid test case. In some cases, the compiler is generating patterns with
1421 // setcc instead and earlier I had implemented setcc first so may have masked
1422 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1423 // figure out how to enable the brcond patterns or else possibly new
1424 // combinations of of brcond and setcc.
1430 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1431 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1436 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1437 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1441 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1442 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1446 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1449 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1450 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1457 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1458 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1462 // never called because compiler transforms a >= k to a > (k-1)
1464 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1465 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1472 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1473 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1477 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1478 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1485 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1486 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1493 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1494 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1498 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1499 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1503 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1504 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1508 // This needs to be there but I forget which code will generate it
1511 <(brcond CPU16Regs:$rx, bb:$targ16),
1512 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1521 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1522 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1529 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1530 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1538 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1539 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1542 def: UncondBranch16_pat<br, Bimm16>;
1545 def: Mips16Pat<(i32 immSExt16:$in),
1546 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1548 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1554 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1555 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1561 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1562 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1567 // if !(a < b) x = y
1569 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1570 CPU16Regs:$x, CPU16Regs:$y),
1571 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1572 CPU16Regs:$a, CPU16Regs:$b)>;
1579 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1580 CPU16Regs:$x, CPU16Regs:$y),
1581 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1582 CPU16Regs:$b, CPU16Regs:$a)>;
1587 // if !(a < b) x = y;
1590 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1591 CPU16Regs:$x, CPU16Regs:$y),
1592 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1593 CPU16Regs:$a, CPU16Regs:$b)>;
1600 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1601 CPU16Regs:$x, CPU16Regs:$y),
1602 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1603 CPU16Regs:$b, CPU16Regs:$a)>;
1607 // due to an llvm optimization, i don't think that this will ever
1608 // be used. This is transformed into x = (a > k-1)?x:y
1613 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1614 // CPU16Regs:$T, CPU16Regs:$F),
1615 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1616 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1619 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1620 // CPU16Regs:$T, CPU16Regs:$F),
1621 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1622 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1627 // if !(a < k) x = y;
1630 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1631 CPU16Regs:$x, CPU16Regs:$y),
1632 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1633 CPU16Regs:$a, immSExt16:$b)>;
1639 // x = (a <= b)? x : y
1643 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1644 CPU16Regs:$x, CPU16Regs:$y),
1645 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1646 CPU16Regs:$b, CPU16Regs:$a)>;
1650 // x = (a <= b)? x : y
1654 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1655 CPU16Regs:$x, CPU16Regs:$y),
1656 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1657 CPU16Regs:$b, CPU16Regs:$a)>;
1661 // x = (a == b)? x : y
1663 // if (a != b) x = y
1665 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1666 CPU16Regs:$x, CPU16Regs:$y),
1667 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1668 CPU16Regs:$b, CPU16Regs:$a)>;
1672 // x = (a == 0)? x : y
1674 // if (a != 0) x = y
1676 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1677 CPU16Regs:$x, CPU16Regs:$y),
1678 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1684 // x = (a == k)? x : y
1686 // if (a != k) x = y
1688 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1689 CPU16Regs:$x, CPU16Regs:$y),
1690 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1691 CPU16Regs:$a, immZExt16:$k)>;
1696 // x = (a != b)? x : y
1698 // if (a == b) x = y
1701 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1702 CPU16Regs:$x, CPU16Regs:$y),
1703 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1704 CPU16Regs:$b, CPU16Regs:$a)>;
1708 // x = (a != 0)? x : y
1710 // if (a == 0) x = y
1712 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1713 CPU16Regs:$x, CPU16Regs:$y),
1714 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1722 def : Mips16Pat<(select CPU16Regs:$a,
1723 CPU16Regs:$x, CPU16Regs:$y),
1724 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1730 // x = (a != k)? x : y
1732 // if (a == k) x = y
1734 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1735 CPU16Regs:$x, CPU16Regs:$y),
1736 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1737 CPU16Regs:$a, immZExt16:$k)>;
1740 // When writing C code to test setxx these patterns,
1741 // some will be transformed into
1742 // other things. So we test using C code but using -O3 and -O0
1747 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1748 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1751 <(seteq CPU16Regs:$lhs, 0),
1752 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1760 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1761 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1765 // For constants, llvm transforms this to:
1766 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1767 // is not used now by the compiler. (Presumably checking that k-1 does not
1768 // overflow). The compiler never uses this at a the current time, due to
1769 // other optimizations.
1772 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1773 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1774 // (LiRxImmX16 1))>;
1776 // This catches the x >= -32768 case by transforming it to x > -32769
1779 <(setgt CPU16Regs:$lhs, -32769),
1780 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1789 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1790 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1796 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1797 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1802 def: SetCC_R16<setlt, SltCCRxRy16>;
1804 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1810 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1811 (SltuCCRxRy16 (LiRxImmX16 0),
1812 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1819 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1820 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1823 // this pattern will never be used because the compiler will transform
1824 // x >= k to x > (k - 1) and then use SLT
1827 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1828 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1829 // (LiRxImmX16 1))>;
1835 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1836 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1842 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1843 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1848 def: SetCC_R16<setult, SltuCCRxRy16>;
1850 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1852 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1853 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1856 def : Mips16Pat<(MipsHi tblockaddress:$in),
1857 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1858 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1859 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1860 def : Mips16Pat<(MipsHi tjumptable:$in),
1861 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1862 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1863 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1865 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1868 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1869 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1870 (ADDiuOp RC:$gp, node:$in)>;
1873 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1874 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1876 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1877 (LbuRxRyOffMemX16 addr16:$src)>;
1878 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1879 (LhuRxRyOffMemX16 addr16:$src)>;
1881 def: Mips16Pat<(trap), (Break16)>;
1883 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1884 (SebRx16 CPU16Regs:$val)>;
1886 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1887 (SehRx16 CPU16Regs:$val)>;
1891 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1892 (ins simm16:$immHi, simm16:$immLo),
1893 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1895 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1896 def cpinst_operand : Operand<i32> {
1897 // let PrintMethod = "printCPInstOperand";
1900 // CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1901 // the function. The first operand is the ID# for this instruction, the second
1902 // is the index into the MachineConstantPool that this is, the third is the
1903 // size in bytes of this constant pool entry.
1905 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1906 def CONSTPOOL_ENTRY :
1907 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1908 i32imm:$size), "foo", []>;