2 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the Mips16 implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips16-instrinfo"
34 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
35 : MipsInstrInfo(tm, Mips::Bimm16),
36 RI(*tm.getSubtargetImpl()) {}
38 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const {
52 /// isStoreToStackSlot - If the specified machine instruction is a direct
53 /// store to a stack slot, return the virtual or physical register number of
54 /// the source reg along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than storing to the stack slot.
57 unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const {
62 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator I, DebugLoc DL,
64 unsigned DestReg, unsigned SrcReg,
68 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
69 Mips::GPR32RegClass.contains(SrcReg))
70 Opc = Mips::MoveR3216;
71 else if (Mips::GPR32RegClass.contains(DestReg) &&
72 Mips::CPU16RegsRegClass.contains(SrcReg))
73 Opc = Mips::Move32R16;
74 else if ((SrcReg == Mips::HI0) &&
75 (Mips::CPU16RegsRegClass.contains(DestReg)))
76 Opc = Mips::Mfhi16, SrcReg = 0;
78 else if ((SrcReg == Mips::LO0) &&
79 (Mips::CPU16RegsRegClass.contains(DestReg)))
80 Opc = Mips::Mflo16, SrcReg = 0;
83 assert(Opc && "Cannot copy registers");
85 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
88 MIB.addReg(DestReg, RegState::Define);
91 MIB.addReg(SrcReg, getKillRegState(KillSrc));
94 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator I,
96 unsigned SrcReg, bool isKill, int FI,
97 const TargetRegisterClass *RC,
98 const TargetRegisterInfo *TRI,
99 int64_t Offset) const {
101 if (I != MBB.end()) DL = I->getDebugLoc();
102 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
104 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
105 Opc = Mips::SwRxSpImmX16;
106 assert(Opc && "Register class not handled!");
107 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
108 addFrameIndex(FI).addImm(Offset)
112 void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator I,
114 unsigned DestReg, int FI,
115 const TargetRegisterClass *RC,
116 const TargetRegisterInfo *TRI,
117 int64_t Offset) const {
119 if (I != MBB.end()) DL = I->getDebugLoc();
120 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
123 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
124 Opc = Mips::LwRxSpImmX16;
125 assert(Opc && "Register class not handled!");
126 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
130 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
131 MachineBasicBlock &MBB = *MI->getParent();
132 switch(MI->getDesc().getOpcode()) {
136 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
144 /// GetOppositeBranchOpc - Return the inverse of the specified
145 /// opcode, e.g. turning BEQ to BNE.
146 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
148 default: llvm_unreachable("Illegal opcode!");
149 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
150 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
151 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
152 case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
153 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
154 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
155 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
156 case Mips::Btnez16: return Mips::Bteqz16;
157 case Mips::BtnezX16: return Mips::BteqzX16;
158 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
159 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
160 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
161 case Mips::Bteqz16: return Mips::Btnez16;
162 case Mips::BteqzX16: return Mips::BtnezX16;
163 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
164 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
165 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
166 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
167 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
168 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
170 assert(false && "Implement this function.");
174 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
175 const std::vector<CalleeSavedInfo> &CSI,
176 unsigned Flags = 0) {
177 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
178 // Add the callee-saved register as live-in. Do not add if the register is
179 // RA and return address is taken, because it has already been added in
180 // method MipsTargetLowering::LowerRETURNADDR.
181 // It's killed at the spill, unless the register is RA and return address
183 unsigned Reg = CSI[e-i-1].getReg();
188 MIB.addReg(Reg, Flags);
193 llvm_unreachable("unexpected mips16 callee saved register");
198 // Adjust SP by FrameSize bytes. Save RA, S0, S1
199 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
200 MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator I) const {
202 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
203 MachineFunction &MF = *MBB.getParent();
204 MachineFrameInfo *MFI = MF.getFrameInfo();
205 const BitVector Reserved = RI.getReservedRegs(MF);
206 bool SaveS2 = Reserved[Mips::S2];
207 MachineInstrBuilder MIB;
208 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
209 MIB = BuildMI(MBB, I, DL, get(Opc));
210 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
211 addSaveRestoreRegs(MIB, CSI);
213 MIB.addReg(Mips::S2);
214 if (isUInt<11>(FrameSize))
215 MIB.addImm(FrameSize);
217 int Base = 2040; // should create template function like isUInt that
218 // returns largest possible n bit unsigned integer
219 int64_t Remainder = FrameSize - Base;
221 if (isInt<16>(-Remainder))
222 BuildAddiuSpImm(MBB, I, -Remainder);
224 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
228 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
229 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
230 MachineBasicBlock &MBB,
231 MachineBasicBlock::iterator I) const {
232 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
233 MachineFunction *MF = MBB.getParent();
234 MachineFrameInfo *MFI = MF->getFrameInfo();
235 const BitVector Reserved = RI.getReservedRegs(*MF);
236 bool SaveS2 = Reserved[Mips::S2];
237 MachineInstrBuilder MIB;
238 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
239 Mips::Restore16:Mips::RestoreX16;
241 if (!isUInt<11>(FrameSize)) {
242 unsigned Base = 2040;
243 int64_t Remainder = FrameSize - Base;
244 FrameSize = Base; // should create template function like isUInt that
245 // returns largest possible n bit unsigned integer
247 if (isInt<16>(Remainder))
248 BuildAddiuSpImm(MBB, I, Remainder);
250 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
252 MIB = BuildMI(MBB, I, DL, get(Opc));
253 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
254 addSaveRestoreRegs(MIB, CSI, RegState::Define);
256 MIB.addReg(Mips::S2, RegState::Define);
257 MIB.addImm(FrameSize);
260 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
261 // This can only be called at times that we know that there is at least one free
263 // This is clearly safe at prologue and epilogue.
265 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
266 MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator I,
268 unsigned Reg1, unsigned Reg2) const {
269 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
273 // add reg1, reg1, reg2
277 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278 MIB1.addImm(Amount).addImm(-1);
279 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280 MIB2.addReg(Mips::SP, RegState::Kill);
281 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283 MIB3.addReg(Reg2, RegState::Kill);
284 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
286 MIB4.addReg(Reg1, RegState::Kill);
289 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
290 unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator I) const {
292 assert(false && "adjust stack pointer amount exceeded");
295 /// Adjust SP by Amount bytes.
296 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
297 MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator I) const {
299 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
300 BuildAddiuSpImm(MBB, I, Amount);
302 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
305 /// This function generates the sequence of instructions needed to get the
306 /// result of adding register REG and immediate IMM.
307 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
308 MachineBasicBlock &MBB,
309 MachineBasicBlock::iterator II,
310 DebugLoc DL, unsigned &NewImm) const {
312 // given original instruction is:
313 // Instr rx, T[offset] where offset is too big.
315 // lo = offset & 0xFFFF
316 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
318 // let T = temporary register
324 int32_t lo = Imm & 0xFFFF;
329 rs.enterBasicBlock(&MBB);
332 // We need to know which registers can be used, in the case where there
333 // are not enough free registers. We exclude all registers that
334 // are used in the instruction that we are helping.
335 // // Consider all allocatable registers in the register class initially
336 BitVector Candidates =
338 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
339 // Exclude all the registers being used by the instruction.
340 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
341 MachineOperand &MO = II->getOperand(i);
342 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
343 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
344 Candidates.reset(MO.getReg());
347 // If the same register was used and defined in an instruction, then
348 // it will not be in the list of candidates.
350 // we need to analyze the instruction that we are helping.
351 // we need to know if it defines register x but register x is not
352 // present as an operand of the instruction. this tells
353 // whether the register is live before the instruction. if it's not
354 // then we don't need to save it in case there are no free registers.
356 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
357 MachineOperand &MO = II->getOperand(i);
358 if (MO.isReg() && MO.isDef()) {
359 DefReg = MO.getReg();
364 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
365 Available &= Candidates;
367 // we use T0 for the first register, if we need to save something away.
368 // we use T1 for the second register, if we need to save something away.
370 unsigned FirstRegSaved =0, SecondRegSaved=0;
371 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
373 Reg = Available.find_first();
376 Reg = Candidates.find_first();
377 Candidates.reset(Reg);
380 FirstRegSavedTo = Mips::T0;
381 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
385 Available.reset(Reg);
386 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
388 if (FrameReg == Mips::SP) {
389 SpReg = Available.find_first();
391 SpReg = Candidates.find_first();
392 // Candidates.reset(SpReg); // not really needed
393 if (DefReg!= SpReg) {
394 SecondRegSaved = SpReg;
395 SecondRegSavedTo = Mips::T1;
398 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
401 Available.reset(SpReg);
402 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
403 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
407 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
408 .addReg(Reg, RegState::Kill);
409 if (FirstRegSaved || SecondRegSaved) {
412 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
414 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
419 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
420 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
421 Opc == Mips::Bimm16 ||
422 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
423 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
424 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
425 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
426 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
427 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
428 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
429 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
430 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
431 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
434 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
435 MachineBasicBlock::iterator I,
436 unsigned Opc) const {
437 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
440 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
441 if (validSpImm8(Imm))
442 return get(Mips::AddiuSpImm16);
444 return get(Mips::AddiuSpImmX16);
447 void Mips16InstrInfo::BuildAddiuSpImm
448 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
449 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
450 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
453 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
454 return new Mips16InstrInfo(TM);
457 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
460 case Mips::LbRxRyOffMemX16:
461 case Mips::LbuRxRyOffMemX16:
462 case Mips::LhRxRyOffMemX16:
463 case Mips::LhuRxRyOffMemX16:
464 case Mips::SbRxRyOffMemX16:
465 case Mips::ShRxRyOffMemX16:
466 case Mips::LwRxRyOffMemX16:
467 case Mips::SwRxRyOffMemX16:
468 case Mips::SwRxSpImmX16:
469 case Mips::LwRxSpImmX16:
470 return isInt<16>(Amount);
471 case Mips::AddiuRxRyOffMemX16:
472 if ((Reg == Mips::PC) || (Reg == Mips::SP))
473 return isInt<16>(Amount);
474 return isInt<15>(Amount);
476 llvm_unreachable("unexpected Opcode in validImmediate");
479 /// Measure the specified inline asm to determine an approximation of its
481 /// Comments (which run till the next SeparatorString or newline) do not
482 /// count as an instruction.
483 /// Any other non-whitespace text is considered an instruction, with
484 /// multiple instructions separated by SeparatorString or newlines.
485 /// Variable-length instructions are not handled here; this function
486 /// may be overloaded in the target code to do that.
487 /// We implement the special case of the .space directive taking only an
488 /// integer argument, which is the size in bytes. This is used for creating
489 /// inline code spacing for testing purposes using inline assembly.
491 unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
492 const MCAsmInfo &MAI) const {
494 // Count the number of instructions in the asm.
495 bool atInsnStart = true;
497 for (; *Str; ++Str) {
498 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
499 strlen(MAI.getSeparatorString())) == 0)
501 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
502 if (strncmp(Str, ".space", 6)==0) {
504 Sz = strtol(Str+6, &EStr, 10);
505 while (isspace(*EStr)) ++EStr;
507 DEBUG(dbgs() << "parsed .space " << Sz << '\n');
511 Length += MAI.getMaxInstLength();
514 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
515 strlen(MAI.getCommentString())) == 0)