1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 static cl::opt<bool> NeverUseSaveRestore(
31 "mips16-never-use-save-restore",
33 cl::desc("For testing ability to adjust stack pointer "
34 "without save/restore instruction"),
38 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39 : MipsInstrInfo(tm, Mips::BimmX16),
40 RI(*tm.getSubtargetImpl(), *this) {}
42 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
46 /// isLoadFromStackSlot - If the specified machine instruction is a direct
47 /// load from a stack slot, return the virtual or physical register number of
48 /// the destination along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than loading from the stack slot.
51 unsigned Mips16InstrInfo::
52 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
62 unsigned Mips16InstrInfo::
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
74 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75 Mips::CPURegsRegClass.contains(SrcReg))
76 Opc = Mips::MoveR3216;
77 else if (Mips::CPURegsRegClass.contains(DestReg) &&
78 Mips::CPU16RegsRegClass.contains(SrcReg))
79 Opc = Mips::Move32R16;
80 else if ((SrcReg == Mips::HI) &&
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
82 Opc = Mips::Mfhi16, SrcReg = 0;
84 else if ((SrcReg == Mips::LO) &&
85 (Mips::CPU16RegsRegClass.contains(DestReg)))
86 Opc = Mips::Mflo16, SrcReg = 0;
89 assert(Opc && "Cannot copy registers");
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
100 void Mips16InstrInfo::
101 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102 unsigned SrcReg, bool isKill, int FI,
103 const TargetRegisterClass *RC,
104 const TargetRegisterInfo *TRI) const {
106 if (I != MBB.end()) DL = I->getDebugLoc();
107 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
109 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110 Opc = Mips::SwRxSpImmX16;
111 assert(Opc && "Register class not handled!");
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
116 void Mips16InstrInfo::
117 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118 unsigned DestReg, int FI,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const {
122 if (I != MBB.end()) DL = I->getDebugLoc();
123 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
126 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127 Opc = Mips::LwRxSpImmX16;
128 assert(Opc && "Register class not handled!");
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
133 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134 MachineBasicBlock &MBB = *MI->getParent();
136 switch(MI->getDesc().getOpcode()) {
139 case Mips::BtnezT8CmpX16:
140 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
143 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
151 /// GetOppositeBranchOpc - Return the inverse of the specified
152 /// opcode, e.g. turning BEQ to BNE.
153 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
155 default: llvm_unreachable("Illegal opcode!");
156 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
157 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
158 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
159 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
160 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
161 case Mips::BtnezX16: return Mips::BteqzX16;
162 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
163 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
164 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
165 case Mips::BteqzX16: return Mips::BtnezX16;
166 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
167 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
168 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
169 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
170 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
171 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
173 assert(false && "Implement this function.");
177 // Adjust SP by FrameSize bytes. Save RA, S0, S1
178 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
179 MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator I) const {
181 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
182 if (!NeverUseSaveRestore) {
183 if (isUInt<11>(FrameSize))
184 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
186 int Base = 2040; // should create template function like isUInt that
187 // returns largest possible n bit unsigned integer
188 int64_t Remainder = FrameSize - Base;
189 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
190 if (isInt<16>(-Remainder))
191 BuildAddiuSpImm(MBB, I, -Remainder);
193 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
203 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
205 MIB1.addReg(Mips::SP);
207 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
209 MIB2.addReg(Mips::SP);
211 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
213 MIB3.addReg(Mips::SP);
215 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
219 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
220 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
221 MachineBasicBlock &MBB,
222 MachineBasicBlock::iterator I) const {
223 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
224 if (!NeverUseSaveRestore) {
225 if (isUInt<11>(FrameSize))
226 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
228 int Base = 2040; // should create template function like isUInt that
229 // returns largest possible n bit unsigned integer
230 int64_t Remainder = FrameSize - Base;
231 if (isInt<16>(Remainder))
232 BuildAddiuSpImm(MBB, I, Remainder);
234 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
235 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
239 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
243 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
245 MIB1.addReg(Mips::SP);
247 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
249 MIB0.addReg(Mips::A0);
250 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
252 MIB2.addReg(Mips::SP);
254 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
256 MIB3.addReg(Mips::SP);
262 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
263 // This can only be called at times that we know that there is at least one free
265 // This is clearly safe at prologue and epilogue.
267 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
268 MachineBasicBlock &MBB,
269 MachineBasicBlock::iterator I,
270 unsigned Reg1, unsigned Reg2) const {
271 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
272 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
273 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
274 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
278 // add reg1, reg1, reg2
282 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
284 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
285 MIB2.addReg(Mips::SP, RegState::Kill);
286 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
288 MIB3.addReg(Reg2, RegState::Kill);
289 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
291 MIB4.addReg(Reg1, RegState::Kill);
294 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
295 MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator I) const {
297 assert(false && "adjust stack pointer amount exceeded");
300 /// Adjust SP by Amount bytes.
301 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
302 MachineBasicBlock &MBB,
303 MachineBasicBlock::iterator I) const {
304 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
305 BuildAddiuSpImm(MBB, I, Amount);
307 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
310 /// This function generates the sequence of instructions needed to get the
311 /// result of adding register REG and immediate IMM.
313 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
314 int64_t Imm, MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator II, DebugLoc DL,
316 unsigned &NewImm) const {
318 // given original instruction is:
319 // Instr rx, T[offset] where offset is too big.
321 // lo = offset & 0xFFFF
322 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
324 // let T = temporary register
330 int32_t lo = Imm & 0xFFFF;
331 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
335 rs.enterBasicBlock(&MBB);
338 // we use T0 for the first register, if we need to save something away.
339 // we use T1 for the second register, if we need to save something away.
341 unsigned FirstRegSaved =0, SecondRegSaved=0;
342 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
344 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
346 FirstRegSaved = Reg = Mips::V0;
347 FirstRegSavedTo = Mips::T0;
348 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
352 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
353 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
355 if (FrameReg == Mips::SP) {
356 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
358 if (Reg != Mips::V1) {
359 SecondRegSaved = SpReg = Mips::V1;
360 SecondRegSavedTo = Mips::T1;
363 SecondRegSaved = SpReg = Mips::V0;
364 SecondRegSavedTo = Mips::T0;
366 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
371 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
372 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
376 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
377 .addReg(Reg, RegState::Kill);
378 if (FirstRegSaved || SecondRegSaved) {
381 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
383 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
388 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
389 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
390 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
391 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
392 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
393 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
394 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
395 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
396 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
397 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
400 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
401 MachineBasicBlock::iterator I,
402 unsigned Opc) const {
403 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
407 void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
408 MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
409 unsigned BtOpc, unsigned CmpOpc) const {
410 unsigned regX = I->getOperand(0).getReg();
411 unsigned regY = I->getOperand(1).getReg();
412 MachineBasicBlock *target = I->getOperand(2).getMBB();
413 BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
414 BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
417 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
418 if (validSpImm8(Imm))
419 return get(Mips::AddiuSpImm16);
421 return get(Mips::AddiuSpImmX16);
424 void Mips16InstrInfo::BuildAddiuSpImm
425 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
426 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
427 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
430 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
431 return new Mips16InstrInfo(TM);