1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 static cl::opt<bool> NeverUseSaveRestore(
31 "mips16-never-use-save-restore",
33 cl::desc("For testing ability to adjust stack pointer "
34 "without save/restore instruction"),
38 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39 : MipsInstrInfo(tm, Mips::BimmX16),
40 RI(*tm.getSubtargetImpl(), *this) {}
42 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
46 /// isLoadFromStackSlot - If the specified machine instruction is a direct
47 /// load from a stack slot, return the virtual or physical register number of
48 /// the destination along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than loading from the stack slot.
51 unsigned Mips16InstrInfo::
52 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
62 unsigned Mips16InstrInfo::
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
74 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75 Mips::CPURegsRegClass.contains(SrcReg))
76 Opc = Mips::MoveR3216;
77 else if (Mips::CPURegsRegClass.contains(DestReg) &&
78 Mips::CPU16RegsRegClass.contains(SrcReg))
79 Opc = Mips::Move32R16;
80 else if ((SrcReg == Mips::HI) &&
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
82 Opc = Mips::Mfhi16, SrcReg = 0;
84 else if ((SrcReg == Mips::LO) &&
85 (Mips::CPU16RegsRegClass.contains(DestReg)))
86 Opc = Mips::Mflo16, SrcReg = 0;
89 assert(Opc && "Cannot copy registers");
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
100 void Mips16InstrInfo::
101 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102 unsigned SrcReg, bool isKill, int FI,
103 const TargetRegisterClass *RC,
104 const TargetRegisterInfo *TRI) const {
106 if (I != MBB.end()) DL = I->getDebugLoc();
107 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
109 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110 Opc = Mips::SwRxSpImmX16;
111 assert(Opc && "Register class not handled!");
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
116 void Mips16InstrInfo::
117 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118 unsigned DestReg, int FI,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const {
122 if (I != MBB.end()) DL = I->getDebugLoc();
123 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
126 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127 Opc = Mips::LwRxSpImmX16;
128 assert(Opc && "Register class not handled!");
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
133 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134 MachineBasicBlock &MBB = *MI->getParent();
136 switch(MI->getDesc().getOpcode()) {
139 case Mips::BteqzT8CmpX16:
140 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
142 case Mips::BtnezT8CmpX16:
143 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
146 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
154 /// GetOppositeBranchOpc - Return the inverse of the specified
155 /// opcode, e.g. turning BEQ to BNE.
156 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
158 default: llvm_unreachable("Illegal opcode!");
159 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
160 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
161 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
162 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
163 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
164 case Mips::BtnezX16: return Mips::BteqzX16;
165 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
166 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
167 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
168 case Mips::BteqzX16: return Mips::BtnezX16;
169 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
170 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
171 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
172 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
173 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
174 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
176 assert(false && "Implement this function.");
180 // Adjust SP by FrameSize bytes. Save RA, S0, S1
181 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
182 MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator I) const {
184 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
185 if (!NeverUseSaveRestore) {
186 if (isUInt<11>(FrameSize))
187 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
189 int Base = 2040; // should create template function like isUInt that
190 // returns largest possible n bit unsigned integer
191 int64_t Remainder = FrameSize - Base;
192 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
193 if (isInt<16>(-Remainder))
194 BuildAddiuSpImm(MBB, I, -Remainder);
196 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
206 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
208 MIB1.addReg(Mips::SP);
210 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
212 MIB2.addReg(Mips::SP);
214 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
216 MIB3.addReg(Mips::SP);
218 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
222 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
223 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
224 MachineBasicBlock &MBB,
225 MachineBasicBlock::iterator I) const {
226 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
227 if (!NeverUseSaveRestore) {
228 if (isUInt<11>(FrameSize))
229 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
231 int Base = 2040; // should create template function like isUInt that
232 // returns largest possible n bit unsigned integer
233 int64_t Remainder = FrameSize - Base;
234 if (isInt<16>(Remainder))
235 BuildAddiuSpImm(MBB, I, Remainder);
237 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
238 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
242 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
246 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
248 MIB1.addReg(Mips::SP);
250 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
252 MIB0.addReg(Mips::A0);
253 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
255 MIB2.addReg(Mips::SP);
257 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
259 MIB3.addReg(Mips::SP);
265 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
266 // This can only be called at times that we know that there is at least one free
268 // This is clearly safe at prologue and epilogue.
270 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
271 MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator I,
273 unsigned Reg1, unsigned Reg2) const {
274 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
275 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
276 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
277 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
281 // add reg1, reg1, reg2
285 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
287 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
288 MIB2.addReg(Mips::SP, RegState::Kill);
289 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
291 MIB3.addReg(Reg2, RegState::Kill);
292 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
294 MIB4.addReg(Reg1, RegState::Kill);
297 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
298 MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator I) const {
300 assert(false && "adjust stack pointer amount exceeded");
303 /// Adjust SP by Amount bytes.
304 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
305 MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator I) const {
307 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
308 BuildAddiuSpImm(MBB, I, Amount);
310 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
313 /// This function generates the sequence of instructions needed to get the
314 /// result of adding register REG and immediate IMM.
316 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
317 int64_t Imm, MachineBasicBlock &MBB,
318 MachineBasicBlock::iterator II, DebugLoc DL,
319 unsigned &NewImm) const {
321 // given original instruction is:
322 // Instr rx, T[offset] where offset is too big.
324 // lo = offset & 0xFFFF
325 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
327 // let T = temporary register
333 int32_t lo = Imm & 0xFFFF;
334 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
338 rs.enterBasicBlock(&MBB);
341 // we use T0 for the first register, if we need to save something away.
342 // we use T1 for the second register, if we need to save something away.
344 unsigned FirstRegSaved =0, SecondRegSaved=0;
345 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
347 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
349 FirstRegSaved = Reg = Mips::V0;
350 FirstRegSavedTo = Mips::T0;
351 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
355 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
356 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
358 if (FrameReg == Mips::SP) {
359 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
361 if (Reg != Mips::V1) {
362 SecondRegSaved = SpReg = Mips::V1;
363 SecondRegSavedTo = Mips::T1;
366 SecondRegSaved = SpReg = Mips::V0;
367 SecondRegSavedTo = Mips::T0;
369 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
374 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
375 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
379 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
380 .addReg(Reg, RegState::Kill);
381 if (FirstRegSaved || SecondRegSaved) {
384 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
386 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
391 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
392 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
393 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
394 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
395 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
396 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
397 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
398 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
399 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
400 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
403 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator I,
405 unsigned Opc) const {
406 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
410 void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
411 MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
412 unsigned BtOpc, unsigned CmpOpc) const {
413 unsigned regX = I->getOperand(0).getReg();
414 unsigned regY = I->getOperand(1).getReg();
415 MachineBasicBlock *target = I->getOperand(2).getMBB();
416 BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
417 BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
420 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
421 if (validSpImm8(Imm))
422 return get(Mips::AddiuSpImm16);
424 return get(Mips::AddiuSpImmX16);
427 void Mips16InstrInfo::BuildAddiuSpImm
428 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
429 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
430 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
433 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
434 return new Mips16InstrInfo(TM);