1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
27 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
28 : MipsInstrInfo(tm, /* FIXME: set mips16 unconditional br */ 0),
29 RI(*tm.getSubtargetImpl()) {}
31 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned Mips16InstrInfo::
41 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
46 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// store to a stack slot, return the virtual or physical register number of
48 /// the source reg along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than storing to the stack slot.
51 unsigned Mips16InstrInfo::
52 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
57 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator I, DebugLoc DL,
59 unsigned DestReg, unsigned SrcReg,
63 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
64 Mips::CPURegsRegClass.contains(SrcReg))
65 Opc = Mips::MoveR3216;
66 else if (Mips::CPURegsRegClass.contains(DestReg) &&
67 Mips::CPU16RegsRegClass.contains(SrcReg))
68 Opc = Mips::Move32R16;
69 else if ((SrcReg == Mips::HI) &&
70 (Mips::CPU16RegsRegClass.contains(DestReg)))
71 Opc = Mips::Mfhi16, SrcReg = 0;
73 else if ((SrcReg == Mips::LO) &&
74 (Mips::CPU16RegsRegClass.contains(DestReg)))
75 Opc = Mips::Mflo16, SrcReg = 0;
78 assert(Opc && "Cannot copy registers");
80 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
83 MIB.addReg(DestReg, RegState::Define);
86 MIB.addReg(SrcReg, getKillRegState(KillSrc));
89 void Mips16InstrInfo::
90 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned SrcReg, bool isKill, int FI,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const {
95 if (I != MBB.end()) DL = I->getDebugLoc();
96 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
98 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
99 Opc = Mips::SwRxSpImmX16;
100 assert(Opc && "Register class not handled!");
101 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
105 void Mips16InstrInfo::
106 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107 unsigned DestReg, int FI,
108 const TargetRegisterClass *RC,
109 const TargetRegisterInfo *TRI) const {
111 if (I != MBB.end()) DL = I->getDebugLoc();
112 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
115 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
116 Opc = Mips::LwRxSpImmX16;
117 assert(Opc && "Register class not handled!");
118 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
122 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
123 MachineBasicBlock &MBB = *MI->getParent();
125 switch(MI->getDesc().getOpcode()) {
129 ExpandRetRA16(MBB, MI, Mips::JrRa16);
137 /// GetOppositeBranchOpc - Return the inverse of the specified
138 /// opcode, e.g. turning BEQ to BNE.
139 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
140 assert(false && "Implement this function.");
144 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
148 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator I,
150 unsigned Opc) const {
151 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
154 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
155 return new Mips16InstrInfo(TM);