lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 // The overall idea of the PredicateControl class is to chop the Predicates list
  19 // into subsets that are usually overridden independently. This allows
  20 // subclasses to partially override the predicates of their superclasses without
  21 // having to re-add all the existing predicates.
  22 class PredicateControl {
  23   // Predicates for the encoding scheme in use such as HasStdEnc
  24   list<Predicate> EncodingPredicates = [];
  25   // Predicates for anything else
  26   list<Predicate> AdditionalPredicates = [];
  27   list<Predicate> Predicates = !listconcat(EncodingPredicates,
  28                                            AdditionalPredicates);
  29 }
  30
  31 // Like Requires<> but for the AdditionalPredicates list
  32 class AdditionalRequires<list<Predicate> preds> {
  33   list<Predicate> AdditionalPredicates = preds;
  34 }
  35
  36 //===----------------------------------------------------------------------===//
  37 // Register File, Calling Conv, Instruction Descriptions
  38 //===----------------------------------------------------------------------===//
  39
  40 include "MipsRegisterInfo.td"
  41 include "MipsSchedule.td"
  42 include "MipsInstrInfo.td"
  43 include "MipsCallingConv.td"
  44
  45 def MipsInstrInfo : InstrInfo;
  46
  47 //===----------------------------------------------------------------------===//
  48 // Mips Subtarget features                                                    //
  49 //===----------------------------------------------------------------------===//
  50
  51 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  52                                 "General Purpose Registers are 64-bit wide.">;
  53 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  54                                 "Support 64-bit FP registers.">;
  55 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  56                                 "IEEE 754-2008 NaN encoding.">;
  57 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  58                                 "true", "Only supports single precision float">;
  59 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  60                                 "Enable o32 ABI">;
  61 def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
  62                                 "Enable n32 ABI">;
  63 def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
  64                                 "Enable n64 ABI">;
  65 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  66                                 "Enable eabi ABI">;
  67 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  68                                 "true", "Enable vector FPU instructions.">;
  69 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  70                                 "Enable 'signext in register' instructions.">;
  71 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  72                                 "Enable 'conditional move' instructions.">;
  73 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  74                                 "Enable 'byte/half swap' instructions.">;
  75 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  76                                 "Enable 'count leading bits' instructions.">;
  77 def FeatureFPIdx       : SubtargetFeature<"fpidx", "HasFPIdx", "true",
  78                                 "Enable 'FP indexed load/store' instructions.">;
  79 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
  80                                 "Mips32 ISA Support",
  81                                 [FeatureCondMov, FeatureBitCount]>;
  82 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
  83                                 "Mips32r2", "Mips32r2 ISA Support",
  84                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
  85                                  FeatureFPIdx]>;
  86 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
  87                                 "Mips4", "MIPS IV ISA Support",
  88                                 [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
  89                                  FeatureCondMov]>;
  90 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
  91                                 "Mips64", "Mips64 ISA Support",
  92                                 [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
  93 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
  94                                 "Mips64r2", "Mips64r2 ISA Support",
  95                                 [FeatureMips64, FeatureMips32r2]>;
  96
  97 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
  98                                       "Mips16 mode">;
  99
 100 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 101 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
 102                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 103
 104 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 105
 106 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
 107                                          "microMips mode">;
 108
 109 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
 110                                 "true", "Octeon cnMIPS Support",
 111                                 [FeatureMips64r2]>;
 112
 113 //===----------------------------------------------------------------------===//
 114 // Mips processors supported.
 115 //===----------------------------------------------------------------------===//
 116
 117 class Proc<string Name, list<SubtargetFeature> Features>
 118  : Processor<Name, MipsGenericItineraries, Features>;
 119
 120 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 121 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
 122 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
 123 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 124 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
 125 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 126 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 127
 128 def MipsAsmParser : AsmParser {
 129   let ShouldEmitMatchRegisterName = 0;
 130   let MnemonicContainsDot = 1;
 131 }
 132
 133 def MipsAsmParserVariant : AsmParserVariant {
 134   int Variant = 0;
 135
 136   // Recognize hard coded registers.
 137   string RegisterPrefix = "$";
 138 }
 139
 140 def Mips : Target {
 141   let InstructionSet = MipsInstrInfo;
 142   let AssemblyParsers = [MipsAsmParser];
 143   let AssemblyParserVariants = [MipsAsmParserVariant];
 144 }