1 //===- Mips.td - Describe the Mips Target Machine ---------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "../Target.td"
18 //===----------------------------------------------------------------------===//
19 // Register File, Calling Conv, Instruction Descriptions
20 //===----------------------------------------------------------------------===//
22 include "MipsRegisterInfo.td"
23 include "MipsSchedule.td"
24 include "MipsInstrInfo.td"
25 include "MipsCallingConv.td"
27 def MipsInstrInfo : InstrInfo {
28 let TSFlagsFields = [];
29 let TSFlagsShifts = [];
32 //===----------------------------------------------------------------------===//
33 // Mips Subtarget features //
34 //===----------------------------------------------------------------------===//
36 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
37 "General Purpose Registers are 64-bit wide.">;
38 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
39 "Support 64-bit FP registers.">;
40 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
41 "true", "Only supports single precision float">;
42 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
44 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
46 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
48 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
49 "true", "Enable vector FPU instructions.">;
50 def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
51 "Enable 'signext in register' instructions.">;
53 //===----------------------------------------------------------------------===//
54 // Mips processors supported.
55 //===----------------------------------------------------------------------===//
57 class Proc<string Name, list<SubtargetFeature> Features>
58 : Processor<Name, MipsGenericItineraries, Features>;
60 def : Proc<"mips1", []>;
61 def : Proc<"r2000", []>;
62 def : Proc<"r3000", []>;
64 def : Proc<"mips2", [FeatureMips2]>;
65 def : Proc<"r6000", [FeatureMips2]>;
67 // Allegrex is a 32bit subset of r4000, both for interger and fp registers,
68 // but much more similar to Mips2 than Mips3.
69 def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
70 FeatureSEInReg, FeatureVFPU]>;
73 let InstructionSet = MipsInstrInfo;