1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def uimm5_lsl2 : Operand<OtherVT> {
17 let EncoderMethod = "getUImm5Lsl2Encoding";
18 let DecoderMethod = "DecodeUImm5lsl2";
21 def uimm6_lsl2 : Operand<i32> {
22 let EncoderMethod = "getUImm6Lsl2Encoding";
23 let DecoderMethod = "DecodeUImm6Lsl2";
26 def simm9_addiusp : Operand<i32> {
27 let EncoderMethod = "getSImm9AddiuspValue";
28 let DecoderMethod = "DecodeSimm9SP";
31 def uimm3_shift : Operand<i32> {
32 let EncoderMethod = "getUImm3Mod8Encoding";
35 def simm3_lsa2 : Operand<i32> {
36 let EncoderMethod = "getSImm3Lsa2Value";
37 let DecoderMethod = "DecodeAddiur2Simm7";
40 def uimm4_andi : Operand<i32> {
41 let EncoderMethod = "getUImm4AndValue";
42 let DecoderMethod = "DecodeANDI16Imm";
45 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
47 Imm < 28 && Imm > 0);}]>;
49 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
51 def immZExtAndi16 : ImmLeaf<i32,
52 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
53 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
54 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
56 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
58 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
60 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
61 let Name = "MicroMipsMem";
62 let RenderMethod = "addMicroMipsMemOperands";
63 let ParserMethod = "parseMemOperand";
64 let PredicateMethod = "isMemWithGRPMM16Base";
67 class mem_mm_4_generic : Operand<i32> {
68 let PrintMethod = "printMemOperand";
69 let MIOperandInfo = (ops GPRMM16, simm4);
70 let OperandType = "OPERAND_MEMORY";
71 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
74 def mem_mm_4 : mem_mm_4_generic {
75 let EncoderMethod = "getMemEncodingMMImm4";
78 def mem_mm_4_lsl1 : mem_mm_4_generic {
79 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
82 def mem_mm_4_lsl2 : mem_mm_4_generic {
83 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
86 def MicroMipsMemSPAsmOperand : AsmOperandClass {
87 let Name = "MicroMipsMemSP";
88 let RenderMethod = "addMemOperands";
89 let ParserMethod = "parseMemOperand";
90 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
93 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
94 let PrintMethod = "printMemOperand";
95 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
96 let OperandType = "OPERAND_MEMORY";
97 let ParserMatchClass = MicroMipsMemSPAsmOperand;
98 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
101 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
104 let OperandType = "OPERAND_MEMORY";
105 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
108 def mem_mm_12 : Operand<i32> {
109 let PrintMethod = "printMemOperand";
110 let MIOperandInfo = (ops GPR32, simm12);
111 let EncoderMethod = "getMemEncodingMMImm12";
112 let ParserMatchClass = MipsMemAsmOperand;
113 let OperandType = "OPERAND_MEMORY";
116 def MipsMemUimm4AsmOperand : AsmOperandClass {
117 let Name = "MemOffsetUimm4";
118 let SuperClasses = [MipsMemAsmOperand];
119 let RenderMethod = "addMemOperands";
120 let ParserMethod = "parseMemOperand";
121 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
124 def mem_mm_4sp : Operand<i32> {
125 let PrintMethod = "printMemOperand";
126 let MIOperandInfo = (ops GPR32, uimm8);
127 let EncoderMethod = "getMemEncodingMMImm4sp";
128 let ParserMatchClass = MipsMemUimm4AsmOperand;
129 let OperandType = "OPERAND_MEMORY";
132 def jmptarget_mm : Operand<OtherVT> {
133 let EncoderMethod = "getJumpTargetOpValueMM";
136 def calltarget_mm : Operand<iPTR> {
137 let EncoderMethod = "getJumpTargetOpValueMM";
140 def brtarget7_mm : Operand<OtherVT> {
141 let EncoderMethod = "getBranchTarget7OpValueMM";
142 let OperandType = "OPERAND_PCREL";
143 let DecoderMethod = "DecodeBranchTarget7MM";
144 let ParserMatchClass = MipsJumpTargetAsmOperand;
147 def brtarget10_mm : Operand<OtherVT> {
148 let EncoderMethod = "getBranchTargetOpValueMMPC10";
149 let OperandType = "OPERAND_PCREL";
150 let DecoderMethod = "DecodeBranchTarget10MM";
151 let ParserMatchClass = MipsJumpTargetAsmOperand;
154 def brtarget_mm : Operand<OtherVT> {
155 let EncoderMethod = "getBranchTargetOpValueMM";
156 let OperandType = "OPERAND_PCREL";
157 let DecoderMethod = "DecodeBranchTargetMM";
158 let ParserMatchClass = MipsJumpTargetAsmOperand;
161 def simm23_lsl2 : Operand<i32> {
162 let EncoderMethod = "getSimm23Lsl2Encoding";
163 let DecoderMethod = "DecodeSimm23Lsl2";
166 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
167 RegisterOperand RO> :
168 InstSE<(outs), (ins RO:$rs, opnd:$offset),
169 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
171 let isTerminator = 1;
172 let hasDelaySlot = 0;
176 let canFoldAsLoad = 1 in
177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
179 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
180 !strconcat(opstr, "\t$rt, $addr"),
181 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
183 let DecoderMethod = "DecodeMemMMImm12";
184 string Constraints = "$src = $rt";
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
189 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
190 !strconcat(opstr, "\t$rt, $addr"),
191 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
192 let DecoderMethod = "DecodeMemMMImm12";
195 /// A register pair used by load/store pair instructions.
196 def RegPairAsmOperand : AsmOperandClass {
197 let Name = "RegPair";
198 let ParserMethod = "parseRegisterPair";
201 def regpair : Operand<i32> {
202 let EncoderMethod = "getRegisterPairOpValue";
203 let ParserMatchClass = RegPairAsmOperand;
204 let PrintMethod = "printRegisterPair";
205 let DecoderMethod = "DecodeRegPairOperand";
206 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
209 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
210 ComplexPattern Addr = addr> :
211 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
212 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
213 let DecoderMethod = "DecodeMemMMImm12";
217 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
218 ComplexPattern Addr = addr> :
219 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
220 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
221 let DecoderMethod = "DecodeMemMMImm12";
225 class LLBaseMM<string opstr, RegisterOperand RO> :
226 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
227 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
228 let DecoderMethod = "DecodeMemMMImm12";
232 class SCBaseMM<string opstr, RegisterOperand RO> :
233 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
234 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
235 let DecoderMethod = "DecodeMemMMImm12";
237 let Constraints = "$rt = $dst";
240 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
241 InstrItinClass Itin = NoItinerary> :
242 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
243 !strconcat(opstr, "\t$rt, $addr"),
244 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
245 let DecoderMethod = "DecodeMemMMImm12";
246 let canFoldAsLoad = 1;
250 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
251 InstrItinClass Itin = NoItinerary,
252 SDPatternOperator OpNode = null_frag> :
253 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
254 !strconcat(opstr, "\t$rd, $rs, $rt"),
255 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
256 let isCommutable = isComm;
259 class AndImmMM16<string opstr, RegisterOperand RO,
260 InstrItinClass Itin = NoItinerary> :
261 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
262 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
264 class LogicRMM16<string opstr, RegisterOperand RO,
265 InstrItinClass Itin = NoItinerary,
266 SDPatternOperator OpNode = null_frag> :
267 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
268 !strconcat(opstr, "\t$rt, $rs"),
269 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
270 let isCommutable = 1;
271 let Constraints = "$rt = $dst";
274 class NotMM16<string opstr, RegisterOperand RO> :
275 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
276 !strconcat(opstr, "\t$rt, $rs"),
277 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
279 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
280 InstrItinClass Itin = NoItinerary> :
281 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
282 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
284 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
285 InstrItinClass Itin, Operand MemOpnd> :
286 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
287 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
288 let DecoderMethod = "DecodeMemMMImm4";
289 let canFoldAsLoad = 1;
293 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
294 SDPatternOperator OpNode, InstrItinClass Itin,
296 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
297 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
298 let DecoderMethod = "DecodeMemMMImm4";
302 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
304 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
305 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
306 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
307 let canFoldAsLoad = 1;
311 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
313 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
314 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
315 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
319 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
321 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
322 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
323 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
324 let canFoldAsLoad = 1;
328 class AddImmUR2<string opstr, RegisterOperand RO> :
329 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
330 !strconcat(opstr, "\t$rd, $rs, $imm"),
331 [], NoItinerary, FrmR> {
332 let isCommutable = 1;
335 class AddImmUS5<string opstr, RegisterOperand RO> :
336 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
337 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
338 let Constraints = "$rd = $dst";
341 class AddImmUR1SP<string opstr, RegisterOperand RO> :
342 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
343 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
345 class AddImmUSP<string opstr> :
346 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
347 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
349 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
350 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
351 [], II_MFHI_MFLO, FrmR> {
353 let hasSideEffects = 0;
356 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
357 InstrItinClass Itin = NoItinerary> :
358 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
359 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
360 let isCommutable = isComm;
361 let isReMaterializable = 1;
364 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
365 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
366 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
367 let isReMaterializable = 1;
370 // 16-bit Jump and Link (Call)
371 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
372 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
373 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
375 let hasDelaySlot = 1;
380 class JumpRegMM16<string opstr, RegisterOperand RO> :
381 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
382 [], IIBranch, FrmR> {
383 let hasDelaySlot = 1;
385 let isIndirectBranch = 1;
388 // Base class for JRADDIUSP instruction.
389 class JumpRAddiuStackMM16 :
390 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
391 [], IIBranch, FrmR> {
392 let isTerminator = 1;
395 let isIndirectBranch = 1;
398 // 16-bit Jump and Link (Call) - Short Delay Slot
399 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
400 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
401 [], IIBranch, FrmR> {
403 let hasDelaySlot = 1;
407 // 16-bit Jump Register Compact - No delay slot
408 class JumpRegCMM16<string opstr, RegisterOperand RO> :
409 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
410 [], IIBranch, FrmR> {
411 let isTerminator = 1;
414 let isIndirectBranch = 1;
417 // Break16 and Sdbbp16
418 class BrkSdbbp16MM<string opstr> :
419 MicroMipsInst16<(outs), (ins uimm4:$code_),
420 !strconcat(opstr, "\t$code_"),
421 [], NoItinerary, FrmOther>;
423 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
424 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
425 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
427 let isTerminator = 1;
428 let hasDelaySlot = 1;
432 // MicroMIPS Jump and Link (Call) - Short Delay Slot
433 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
434 class JumpLinkMM<string opstr, DAGOperand opnd> :
435 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
436 [], IIBranch, FrmJ, opstr> {
437 let DecoderMethod = "DecodeJumpTargetMM";
440 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
441 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
444 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
445 RegisterOperand RO> :
446 InstSE<(outs), (ins RO:$rs, opnd:$offset),
447 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
450 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
451 InstrItinClass Itin = NoItinerary,
452 SDPatternOperator OpNode = null_frag> :
453 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
454 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
456 class AddImmUPC<string opstr, RegisterOperand RO> :
457 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
458 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
460 /// A list of registers used by load/store multiple instructions.
461 def RegListAsmOperand : AsmOperandClass {
462 let Name = "RegList";
463 let ParserMethod = "parseRegisterList";
466 def reglist : Operand<i32> {
467 let EncoderMethod = "getRegisterListOpValue";
468 let ParserMatchClass = RegListAsmOperand;
469 let PrintMethod = "printRegisterList";
470 let DecoderMethod = "DecodeRegListOperand";
473 def RegList16AsmOperand : AsmOperandClass {
474 let Name = "RegList16";
475 let ParserMethod = "parseRegisterList";
476 let PredicateMethod = "isRegList16";
477 let RenderMethod = "addRegListOperands";
480 def reglist16 : Operand<i32> {
481 let EncoderMethod = "getRegisterListOpValue16";
482 let DecoderMethod = "DecodeRegListOperand16";
483 let PrintMethod = "printRegisterList";
484 let ParserMatchClass = RegList16AsmOperand;
487 class StoreMultMM<string opstr,
488 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
489 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
490 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
491 let DecoderMethod = "DecodeMemMMImm12";
495 class LoadMultMM<string opstr,
496 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
497 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
498 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
499 let DecoderMethod = "DecodeMemMMImm12";
503 class StoreMultMM16<string opstr,
504 InstrItinClass Itin = NoItinerary,
505 ComplexPattern Addr = addr> :
506 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
507 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
511 class LoadMultMM16<string opstr,
512 InstrItinClass Itin = NoItinerary,
513 ComplexPattern Addr = addr> :
514 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
515 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
519 class UncondBranchMM16<string opstr> :
520 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
521 !strconcat(opstr, "\t$offset"),
522 [], IIBranch, FrmI> {
524 let isTerminator = 1;
526 let hasDelaySlot = 1;
527 let Predicates = [RelocPIC, InMicroMips];
531 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
533 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
535 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
536 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
538 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
540 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
542 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
543 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
545 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
547 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
548 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
549 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
550 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
551 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
552 LOAD_STORE_FM_MM16<0x1a>;
553 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
554 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
555 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
556 II_SH, mem_mm_4_lsl1>,
557 LOAD_STORE_FM_MM16<0x2a>;
558 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
559 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
560 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
561 LOAD_GP_FM_MM16<0x19>;
562 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
563 LOAD_STORE_SP_FM_MM16<0x12>;
564 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
565 LOAD_STORE_SP_FM_MM16<0x32>;
566 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
567 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
568 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
569 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
570 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
571 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
572 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
573 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
575 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
576 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
577 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
578 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
579 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
580 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
581 BEQNEZ_FM_MM16<0x23>;
582 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
583 BEQNEZ_FM_MM16<0x2b>;
584 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
585 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
586 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
588 class WaitMM<string opstr> :
589 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
590 NoItinerary, FrmOther, opstr>;
592 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
593 /// Compact Branch Instructions
594 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
595 COMPACT_BRANCH_FM_MM<0x7>;
596 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
597 COMPACT_BRANCH_FM_MM<0x5>;
599 /// Arithmetic Instructions (ALU Immediate)
600 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
602 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
604 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
606 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
608 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
610 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
612 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
614 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
616 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
619 /// Arithmetic Instructions (3-Operand, R-Type)
620 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
621 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
622 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
623 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
624 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
625 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
626 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
628 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
630 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
632 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
634 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
635 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
637 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
639 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
641 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
644 /// Arithmetic Instructions with PC and Immediate
645 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
647 /// Shift Instructions
648 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
650 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
652 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
654 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
656 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
658 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
660 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
662 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
665 /// Load and Store Instructions - aligned
666 let DecoderMethod = "DecodeMemMMImm16" in {
667 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
668 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
669 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
670 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
671 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
672 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
673 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
674 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
677 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
679 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
681 /// Load and Store Instructions - unaligned
682 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
684 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
686 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
688 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
691 /// Load and Store Instructions - multiple
692 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
693 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
694 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
695 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
697 /// Load and Store Pair Instructions
698 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
699 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
701 /// Load and Store multiple pseudo Instructions
702 class LoadWordMultMM<string instr_asm > :
703 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
704 !strconcat(instr_asm, "\t$rt, $addr")> ;
706 class StoreWordMultMM<string instr_asm > :
707 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
708 !strconcat(instr_asm, "\t$rt, $addr")> ;
711 def SWM_MM : StoreWordMultMM<"swm">;
712 def LWM_MM : LoadWordMultMM<"lwm">;
715 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
716 NoItinerary>, ADD_FM_MM<0, 0x58>;
717 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
718 NoItinerary>, ADD_FM_MM<0, 0x18>;
719 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
720 CMov_F_I_FM_MM<0x25>;
721 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
724 /// Move to/from HI/LO
725 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
727 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
729 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
731 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
734 /// Multiply Add/Sub Instructions
735 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
736 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
737 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
738 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
741 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
743 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
746 /// Sign Ext In Register Instructions.
747 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
748 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
749 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
750 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
752 /// Word Swap Bytes Within Halfwords
753 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
756 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
758 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
761 /// Jump Instructions
762 let DecoderMethod = "DecodeJumpTargetMM" in {
763 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
765 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
767 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
768 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
770 /// Jump Instructions - Short Delay Slot
771 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
772 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
774 /// Branch Instructions
775 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
777 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
779 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
781 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
783 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
785 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
787 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
789 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
792 /// Branch Instructions - Short Delay Slot
793 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
794 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
795 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
796 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
798 /// Control Instructions
799 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
800 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
801 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
802 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
803 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
804 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
805 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
807 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
810 /// Trap Instructions
811 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
812 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
813 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
814 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
815 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
816 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
818 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
819 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
820 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
821 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
822 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
823 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
825 /// Load-linked, Store-conditional
826 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
827 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
829 let DecoderMethod = "DecodeCacheOpMM" in {
830 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
831 CACHE_PREF_FM_MM<0x08, 0x6>;
832 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
833 CACHE_PREF_FM_MM<0x18, 0x2>;
835 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
836 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
837 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
839 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
840 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
841 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
842 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
844 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
845 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
848 let Predicates = [InMicroMips] in {
850 //===----------------------------------------------------------------------===//
851 // MicroMips arbitrary patterns that map to one or more instructions
852 //===----------------------------------------------------------------------===//
854 def : MipsPat<(i32 immLi16:$imm),
855 (LI16_MM immLi16:$imm)>;
856 def : MipsPat<(i32 immSExt16:$imm),
857 (ADDiu_MM ZERO, immSExt16:$imm)>;
858 def : MipsPat<(i32 immZExt16:$imm),
859 (ORi_MM ZERO, immZExt16:$imm)>;
861 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
862 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
863 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
864 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
865 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
866 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
868 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
869 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
870 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
871 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
873 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
874 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
875 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
876 (SLL_MM GPR32:$src, immZExt5:$imm)>;
878 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
879 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
880 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
881 (SRL_MM GPR32:$src, immZExt5:$imm)>;
883 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
884 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
885 def : MipsPat<(store GPR32:$src, addr:$addr),
886 (SW_MM GPR32:$src, addr:$addr)>;
888 def : MipsPat<(load addrimm4lsl2:$addr),
889 (LW16_MM addrimm4lsl2:$addr)>;
890 def : MipsPat<(load addr:$addr),
893 //===----------------------------------------------------------------------===//
894 // MicroMips instruction aliases
895 //===----------------------------------------------------------------------===//
897 class UncondBranchMMPseudo<string opstr> :
898 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
899 !strconcat(opstr, "\t$offset")>;
901 def B_MM_Pseudo : UncondBranchMMPseudo<"b">;
903 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
904 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
905 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;