1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def li_simm7 : Operand<i32> {
7 let DecoderMethod = "DecodeLiSimm7";
10 def simm12 : Operand<i32> {
11 let DecoderMethod = "DecodeSimm12";
14 def uimm5_lsl2 : Operand<OtherVT> {
15 let EncoderMethod = "getUImm5Lsl2Encoding";
16 let DecoderMethod = "DecodeUImm5lsl2";
19 def uimm6_lsl2 : Operand<i32> {
20 let EncoderMethod = "getUImm6Lsl2Encoding";
21 let DecoderMethod = "DecodeUImm6Lsl2";
24 def simm9_addiusp : Operand<i32> {
25 let EncoderMethod = "getSImm9AddiuspValue";
26 let DecoderMethod = "DecodeSimm9SP";
29 def uimm3_shift : Operand<i32> {
30 let EncoderMethod = "getUImm3Mod8Encoding";
33 def simm3_lsa2 : Operand<i32> {
34 let EncoderMethod = "getSImm3Lsa2Value";
35 let DecoderMethod = "DecodeAddiur2Simm7";
38 def uimm4_andi : Operand<i32> {
39 let EncoderMethod = "getUImm4AndValue";
40 let DecoderMethod = "DecodeANDI16Imm";
43 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
45 Imm < 28 && Imm > 0);}]>;
47 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
49 def immZExtAndi16 : ImmLeaf<i32,
50 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
51 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
52 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
54 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
56 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
58 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
59 let Name = "MicroMipsMem";
60 let RenderMethod = "addMicroMipsMemOperands";
61 let ParserMethod = "parseMemOperand";
62 let PredicateMethod = "isMemWithGRPMM16Base";
65 class mem_mm_4_generic : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let MIOperandInfo = (ops ptr_rc, simm4);
68 let OperandType = "OPERAND_MEMORY";
69 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
72 def mem_mm_4 : mem_mm_4_generic {
73 let EncoderMethod = "getMemEncodingMMImm4";
76 def mem_mm_4_lsl1 : mem_mm_4_generic {
77 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
80 def mem_mm_4_lsl2 : mem_mm_4_generic {
81 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
84 def MicroMipsMemSPAsmOperand : AsmOperandClass {
85 let Name = "MicroMipsMemSP";
86 let RenderMethod = "addMemOperands";
87 let ParserMethod = "parseMemOperand";
88 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
91 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
92 let PrintMethod = "printMemOperand";
93 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
94 let OperandType = "OPERAND_MEMORY";
95 let ParserMatchClass = MicroMipsMemSPAsmOperand;
96 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
99 def mem_mm_12 : Operand<i32> {
100 let PrintMethod = "printMemOperand";
101 let MIOperandInfo = (ops GPR32, simm12);
102 let EncoderMethod = "getMemEncodingMMImm12";
103 let ParserMatchClass = MipsMemAsmOperand;
104 let OperandType = "OPERAND_MEMORY";
107 def MipsMemUimm4AsmOperand : AsmOperandClass {
108 let Name = "MemOffsetUimm4";
109 let SuperClasses = [MipsMemAsmOperand];
110 let RenderMethod = "addMemOperands";
111 let ParserMethod = "parseMemOperand";
112 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
115 def mem_mm_4sp : Operand<i32> {
116 let PrintMethod = "printMemOperand";
117 let MIOperandInfo = (ops GPR32, uimm8);
118 let EncoderMethod = "getMemEncodingMMImm4sp";
119 let ParserMatchClass = MipsMemUimm4AsmOperand;
120 let OperandType = "OPERAND_MEMORY";
123 def jmptarget_mm : Operand<OtherVT> {
124 let EncoderMethod = "getJumpTargetOpValueMM";
127 def calltarget_mm : Operand<iPTR> {
128 let EncoderMethod = "getJumpTargetOpValueMM";
131 def brtarget7_mm : Operand<OtherVT> {
132 let EncoderMethod = "getBranchTarget7OpValueMM";
133 let OperandType = "OPERAND_PCREL";
134 let DecoderMethod = "DecodeBranchTarget7MM";
135 let ParserMatchClass = MipsJumpTargetAsmOperand;
138 def brtarget_mm : Operand<OtherVT> {
139 let EncoderMethod = "getBranchTargetOpValueMM";
140 let OperandType = "OPERAND_PCREL";
141 let DecoderMethod = "DecodeBranchTargetMM";
144 def simm23_lsl2 : Operand<i32> {
145 let EncoderMethod = "getSimm23Lsl2Encoding";
146 let DecoderMethod = "DecodeSimm23Lsl2";
149 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
150 RegisterOperand RO> :
151 InstSE<(outs), (ins RO:$rs, opnd:$offset),
152 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
154 let isTerminator = 1;
155 let hasDelaySlot = 0;
159 let canFoldAsLoad = 1 in
160 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
162 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
163 !strconcat(opstr, "\t$rt, $addr"),
164 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
166 let DecoderMethod = "DecodeMemMMImm12";
167 string Constraints = "$src = $rt";
170 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
172 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
173 !strconcat(opstr, "\t$rt, $addr"),
174 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
175 let DecoderMethod = "DecodeMemMMImm12";
178 /// A register pair used by load/store pair instructions.
179 def RegPairAsmOperand : AsmOperandClass {
180 let Name = "RegPair";
181 let ParserMethod = "parseRegisterPair";
184 def regpair : Operand<i32> {
185 let EncoderMethod = "getRegisterPairOpValue";
186 let ParserMatchClass = RegPairAsmOperand;
187 let PrintMethod = "printRegisterPair";
188 let DecoderMethod = "DecodeRegPairOperand";
189 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
192 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
193 ComplexPattern Addr = addr> :
194 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
195 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
196 let DecoderMethod = "DecodeMemMMImm12";
200 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
201 ComplexPattern Addr = addr> :
202 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
203 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
204 let DecoderMethod = "DecodeMemMMImm12";
208 class LLBaseMM<string opstr, RegisterOperand RO> :
209 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
210 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
211 let DecoderMethod = "DecodeMemMMImm12";
215 class SCBaseMM<string opstr, RegisterOperand RO> :
216 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
217 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
218 let DecoderMethod = "DecodeMemMMImm12";
220 let Constraints = "$rt = $dst";
223 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
224 InstrItinClass Itin = NoItinerary> :
225 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
226 !strconcat(opstr, "\t$rt, $addr"),
227 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
228 let DecoderMethod = "DecodeMemMMImm12";
229 let canFoldAsLoad = 1;
233 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
234 InstrItinClass Itin = NoItinerary,
235 SDPatternOperator OpNode = null_frag> :
236 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
237 !strconcat(opstr, "\t$rd, $rs, $rt"),
238 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
239 let isCommutable = isComm;
242 class AndImmMM16<string opstr, RegisterOperand RO,
243 InstrItinClass Itin = NoItinerary> :
244 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
245 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
247 class LogicRMM16<string opstr, RegisterOperand RO,
248 InstrItinClass Itin = NoItinerary,
249 SDPatternOperator OpNode = null_frag> :
250 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
251 !strconcat(opstr, "\t$rt, $rs"),
252 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
253 let isCommutable = 1;
254 let Constraints = "$rt = $dst";
257 class NotMM16<string opstr, RegisterOperand RO> :
258 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
259 !strconcat(opstr, "\t$rt, $rs"),
260 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
262 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
263 InstrItinClass Itin = NoItinerary> :
264 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
265 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
267 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
268 InstrItinClass Itin, Operand MemOpnd> :
269 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
270 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
271 let DecoderMethod = "DecodeMemMMImm4";
272 let canFoldAsLoad = 1;
276 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
277 SDPatternOperator OpNode, InstrItinClass Itin,
279 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
280 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
281 let DecoderMethod = "DecodeMemMMImm4";
285 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
287 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
288 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
289 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
290 let canFoldAsLoad = 1;
294 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
296 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
297 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
298 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
302 class AddImmUR2<string opstr, RegisterOperand RO> :
303 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
304 !strconcat(opstr, "\t$rd, $rs, $imm"),
305 [], NoItinerary, FrmR> {
306 let isCommutable = 1;
309 class AddImmUS5<string opstr, RegisterOperand RO> :
310 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
311 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
312 let Constraints = "$rd = $dst";
315 class AddImmUR1SP<string opstr, RegisterOperand RO> :
316 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
317 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
319 class AddImmUSP<string opstr> :
320 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
321 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
323 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
324 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
325 [], II_MFHI_MFLO, FrmR> {
327 let hasSideEffects = 0;
330 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
331 InstrItinClass Itin = NoItinerary> :
332 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
333 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
334 let isCommutable = isComm;
335 let isReMaterializable = 1;
338 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
339 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
340 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
341 let isReMaterializable = 1;
344 // 16-bit Jump and Link (Call)
345 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
346 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
347 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
349 let hasDelaySlot = 1;
354 class JumpRegMM16<string opstr, RegisterOperand RO> :
355 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
356 [], IIBranch, FrmR> {
357 let hasDelaySlot = 1;
359 let isIndirectBranch = 1;
362 // Base class for JRADDIUSP instruction.
363 class JumpRAddiuStackMM16 :
364 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
365 [], IIBranch, FrmR> {
366 let isTerminator = 1;
369 let isIndirectBranch = 1;
372 // 16-bit Jump and Link (Call) - Short Delay Slot
373 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
374 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
375 [], IIBranch, FrmR> {
377 let hasDelaySlot = 1;
381 // 16-bit Jump Register Compact - No delay slot
382 class JumpRegCMM16<string opstr, RegisterOperand RO> :
383 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
384 [], IIBranch, FrmR> {
385 let isTerminator = 1;
388 let isIndirectBranch = 1;
391 // Break16 and Sdbbp16
392 class BrkSdbbp16MM<string opstr> :
393 MicroMipsInst16<(outs), (ins uimm4:$code_),
394 !strconcat(opstr, "\t$code_"),
395 [], NoItinerary, FrmOther>;
397 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
398 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
399 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
401 let isTerminator = 1;
402 let hasDelaySlot = 1;
406 // MicroMIPS Jump and Link (Call) - Short Delay Slot
407 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
408 class JumpLinkMM<string opstr, DAGOperand opnd> :
409 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
410 [], IIBranch, FrmJ, opstr> {
411 let DecoderMethod = "DecodeJumpTargetMM";
414 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
415 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
418 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
419 RegisterOperand RO> :
420 InstSE<(outs), (ins RO:$rs, opnd:$offset),
421 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
424 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
425 InstrItinClass Itin = NoItinerary,
426 SDPatternOperator OpNode = null_frag> :
427 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
428 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
430 class AddImmUPC<string opstr, RegisterOperand RO> :
431 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
432 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
434 /// A list of registers used by load/store multiple instructions.
435 def RegListAsmOperand : AsmOperandClass {
436 let Name = "RegList";
437 let ParserMethod = "parseRegisterList";
440 def reglist : Operand<i32> {
441 let EncoderMethod = "getRegisterListOpValue";
442 let ParserMatchClass = RegListAsmOperand;
443 let PrintMethod = "printRegisterList";
444 let DecoderMethod = "DecodeRegListOperand";
447 def RegList16AsmOperand : AsmOperandClass {
448 let Name = "RegList16";
449 let ParserMethod = "parseRegisterList";
450 let PredicateMethod = "isRegList16";
451 let RenderMethod = "addRegListOperands";
454 def reglist16 : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue16";
456 let DecoderMethod = "DecodeRegListOperand16";
457 let PrintMethod = "printRegisterList";
458 let ParserMatchClass = RegList16AsmOperand;
461 class StoreMultMM<string opstr,
462 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
463 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
464 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
465 let DecoderMethod = "DecodeMemMMImm12";
469 class LoadMultMM<string opstr,
470 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
471 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
472 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
473 let DecoderMethod = "DecodeMemMMImm12";
477 class StoreMultMM16<string opstr,
478 InstrItinClass Itin = NoItinerary,
479 ComplexPattern Addr = addr> :
480 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
481 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
485 class LoadMultMM16<string opstr,
486 InstrItinClass Itin = NoItinerary,
487 ComplexPattern Addr = addr> :
488 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
489 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
493 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
495 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
497 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
498 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
500 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
502 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
504 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
505 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
507 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
509 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
510 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
511 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
512 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
513 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
514 LOAD_STORE_FM_MM16<0x1a>;
515 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
516 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
517 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
518 II_SH, mem_mm_4_lsl1>,
519 LOAD_STORE_FM_MM16<0x2a>;
520 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
521 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
522 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
523 LOAD_STORE_SP_FM_MM16<0x12>;
524 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
525 LOAD_STORE_SP_FM_MM16<0x32>;
526 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
527 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
528 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
529 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
530 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
531 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
532 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
533 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
535 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
536 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
537 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
538 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
539 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
540 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
541 BEQNEZ_FM_MM16<0x23>;
542 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
543 BEQNEZ_FM_MM16<0x2b>;
544 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
545 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
547 class WaitMM<string opstr> :
548 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
549 NoItinerary, FrmOther, opstr>;
551 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
552 /// Compact Branch Instructions
553 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
554 COMPACT_BRANCH_FM_MM<0x7>;
555 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
556 COMPACT_BRANCH_FM_MM<0x5>;
558 /// Arithmetic Instructions (ALU Immediate)
559 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
561 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
563 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
565 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
567 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
569 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
571 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
573 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
575 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
578 /// Arithmetic Instructions (3-Operand, R-Type)
579 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
580 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
581 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
582 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
583 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
584 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
585 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
587 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
589 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
591 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
593 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
594 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
596 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
598 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
600 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
603 /// Arithmetic Instructions with PC and Immediate
604 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
606 /// Shift Instructions
607 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
609 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
611 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
613 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
615 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
617 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
619 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
621 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
624 /// Load and Store Instructions - aligned
625 let DecoderMethod = "DecodeMemMMImm16" in {
626 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
627 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
628 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
629 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
630 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
631 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
632 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
633 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
636 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
638 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
640 /// Load and Store Instructions - unaligned
641 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
643 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
645 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
647 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
650 /// Load and Store Instructions - multiple
651 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
652 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
653 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
654 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
656 /// Load and Store Pair Instructions
657 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
658 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
661 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
662 NoItinerary>, ADD_FM_MM<0, 0x58>;
663 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
664 NoItinerary>, ADD_FM_MM<0, 0x18>;
665 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
666 CMov_F_I_FM_MM<0x25>;
667 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
670 /// Move to/from HI/LO
671 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
673 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
675 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
677 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
680 /// Multiply Add/Sub Instructions
681 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
682 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
683 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
684 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
687 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
689 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
692 /// Sign Ext In Register Instructions.
693 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
694 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
695 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
696 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
698 /// Word Swap Bytes Within Halfwords
699 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
702 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
704 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
707 /// Jump Instructions
708 let DecoderMethod = "DecodeJumpTargetMM" in {
709 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
711 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
713 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
714 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
716 /// Jump Instructions - Short Delay Slot
717 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
718 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
720 /// Branch Instructions
721 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
723 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
725 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
727 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
729 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
731 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
733 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
735 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
738 /// Branch Instructions - Short Delay Slot
739 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
740 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
741 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
742 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
744 /// Control Instructions
745 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
746 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
747 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
748 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
749 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
750 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
751 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
753 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
756 /// Trap Instructions
757 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
758 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
759 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
760 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
761 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
762 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
764 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
765 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
766 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
767 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
768 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
769 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
771 /// Load-linked, Store-conditional
772 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
773 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
775 let DecoderMethod = "DecodeCacheOpMM" in {
776 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
777 CACHE_PREF_FM_MM<0x08, 0x6>;
778 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
779 CACHE_PREF_FM_MM<0x18, 0x2>;
781 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
782 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
783 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
785 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
786 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
787 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
788 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
790 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
791 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
794 let Predicates = [InMicroMips] in {
796 //===----------------------------------------------------------------------===//
797 // MicroMips arbitrary patterns that map to one or more instructions
798 //===----------------------------------------------------------------------===//
800 def : MipsPat<(i32 immLi16:$imm),
801 (LI16_MM immLi16:$imm)>;
802 def : MipsPat<(i32 immSExt16:$imm),
803 (ADDiu_MM ZERO, immSExt16:$imm)>;
804 def : MipsPat<(i32 immZExt16:$imm),
805 (ORi_MM ZERO, immZExt16:$imm)>;
807 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
808 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
809 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
810 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
811 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
812 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
814 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
815 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
816 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
817 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
819 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
820 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
821 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
822 (SLL_MM GPR32:$src, immZExt5:$imm)>;
824 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
825 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
826 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
827 (SRL_MM GPR32:$src, immZExt5:$imm)>;
829 //===----------------------------------------------------------------------===//
830 // MicroMips instruction aliases
831 //===----------------------------------------------------------------------===//
833 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
834 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
835 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;