1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
5 def simm12 : Operand<i32> {
6 let DecoderMethod = "DecodeSimm12";
9 def uimm5_lsl2 : Operand<OtherVT> {
10 let EncoderMethod = "getUImm5Lsl2Encoding";
13 def simm9_addiusp : Operand<i32> {
14 let EncoderMethod = "getSImm9AddiuspValue";
17 def mem_mm_12 : Operand<i32> {
18 let PrintMethod = "printMemOperand";
19 let MIOperandInfo = (ops GPR32, simm12);
20 let EncoderMethod = "getMemEncodingMMImm12";
21 let ParserMatchClass = MipsMemAsmOperand;
22 let OperandType = "OPERAND_MEMORY";
25 def jmptarget_mm : Operand<OtherVT> {
26 let EncoderMethod = "getJumpTargetOpValueMM";
29 def calltarget_mm : Operand<iPTR> {
30 let EncoderMethod = "getJumpTargetOpValueMM";
33 def brtarget_mm : Operand<OtherVT> {
34 let EncoderMethod = "getBranchTargetOpValueMM";
35 let OperandType = "OPERAND_PCREL";
36 let DecoderMethod = "DecodeBranchTargetMM";
39 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
41 InstSE<(outs), (ins RO:$rs, opnd:$offset),
42 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
49 let canFoldAsLoad = 1 in
50 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
52 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
53 !strconcat(opstr, "\t$rt, $addr"),
54 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
56 let DecoderMethod = "DecodeMemMMImm12";
57 string Constraints = "$src = $rt";
60 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
62 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
63 !strconcat(opstr, "\t$rt, $addr"),
64 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
65 let DecoderMethod = "DecodeMemMMImm12";
68 class LLBaseMM<string opstr, RegisterOperand RO> :
69 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
70 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
71 let DecoderMethod = "DecodeMemMMImm12";
75 class SCBaseMM<string opstr, RegisterOperand RO> :
76 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
77 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
78 let DecoderMethod = "DecodeMemMMImm12";
80 let Constraints = "$rt = $dst";
83 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
84 InstrItinClass Itin = NoItinerary> :
85 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
86 !strconcat(opstr, "\t$rt, $addr"),
87 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
88 let DecoderMethod = "DecodeMemMMImm12";
89 let canFoldAsLoad = 1;
93 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
94 InstrItinClass Itin = NoItinerary,
95 SDPatternOperator OpNode = null_frag> :
96 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
97 !strconcat(opstr, "\t$rd, $rs, $rt"),
98 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
99 let isCommutable = isComm;
102 class LogicRMM16<string opstr, RegisterOperand RO,
103 InstrItinClass Itin = NoItinerary,
104 SDPatternOperator OpNode = null_frag> :
105 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
106 !strconcat(opstr, "\t$rt, $rs"),
107 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
108 let isCommutable = 1;
109 let Constraints = "$rt = $dst";
112 class NotMM16<string opstr, RegisterOperand RO> :
113 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
114 !strconcat(opstr, "\t$rt, $rs"),
115 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
117 class AddImmUS5<string opstr, RegisterOperand RO> :
118 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
119 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
120 let Constraints = "$rd = $dst";
121 let isCommutable = 1;
124 class AddImmUSP<string opstr> :
125 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
126 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
128 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
129 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
130 [], II_MFHI_MFLO, FrmR> {
132 let hasSideEffects = 0;
135 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
136 InstrItinClass Itin = NoItinerary> :
137 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
138 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
139 let isCommutable = isComm;
140 let isReMaterializable = 1;
143 // 16-bit Jump and Link (Call)
144 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
145 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
146 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
148 let hasDelaySlot = 1;
153 class JumpRegMM16<string opstr, RegisterOperand RO> :
154 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
155 [], IIBranch, FrmR> {
156 let hasDelaySlot = 1;
158 let isIndirectBranch = 1;
161 // Base class for JRADDIUSP instruction.
162 class JumpRAddiuStackMM16 :
163 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
164 [], IIBranch, FrmR> {
165 let isTerminator = 1;
167 let hasDelaySlot = 1;
169 let isIndirectBranch = 1;
172 // 16-bit Jump and Link (Call) - Short Delay Slot
173 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
174 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
175 [], IIBranch, FrmR> {
177 let hasDelaySlot = 1;
181 // 16-bit Jump Register Compact - No delay slot
182 class JumpRegCMM16<string opstr, RegisterOperand RO> :
183 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
184 [], IIBranch, FrmR> {
185 let isTerminator = 1;
188 let isIndirectBranch = 1;
191 // MicroMIPS Jump and Link (Call) - Short Delay Slot
192 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
193 class JumpLinkMM<string opstr, DAGOperand opnd> :
194 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
195 [], IIBranch, FrmJ, opstr> {
196 let DecoderMethod = "DecodeJumpTargetMM";
199 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
200 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
203 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
204 RegisterOperand RO> :
205 InstSE<(outs), (ins RO:$rs, opnd:$offset),
206 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
209 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
211 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
213 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
215 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
217 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
219 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
220 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
221 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
222 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
223 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
224 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
225 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
226 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
227 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
228 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
229 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
231 class WaitMM<string opstr> :
232 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
233 NoItinerary, FrmOther, opstr>;
235 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
236 /// Compact Branch Instructions
237 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
238 COMPACT_BRANCH_FM_MM<0x7>;
239 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
240 COMPACT_BRANCH_FM_MM<0x5>;
242 /// Arithmetic Instructions (ALU Immediate)
243 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
245 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
247 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
249 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
251 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
253 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
255 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
257 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
259 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
262 /// Arithmetic Instructions (3-Operand, R-Type)
263 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
264 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
265 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
266 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
267 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
268 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
269 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
271 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
273 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
275 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
277 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
278 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
280 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
282 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
284 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
287 /// Shift Instructions
288 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
290 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
292 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
294 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
296 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
298 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
300 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
302 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
305 /// Load and Store Instructions - aligned
306 let DecoderMethod = "DecodeMemMMImm16" in {
307 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
308 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
309 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
310 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
311 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
312 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
313 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
314 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
317 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
319 /// Load and Store Instructions - unaligned
320 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
322 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
324 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
326 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
330 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
331 NoItinerary>, ADD_FM_MM<0, 0x58>;
332 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
333 NoItinerary>, ADD_FM_MM<0, 0x18>;
334 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
335 CMov_F_I_FM_MM<0x25>;
336 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
339 /// Move to/from HI/LO
340 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
342 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
344 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
346 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
349 /// Multiply Add/Sub Instructions
350 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
351 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
352 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
353 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
356 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
358 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
361 /// Sign Ext In Register Instructions.
362 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
363 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
364 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
365 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
367 /// Word Swap Bytes Within Halfwords
368 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
371 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
373 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
376 /// Jump Instructions
377 let DecoderMethod = "DecodeJumpTargetMM" in {
378 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
380 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
382 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
383 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
385 /// Jump Instructions - Short Delay Slot
386 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
387 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
389 /// Branch Instructions
390 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
392 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
394 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
396 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
398 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
400 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
402 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
404 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
407 /// Branch Instructions - Short Delay Slot
408 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
409 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
410 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
411 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
413 /// Control Instructions
414 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
415 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
416 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
417 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
418 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
419 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
420 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
422 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
425 /// Trap Instructions
426 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
427 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
428 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
429 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
430 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
431 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
433 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
434 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
435 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
436 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
437 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
438 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
440 /// Load-linked, Store-conditional
441 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
442 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
444 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
445 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
446 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
447 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
450 //===----------------------------------------------------------------------===//
451 // MicroMips instruction aliases
452 //===----------------------------------------------------------------------===//
454 let Predicates = [InMicroMips] in {
455 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;