1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def uimm6_lsl2 : Operand<i32> {
17 let EncoderMethod = "getUImm6Lsl2Encoding";
18 let DecoderMethod = "DecodeUImm6Lsl2";
21 def simm9_addiusp : Operand<i32> {
22 let EncoderMethod = "getSImm9AddiuspValue";
23 let DecoderMethod = "DecodeSimm9SP";
26 def uimm3_shift : Operand<i32> {
27 let EncoderMethod = "getUImm3Mod8Encoding";
28 let DecoderMethod = "DecodePOOL16BEncodedField";
31 def simm3_lsa2 : Operand<i32> {
32 let EncoderMethod = "getSImm3Lsa2Value";
33 let DecoderMethod = "DecodeAddiur2Simm7";
36 def uimm4_andi : Operand<i32> {
37 let EncoderMethod = "getUImm4AndValue";
38 let DecoderMethod = "DecodeANDI16Imm";
41 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
43 Imm < 28 && Imm > 0);}]>;
45 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
47 def immZExtAndi16 : ImmLeaf<i32,
48 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
49 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
50 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
52 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
54 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
56 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
57 let Name = "MicroMipsMem";
58 let RenderMethod = "addMicroMipsMemOperands";
59 let ParserMethod = "parseMemOperand";
60 let PredicateMethod = "isMemWithGRPMM16Base";
63 class mem_mm_4_generic : Operand<i32> {
64 let PrintMethod = "printMemOperand";
65 let MIOperandInfo = (ops GPRMM16, simm4);
66 let OperandType = "OPERAND_MEMORY";
67 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
70 def mem_mm_4 : mem_mm_4_generic {
71 let EncoderMethod = "getMemEncodingMMImm4";
74 def mem_mm_4_lsl1 : mem_mm_4_generic {
75 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
78 def mem_mm_4_lsl2 : mem_mm_4_generic {
79 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
82 def MicroMipsMemSPAsmOperand : AsmOperandClass {
83 let Name = "MicroMipsMemSP";
84 let RenderMethod = "addMemOperands";
85 let ParserMethod = "parseMemOperand";
86 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
89 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
92 let OperandType = "OPERAND_MEMORY";
93 let ParserMatchClass = MicroMipsMemSPAsmOperand;
94 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
97 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
98 let PrintMethod = "printMemOperand";
99 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
100 let OperandType = "OPERAND_MEMORY";
101 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
104 def mem_mm_9 : Operand<i32> {
105 let PrintMethod = "printMemOperand";
106 let MIOperandInfo = (ops GPR32, simm9);
107 let EncoderMethod = "getMemEncodingMMImm9";
108 let ParserMatchClass = MipsMemAsmOperand;
109 let OperandType = "OPERAND_MEMORY";
112 def mem_mm_12 : Operand<i32> {
113 let PrintMethod = "printMemOperand";
114 let MIOperandInfo = (ops GPR32, simm12);
115 let EncoderMethod = "getMemEncodingMMImm12";
116 let ParserMatchClass = MipsMemAsmOperand;
117 let OperandType = "OPERAND_MEMORY";
120 def mem_mm_16 : Operand<i32> {
121 let PrintMethod = "printMemOperand";
122 let MIOperandInfo = (ops GPR32, simm16);
123 let EncoderMethod = "getMemEncodingMMImm16";
124 let ParserMatchClass = MipsMemAsmOperand;
125 let OperandType = "OPERAND_MEMORY";
128 def MipsMemUimm4AsmOperand : AsmOperandClass {
129 let Name = "MemOffsetUimm4";
130 let SuperClasses = [MipsMemAsmOperand];
131 let RenderMethod = "addMemOperands";
132 let ParserMethod = "parseMemOperand";
133 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
136 def mem_mm_4sp : Operand<i32> {
137 let PrintMethod = "printMemOperand";
138 let MIOperandInfo = (ops GPR32, uimm8);
139 let EncoderMethod = "getMemEncodingMMImm4sp";
140 let ParserMatchClass = MipsMemUimm4AsmOperand;
141 let OperandType = "OPERAND_MEMORY";
144 def jmptarget_mm : Operand<OtherVT> {
145 let EncoderMethod = "getJumpTargetOpValueMM";
148 def calltarget_mm : Operand<iPTR> {
149 let EncoderMethod = "getJumpTargetOpValueMM";
152 def brtarget7_mm : Operand<OtherVT> {
153 let EncoderMethod = "getBranchTarget7OpValueMM";
154 let OperandType = "OPERAND_PCREL";
155 let DecoderMethod = "DecodeBranchTarget7MM";
156 let ParserMatchClass = MipsJumpTargetAsmOperand;
159 def brtarget10_mm : Operand<OtherVT> {
160 let EncoderMethod = "getBranchTargetOpValueMMPC10";
161 let OperandType = "OPERAND_PCREL";
162 let DecoderMethod = "DecodeBranchTarget10MM";
163 let ParserMatchClass = MipsJumpTargetAsmOperand;
166 def brtarget_mm : Operand<OtherVT> {
167 let EncoderMethod = "getBranchTargetOpValueMM";
168 let OperandType = "OPERAND_PCREL";
169 let DecoderMethod = "DecodeBranchTargetMM";
170 let ParserMatchClass = MipsJumpTargetAsmOperand;
173 def simm23_lsl2 : Operand<i32> {
174 let EncoderMethod = "getSimm23Lsl2Encoding";
175 let DecoderMethod = "DecodeSimm23Lsl2";
178 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
179 RegisterOperand RO> :
180 InstSE<(outs), (ins RO:$rs, opnd:$offset),
181 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
183 let isTerminator = 1;
184 let hasDelaySlot = 0;
188 let canFoldAsLoad = 1 in
189 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
191 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
192 !strconcat(opstr, "\t$rt, $addr"),
193 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
195 let DecoderMethod = "DecodeMemMMImm12";
196 string Constraints = "$src = $rt";
199 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
201 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
202 !strconcat(opstr, "\t$rt, $addr"),
203 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
204 let DecoderMethod = "DecodeMemMMImm12";
207 /// A register pair used by movep instruction.
208 def MovePRegPairAsmOperand : AsmOperandClass {
209 let Name = "MovePRegPair";
210 let ParserMethod = "parseMovePRegPair";
211 let PredicateMethod = "isMovePRegPair";
214 def movep_regpair : Operand<i32> {
215 let EncoderMethod = "getMovePRegPairOpValue";
216 let ParserMatchClass = MovePRegPairAsmOperand;
217 let PrintMethod = "printRegisterList";
218 let DecoderMethod = "DecodeMovePRegPair";
219 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
222 class MovePMM16<string opstr, RegisterOperand RO> :
223 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
224 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
226 let isReMaterializable = 1;
229 /// A register pair used by load/store pair instructions.
230 def RegPairAsmOperand : AsmOperandClass {
231 let Name = "RegPair";
232 let ParserMethod = "parseRegisterPair";
235 def regpair : Operand<i32> {
236 let EncoderMethod = "getRegisterPairOpValue";
237 let ParserMatchClass = RegPairAsmOperand;
238 let PrintMethod = "printRegisterPair";
239 let DecoderMethod = "DecodeRegPairOperand";
240 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
243 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
244 ComplexPattern Addr = addr> :
245 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
246 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
247 let DecoderMethod = "DecodeMemMMImm12";
251 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
252 ComplexPattern Addr = addr> :
253 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
254 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
255 let DecoderMethod = "DecodeMemMMImm12";
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
261 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
262 let DecoderMethod = "DecodeMemMMImm12";
266 class LLEBaseMM<string opstr, RegisterOperand RO> :
267 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
268 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
269 let DecoderMethod = "DecodeMemMMImm9";
273 class SCBaseMM<string opstr, RegisterOperand RO> :
274 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
275 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
276 let DecoderMethod = "DecodeMemMMImm12";
278 let Constraints = "$rt = $dst";
281 class SCEBaseMM<string opstr, RegisterOperand RO> :
282 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
283 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
284 let DecoderMethod = "DecodeMemMMImm9";
286 let Constraints = "$rt = $dst";
289 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
290 InstrItinClass Itin = NoItinerary> :
291 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
292 !strconcat(opstr, "\t$rt, $addr"),
293 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
294 let DecoderMethod = "DecodeMemMMImm12";
295 let canFoldAsLoad = 1;
299 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
300 InstrItinClass Itin = NoItinerary,
301 SDPatternOperator OpNode = null_frag> :
302 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
303 !strconcat(opstr, "\t$rd, $rs, $rt"),
304 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
305 let isCommutable = isComm;
308 class AndImmMM16<string opstr, RegisterOperand RO,
309 InstrItinClass Itin = NoItinerary> :
310 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
311 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
313 class LogicRMM16<string opstr, RegisterOperand RO,
314 InstrItinClass Itin = NoItinerary,
315 SDPatternOperator OpNode = null_frag> :
316 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
317 !strconcat(opstr, "\t$rt, $rs"),
318 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
319 let isCommutable = 1;
320 let Constraints = "$rt = $dst";
323 class NotMM16<string opstr, RegisterOperand RO> :
324 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
325 !strconcat(opstr, "\t$rt, $rs"),
326 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
328 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
329 InstrItinClass Itin = NoItinerary> :
330 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
331 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
333 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
334 InstrItinClass Itin, Operand MemOpnd> :
335 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
336 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
337 let DecoderMethod = "DecodeMemMMImm4";
338 let canFoldAsLoad = 1;
342 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
343 SDPatternOperator OpNode, InstrItinClass Itin,
345 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
346 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
347 let DecoderMethod = "DecodeMemMMImm4";
351 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
353 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
354 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
355 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
356 let canFoldAsLoad = 1;
360 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
362 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
363 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
364 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
368 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
370 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
371 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
372 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
373 let canFoldAsLoad = 1;
377 class AddImmUR2<string opstr, RegisterOperand RO> :
378 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
379 !strconcat(opstr, "\t$rd, $rs, $imm"),
380 [], NoItinerary, FrmR> {
381 let isCommutable = 1;
384 class AddImmUS5<string opstr, RegisterOperand RO> :
385 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
386 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
387 let Constraints = "$rd = $dst";
390 class AddImmUR1SP<string opstr, RegisterOperand RO> :
391 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
392 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
394 class AddImmUSP<string opstr> :
395 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
396 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
398 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
399 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
400 [], II_MFHI_MFLO, FrmR> {
402 let hasSideEffects = 0;
405 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
406 InstrItinClass Itin = NoItinerary> :
407 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
408 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
409 let isCommutable = isComm;
410 let isReMaterializable = 1;
413 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
414 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
415 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
416 let isReMaterializable = 1;
419 // 16-bit Jump and Link (Call)
420 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
421 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
422 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
424 let hasDelaySlot = 1;
429 class JumpRegMM16<string opstr, RegisterOperand RO> :
430 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
432 let hasDelaySlot = 1;
434 let isIndirectBranch = 1;
437 // Base class for JRADDIUSP instruction.
438 class JumpRAddiuStackMM16 :
439 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
440 [], II_JRADDIUSP, FrmR> {
441 let isTerminator = 1;
444 let isIndirectBranch = 1;
447 // 16-bit Jump and Link (Call) - Short Delay Slot
448 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
449 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
450 [], II_JALRS, FrmR> {
452 let hasDelaySlot = 1;
456 // 16-bit Jump Register Compact - No delay slot
457 class JumpRegCMM16<string opstr, RegisterOperand RO> :
458 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
460 let isTerminator = 1;
463 let isIndirectBranch = 1;
466 // Break16 and Sdbbp16
467 class BrkSdbbp16MM<string opstr> :
468 MicroMipsInst16<(outs), (ins uimm4:$code_),
469 !strconcat(opstr, "\t$code_"),
470 [], NoItinerary, FrmOther>;
472 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
473 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
474 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
476 let isTerminator = 1;
477 let hasDelaySlot = 1;
481 // MicroMIPS Jump and Link (Call) - Short Delay Slot
482 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
483 class JumpLinkMM<string opstr, DAGOperand opnd> :
484 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
485 [], II_JALS, FrmJ, opstr> {
486 let DecoderMethod = "DecodeJumpTargetMM";
489 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
490 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
493 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
494 RegisterOperand RO> :
495 InstSE<(outs), (ins RO:$rs, opnd:$offset),
496 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
499 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
500 InstrItinClass Itin = NoItinerary,
501 SDPatternOperator OpNode = null_frag> :
502 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
503 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
505 class PrefetchIndexed<string opstr> :
506 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
507 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
509 class AddImmUPC<string opstr, RegisterOperand RO> :
510 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
511 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
513 /// A list of registers used by load/store multiple instructions.
514 def RegListAsmOperand : AsmOperandClass {
515 let Name = "RegList";
516 let ParserMethod = "parseRegisterList";
519 def reglist : Operand<i32> {
520 let EncoderMethod = "getRegisterListOpValue";
521 let ParserMatchClass = RegListAsmOperand;
522 let PrintMethod = "printRegisterList";
523 let DecoderMethod = "DecodeRegListOperand";
526 def RegList16AsmOperand : AsmOperandClass {
527 let Name = "RegList16";
528 let ParserMethod = "parseRegisterList";
529 let PredicateMethod = "isRegList16";
530 let RenderMethod = "addRegListOperands";
533 def reglist16 : Operand<i32> {
534 let EncoderMethod = "getRegisterListOpValue16";
535 let DecoderMethod = "DecodeRegListOperand16";
536 let PrintMethod = "printRegisterList";
537 let ParserMatchClass = RegList16AsmOperand;
540 class StoreMultMM<string opstr,
541 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
542 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
543 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
544 let DecoderMethod = "DecodeMemMMImm12";
548 class LoadMultMM<string opstr,
549 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
550 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
551 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
552 let DecoderMethod = "DecodeMemMMImm12";
556 class StoreMultMM16<string opstr,
557 InstrItinClass Itin = NoItinerary,
558 ComplexPattern Addr = addr> :
559 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
560 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
561 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
565 class LoadMultMM16<string opstr,
566 InstrItinClass Itin = NoItinerary,
567 ComplexPattern Addr = addr> :
568 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
569 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
570 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
574 class UncondBranchMM16<string opstr> :
575 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
576 !strconcat(opstr, "\t$offset"),
579 let isTerminator = 1;
581 let hasDelaySlot = 1;
582 let Predicates = [RelocPIC, InMicroMips];
586 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
587 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
588 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
589 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
590 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
591 ISA_MICROMIPS_NOT_32R6_64R6;
592 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
593 ISA_MICROMIPS_NOT_32R6_64R6;
594 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
595 ISA_MICROMIPS_NOT_32R6_64R6;
596 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
597 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
598 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
599 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
601 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
602 ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
603 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
604 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
605 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
606 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
607 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
608 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
609 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
610 LOAD_STORE_FM_MM16<0x1a>;
611 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
612 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
613 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
614 II_SH, mem_mm_4_lsl1>,
615 LOAD_STORE_FM_MM16<0x2a>;
616 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
617 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
618 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
619 LOAD_GP_FM_MM16<0x19>;
620 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
621 LOAD_STORE_SP_FM_MM16<0x12>;
622 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
623 LOAD_STORE_SP_FM_MM16<0x32>;
624 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
625 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
626 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
627 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
628 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
629 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
630 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
631 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
632 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
634 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
635 ISA_MICROMIPS32_NOT_MIPS32R6;
636 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
637 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
638 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
639 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
640 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
641 BEQNEZ_FM_MM16<0x23>;
642 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
643 BEQNEZ_FM_MM16<0x2b>;
644 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
645 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
646 ISA_MICROMIPS_NOT_32R6_64R6;
647 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
648 ISA_MICROMIPS_NOT_32R6_64R6;
650 let DecoderNamespace = "MicroMips" in {
651 /// Load and Store Instructions - multiple
652 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>,
653 ISA_MICROMIPS32_NOT_MIPS32R6;
654 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>,
655 ISA_MICROMIPS32_NOT_MIPS32R6;
658 class WaitMM<string opstr> :
659 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
660 NoItinerary, FrmOther, opstr>;
662 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
663 /// Compact Branch Instructions
664 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
665 COMPACT_BRANCH_FM_MM<0x7>;
666 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
667 COMPACT_BRANCH_FM_MM<0x5>;
669 /// Arithmetic Instructions (ALU Immediate)
670 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
672 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
674 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
676 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
678 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
680 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
682 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
684 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
686 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
689 /// Arithmetic Instructions (3-Operand, R-Type)
690 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
692 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
694 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
695 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
696 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
697 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
698 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
700 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
702 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
704 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
706 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
707 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
709 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
711 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
713 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
716 /// Arithmetic Instructions with PC and Immediate
717 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
719 /// Shift Instructions
720 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
722 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
724 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
726 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
728 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
730 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
732 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
734 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
737 /// Load and Store Instructions - aligned
738 let DecoderMethod = "DecodeMemMMImm16" in {
739 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
740 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
741 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
742 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
743 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
744 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
745 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
746 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
749 let DecoderMethod = "DecodeMemMMImm9" in {
750 def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
751 def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
752 def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
753 def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
754 def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
755 def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
756 def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
757 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
758 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
761 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
763 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
765 /// Load and Store Instructions - unaligned
766 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
768 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
770 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
772 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
774 let DecoderMethod = "DecodeMemMMImm9" in {
775 def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
776 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
777 def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
778 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
779 def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
780 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
781 def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
782 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
785 /// Load and Store Instructions - multiple
786 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
787 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
789 /// Load and Store Pair Instructions
790 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
791 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
793 /// Load and Store multiple pseudo Instructions
794 class LoadWordMultMM<string instr_asm > :
795 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
796 !strconcat(instr_asm, "\t$rt, $addr")> ;
798 class StoreWordMultMM<string instr_asm > :
799 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
800 !strconcat(instr_asm, "\t$rt, $addr")> ;
803 def SWM_MM : StoreWordMultMM<"swm">;
804 def LWM_MM : LoadWordMultMM<"lwm">;
807 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
808 NoItinerary>, ADD_FM_MM<0, 0x58>;
809 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
810 NoItinerary>, ADD_FM_MM<0, 0x18>;
811 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
812 CMov_F_I_FM_MM<0x25>;
813 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
816 /// Move to/from HI/LO
817 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
819 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
821 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
823 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
826 /// Multiply Add/Sub Instructions
827 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
828 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
829 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
830 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
833 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
835 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
838 /// Sign Ext In Register Instructions.
839 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
840 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
841 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
842 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
844 /// Word Swap Bytes Within Halfwords
845 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
846 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
847 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
848 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,
849 MipsExt>, EXT_FM_MM<0x2c>;
850 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
853 /// Jump Instructions
854 let DecoderMethod = "DecodeJumpTargetMM" in {
855 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
857 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
858 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
860 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
861 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
863 /// Jump Instructions - Short Delay Slot
864 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
865 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
867 /// Branch Instructions
868 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
870 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
872 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
874 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
876 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
878 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
880 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
882 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
885 /// Branch Instructions - Short Delay Slot
886 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
887 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
888 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
889 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
891 /// Control Instructions
892 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
893 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
894 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
895 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
896 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
897 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
898 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
900 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
903 /// Trap Instructions
904 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
905 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
906 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
907 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
908 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
909 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
911 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
912 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
913 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
914 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
915 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
916 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
918 /// Load-linked, Store-conditional
919 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
920 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
922 def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
923 def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
925 let DecoderMethod = "DecodeCacheOpMM" in {
926 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
927 CACHE_PREF_FM_MM<0x08, 0x6>;
928 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
929 CACHE_PREF_FM_MM<0x18, 0x2>;
932 let DecoderMethod = "DecodePrefeOpMM" in {
933 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
934 CACHE_PREFE_FM_MM<0x18, 0x2>;
935 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
936 CACHE_PREFE_FM_MM<0x18, 0x3>;
938 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
939 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
940 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
942 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
943 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
944 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
945 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
947 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
949 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
952 let DecoderNamespace = "MicroMips" in {
953 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
954 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
957 let Predicates = [InMicroMips] in {
959 //===----------------------------------------------------------------------===//
960 // MicroMips arbitrary patterns that map to one or more instructions
961 //===----------------------------------------------------------------------===//
963 def : MipsPat<(i32 immLi16:$imm),
964 (LI16_MM immLi16:$imm)>;
965 def : MipsPat<(i32 immSExt16:$imm),
966 (ADDiu_MM ZERO, immSExt16:$imm)>;
967 def : MipsPat<(i32 immZExt16:$imm),
968 (ORi_MM ZERO, immZExt16:$imm)>;
969 def : MipsPat<(not GPR32:$in),
970 (NOR_MM GPR32Opnd:$in, ZERO)>;
972 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
973 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
974 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
975 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
976 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
977 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
979 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
980 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
981 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
982 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
984 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
985 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
986 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
987 (SLL_MM GPR32:$src, immZExt5:$imm)>;
989 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
990 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
991 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
992 (SRL_MM GPR32:$src, immZExt5:$imm)>;
994 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
995 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
996 def : MipsPat<(store GPR32:$src, addr:$addr),
997 (SW_MM GPR32:$src, addr:$addr)>;
999 def : MipsPat<(load addrimm4lsl2:$addr),
1000 (LW16_MM addrimm4lsl2:$addr)>;
1001 def : MipsPat<(load addr:$addr),
1002 (LW_MM addr:$addr)>;
1004 //===----------------------------------------------------------------------===//
1005 // MicroMips instruction aliases
1006 //===----------------------------------------------------------------------===//
1008 class UncondBranchMMPseudo<string opstr> :
1009 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1010 !strconcat(opstr, "\t$offset")>;
1012 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1014 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
1015 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
1016 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
1019 let Predicates = [InMicroMips] in {
1020 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
1021 def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
1022 def : MipsInstAlias<"teq $rs, $rt",
1023 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1024 def : MipsInstAlias<"tge $rs, $rt",
1025 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1026 def : MipsInstAlias<"tgeu $rs, $rt",
1027 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1028 def : MipsInstAlias<"tlt $rs, $rt",
1029 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1030 def : MipsInstAlias<"tltu $rs, $rt",
1031 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1032 def : MipsInstAlias<"tne $rs, $rt",
1033 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;