1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
4 def simm7 : Operand<i32>;
6 def simm12 : Operand<i32> {
7 let DecoderMethod = "DecodeSimm12";
10 def uimm5_lsl2 : Operand<OtherVT> {
11 let EncoderMethod = "getUImm5Lsl2Encoding";
14 def uimm6_lsl2 : Operand<i32> {
15 let EncoderMethod = "getUImm6Lsl2Encoding";
18 def simm9_addiusp : Operand<i32> {
19 let EncoderMethod = "getSImm9AddiuspValue";
22 def uimm3_shift : Operand<i32> {
23 let EncoderMethod = "getUImm3Mod8Encoding";
26 def simm3_lsa2 : Operand<i32> {
27 let EncoderMethod = "getSImm3Lsa2Value";
30 def uimm4_andi : Operand<i32> {
31 let EncoderMethod = "getUImm4AndValue";
34 def immZExtAndi16 : ImmLeaf<i32,
35 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
36 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
37 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
39 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
41 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
43 def mem_mm_12 : Operand<i32> {
44 let PrintMethod = "printMemOperand";
45 let MIOperandInfo = (ops GPR32, simm12);
46 let EncoderMethod = "getMemEncodingMMImm12";
47 let ParserMatchClass = MipsMemAsmOperand;
48 let OperandType = "OPERAND_MEMORY";
51 def jmptarget_mm : Operand<OtherVT> {
52 let EncoderMethod = "getJumpTargetOpValueMM";
55 def calltarget_mm : Operand<iPTR> {
56 let EncoderMethod = "getJumpTargetOpValueMM";
59 def brtarget_mm : Operand<OtherVT> {
60 let EncoderMethod = "getBranchTargetOpValueMM";
61 let OperandType = "OPERAND_PCREL";
62 let DecoderMethod = "DecodeBranchTargetMM";
65 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
67 InstSE<(outs), (ins RO:$rs, opnd:$offset),
68 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
75 let canFoldAsLoad = 1 in
76 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
78 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
79 !strconcat(opstr, "\t$rt, $addr"),
80 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
82 let DecoderMethod = "DecodeMemMMImm12";
83 string Constraints = "$src = $rt";
86 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
88 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
89 !strconcat(opstr, "\t$rt, $addr"),
90 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
91 let DecoderMethod = "DecodeMemMMImm12";
94 class LLBaseMM<string opstr, RegisterOperand RO> :
95 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
96 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
97 let DecoderMethod = "DecodeMemMMImm12";
101 class SCBaseMM<string opstr, RegisterOperand RO> :
102 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
103 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
104 let DecoderMethod = "DecodeMemMMImm12";
106 let Constraints = "$rt = $dst";
109 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
110 InstrItinClass Itin = NoItinerary> :
111 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
112 !strconcat(opstr, "\t$rt, $addr"),
113 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
114 let DecoderMethod = "DecodeMemMMImm12";
115 let canFoldAsLoad = 1;
119 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
120 InstrItinClass Itin = NoItinerary,
121 SDPatternOperator OpNode = null_frag> :
122 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
123 !strconcat(opstr, "\t$rd, $rs, $rt"),
124 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
125 let isCommutable = isComm;
128 class AndImmMM16<string opstr, RegisterOperand RO,
129 InstrItinClass Itin = NoItinerary> :
130 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
131 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
133 class LogicRMM16<string opstr, RegisterOperand RO,
134 InstrItinClass Itin = NoItinerary,
135 SDPatternOperator OpNode = null_frag> :
136 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
137 !strconcat(opstr, "\t$rt, $rs"),
138 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
139 let isCommutable = 1;
140 let Constraints = "$rt = $dst";
143 class NotMM16<string opstr, RegisterOperand RO> :
144 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
145 !strconcat(opstr, "\t$rt, $rs"),
146 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
148 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
149 InstrItinClass Itin = NoItinerary> :
150 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
151 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
153 class AddImmUR2<string opstr, RegisterOperand RO> :
154 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
155 !strconcat(opstr, "\t$rd, $rs, $imm"),
156 [], NoItinerary, FrmR> {
157 let isCommutable = 1;
160 class AddImmUS5<string opstr, RegisterOperand RO> :
161 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
162 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
163 let Constraints = "$rd = $dst";
164 let isCommutable = 1;
167 class AddImmUR1SP<string opstr, RegisterOperand RO> :
168 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
169 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
171 class AddImmUSP<string opstr> :
172 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
173 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
175 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
176 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
177 [], II_MFHI_MFLO, FrmR> {
179 let hasSideEffects = 0;
182 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
183 InstrItinClass Itin = NoItinerary> :
184 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
185 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
186 let isCommutable = isComm;
187 let isReMaterializable = 1;
190 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
191 SDPatternOperator imm_type = null_frag> :
192 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
193 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
194 let isReMaterializable = 1;
197 // 16-bit Jump and Link (Call)
198 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
199 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
200 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
202 let hasDelaySlot = 1;
207 class JumpRegMM16<string opstr, RegisterOperand RO> :
208 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
209 [], IIBranch, FrmR> {
210 let hasDelaySlot = 1;
212 let isIndirectBranch = 1;
215 // Base class for JRADDIUSP instruction.
216 class JumpRAddiuStackMM16 :
217 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
218 [], IIBranch, FrmR> {
219 let isTerminator = 1;
221 let hasDelaySlot = 1;
223 let isIndirectBranch = 1;
226 // 16-bit Jump and Link (Call) - Short Delay Slot
227 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
228 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
229 [], IIBranch, FrmR> {
231 let hasDelaySlot = 1;
235 // 16-bit Jump Register Compact - No delay slot
236 class JumpRegCMM16<string opstr, RegisterOperand RO> :
237 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
238 [], IIBranch, FrmR> {
239 let isTerminator = 1;
242 let isIndirectBranch = 1;
245 // MicroMIPS Jump and Link (Call) - Short Delay Slot
246 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
247 class JumpLinkMM<string opstr, DAGOperand opnd> :
248 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
249 [], IIBranch, FrmJ, opstr> {
250 let DecoderMethod = "DecodeJumpTargetMM";
253 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
254 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
257 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
258 RegisterOperand RO> :
259 InstSE<(outs), (ins RO:$rs, opnd:$offset),
260 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
263 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
265 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
267 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
268 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
270 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
272 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
274 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
275 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
277 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
279 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
280 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
281 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
282 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
283 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
284 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
285 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
286 def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>,
287 LI_FM_MM16, IsAsCheapAsAMove;
288 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
289 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
290 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
291 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
292 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
294 class WaitMM<string opstr> :
295 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
296 NoItinerary, FrmOther, opstr>;
298 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
299 /// Compact Branch Instructions
300 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
301 COMPACT_BRANCH_FM_MM<0x7>;
302 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
303 COMPACT_BRANCH_FM_MM<0x5>;
305 /// Arithmetic Instructions (ALU Immediate)
306 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
308 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
310 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
312 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
314 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
316 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
318 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
320 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
322 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
325 /// Arithmetic Instructions (3-Operand, R-Type)
326 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
327 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
328 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
329 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
330 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
331 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
332 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
334 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
336 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
338 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
340 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
341 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
343 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
345 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
347 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
350 /// Shift Instructions
351 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
353 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
355 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
357 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
359 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
361 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
363 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
365 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
368 /// Load and Store Instructions - aligned
369 let DecoderMethod = "DecodeMemMMImm16" in {
370 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
371 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
372 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
373 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
374 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
375 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
376 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
377 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
380 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
382 /// Load and Store Instructions - unaligned
383 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
385 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
387 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
389 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
393 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
394 NoItinerary>, ADD_FM_MM<0, 0x58>;
395 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
396 NoItinerary>, ADD_FM_MM<0, 0x18>;
397 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
398 CMov_F_I_FM_MM<0x25>;
399 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
402 /// Move to/from HI/LO
403 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
405 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
407 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
409 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
412 /// Multiply Add/Sub Instructions
413 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
414 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
415 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
416 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
419 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
421 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
424 /// Sign Ext In Register Instructions.
425 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
426 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
427 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
428 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
430 /// Word Swap Bytes Within Halfwords
431 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
434 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
436 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
439 /// Jump Instructions
440 let DecoderMethod = "DecodeJumpTargetMM" in {
441 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
443 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
445 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
446 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
448 /// Jump Instructions - Short Delay Slot
449 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
450 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
452 /// Branch Instructions
453 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
455 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
457 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
459 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
461 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
463 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
465 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
467 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
470 /// Branch Instructions - Short Delay Slot
471 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
472 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
473 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
474 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
476 /// Control Instructions
477 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
478 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
479 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
480 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
481 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
482 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
483 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
485 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
488 /// Trap Instructions
489 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
490 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
491 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
492 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
493 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
494 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
496 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
497 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
498 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
499 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
500 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
501 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
503 /// Load-linked, Store-conditional
504 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
505 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
507 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
508 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
509 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
510 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
513 let Predicates = [InMicroMips] in {
515 //===----------------------------------------------------------------------===//
516 // MicroMips arbitrary patterns that map to one or more instructions
517 //===----------------------------------------------------------------------===//
519 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
520 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
521 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
522 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
524 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
525 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
526 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
527 (SLL_MM GPR32:$src, immZExt5:$imm)>;
529 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
530 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
531 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
532 (SRL_MM GPR32:$src, immZExt5:$imm)>;
534 //===----------------------------------------------------------------------===//
535 // MicroMips instruction aliases
536 //===----------------------------------------------------------------------===//
538 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;