1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def MipsUimm5Lsl2AsmOperand : AsmOperandClass {
17 let Name = "Uimm5Lsl2";
18 let RenderMethod = "addImmOperands";
19 let ParserMethod = "parseImm";
20 let PredicateMethod = "isUImm5Lsl2";
23 def uimm5_lsl2 : Operand<OtherVT> {
24 let EncoderMethod = "getUImm5Lsl2Encoding";
25 let DecoderMethod = "DecodeUImm5lsl2";
26 let ParserMatchClass = MipsUimm5Lsl2AsmOperand;
29 def uimm6_lsl2 : Operand<i32> {
30 let EncoderMethod = "getUImm6Lsl2Encoding";
31 let DecoderMethod = "DecodeUImm6Lsl2";
34 def simm9_addiusp : Operand<i32> {
35 let EncoderMethod = "getSImm9AddiuspValue";
36 let DecoderMethod = "DecodeSimm9SP";
39 def uimm3_shift : Operand<i32> {
40 let EncoderMethod = "getUImm3Mod8Encoding";
41 let DecoderMethod = "DecodePOOL16BEncodedField";
44 def simm3_lsa2 : Operand<i32> {
45 let EncoderMethod = "getSImm3Lsa2Value";
46 let DecoderMethod = "DecodeAddiur2Simm7";
49 def uimm4_andi : Operand<i32> {
50 let EncoderMethod = "getUImm4AndValue";
51 let DecoderMethod = "DecodeANDI16Imm";
54 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
56 Imm < 28 && Imm > 0);}]>;
58 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
60 def immZExtAndi16 : ImmLeaf<i32,
61 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
62 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
63 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
65 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
67 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
69 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
70 let Name = "MicroMipsMem";
71 let RenderMethod = "addMicroMipsMemOperands";
72 let ParserMethod = "parseMemOperand";
73 let PredicateMethod = "isMemWithGRPMM16Base";
76 class mem_mm_4_generic : Operand<i32> {
77 let PrintMethod = "printMemOperand";
78 let MIOperandInfo = (ops GPRMM16, simm4);
79 let OperandType = "OPERAND_MEMORY";
80 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
83 def mem_mm_4 : mem_mm_4_generic {
84 let EncoderMethod = "getMemEncodingMMImm4";
87 def mem_mm_4_lsl1 : mem_mm_4_generic {
88 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
91 def mem_mm_4_lsl2 : mem_mm_4_generic {
92 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
95 def MicroMipsMemSPAsmOperand : AsmOperandClass {
96 let Name = "MicroMipsMemSP";
97 let RenderMethod = "addMemOperands";
98 let ParserMethod = "parseMemOperand";
99 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
102 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
103 let PrintMethod = "printMemOperand";
104 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
105 let OperandType = "OPERAND_MEMORY";
106 let ParserMatchClass = MicroMipsMemSPAsmOperand;
107 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
110 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
111 let PrintMethod = "printMemOperand";
112 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
113 let OperandType = "OPERAND_MEMORY";
114 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
117 def mem_mm_9 : Operand<i32> {
118 let PrintMethod = "printMemOperand";
119 let MIOperandInfo = (ops GPR32, simm9);
120 let EncoderMethod = "getMemEncodingMMImm9";
121 let ParserMatchClass = MipsMemAsmOperand;
122 let OperandType = "OPERAND_MEMORY";
125 def mem_mm_12 : Operand<i32> {
126 let PrintMethod = "printMemOperand";
127 let MIOperandInfo = (ops GPR32, simm12);
128 let EncoderMethod = "getMemEncodingMMImm12";
129 let ParserMatchClass = MipsMemAsmOperand;
130 let OperandType = "OPERAND_MEMORY";
133 def MipsMemUimm4AsmOperand : AsmOperandClass {
134 let Name = "MemOffsetUimm4";
135 let SuperClasses = [MipsMemAsmOperand];
136 let RenderMethod = "addMemOperands";
137 let ParserMethod = "parseMemOperand";
138 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
141 def mem_mm_4sp : Operand<i32> {
142 let PrintMethod = "printMemOperand";
143 let MIOperandInfo = (ops GPR32, uimm8);
144 let EncoderMethod = "getMemEncodingMMImm4sp";
145 let ParserMatchClass = MipsMemUimm4AsmOperand;
146 let OperandType = "OPERAND_MEMORY";
149 def jmptarget_mm : Operand<OtherVT> {
150 let EncoderMethod = "getJumpTargetOpValueMM";
153 def calltarget_mm : Operand<iPTR> {
154 let EncoderMethod = "getJumpTargetOpValueMM";
157 def brtarget7_mm : Operand<OtherVT> {
158 let EncoderMethod = "getBranchTarget7OpValueMM";
159 let OperandType = "OPERAND_PCREL";
160 let DecoderMethod = "DecodeBranchTarget7MM";
161 let ParserMatchClass = MipsJumpTargetAsmOperand;
164 def brtarget10_mm : Operand<OtherVT> {
165 let EncoderMethod = "getBranchTargetOpValueMMPC10";
166 let OperandType = "OPERAND_PCREL";
167 let DecoderMethod = "DecodeBranchTarget10MM";
168 let ParserMatchClass = MipsJumpTargetAsmOperand;
171 def brtarget_mm : Operand<OtherVT> {
172 let EncoderMethod = "getBranchTargetOpValueMM";
173 let OperandType = "OPERAND_PCREL";
174 let DecoderMethod = "DecodeBranchTargetMM";
175 let ParserMatchClass = MipsJumpTargetAsmOperand;
178 def simm23_lsl2 : Operand<i32> {
179 let EncoderMethod = "getSimm23Lsl2Encoding";
180 let DecoderMethod = "DecodeSimm23Lsl2";
183 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
184 RegisterOperand RO> :
185 InstSE<(outs), (ins RO:$rs, opnd:$offset),
186 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
188 let isTerminator = 1;
189 let hasDelaySlot = 0;
193 let canFoldAsLoad = 1 in
194 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
196 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
197 !strconcat(opstr, "\t$rt, $addr"),
198 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
200 let DecoderMethod = "DecodeMemMMImm12";
201 string Constraints = "$src = $rt";
204 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
206 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
207 !strconcat(opstr, "\t$rt, $addr"),
208 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
209 let DecoderMethod = "DecodeMemMMImm12";
212 /// A register pair used by movep instruction.
213 def MovePRegPairAsmOperand : AsmOperandClass {
214 let Name = "MovePRegPair";
215 let ParserMethod = "parseMovePRegPair";
216 let PredicateMethod = "isMovePRegPair";
219 def movep_regpair : Operand<i32> {
220 let EncoderMethod = "getMovePRegPairOpValue";
221 let ParserMatchClass = MovePRegPairAsmOperand;
222 let PrintMethod = "printRegisterList";
223 let DecoderMethod = "DecodeMovePRegPair";
224 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
227 class MovePMM16<string opstr, RegisterOperand RO> :
228 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
229 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
231 let isReMaterializable = 1;
234 /// A register pair used by load/store pair instructions.
235 def RegPairAsmOperand : AsmOperandClass {
236 let Name = "RegPair";
237 let ParserMethod = "parseRegisterPair";
240 def regpair : Operand<i32> {
241 let EncoderMethod = "getRegisterPairOpValue";
242 let ParserMatchClass = RegPairAsmOperand;
243 let PrintMethod = "printRegisterPair";
244 let DecoderMethod = "DecodeRegPairOperand";
245 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
248 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
249 ComplexPattern Addr = addr> :
250 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
251 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
252 let DecoderMethod = "DecodeMemMMImm12";
256 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
257 ComplexPattern Addr = addr> :
258 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
259 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
260 let DecoderMethod = "DecodeMemMMImm12";
264 class LLBaseMM<string opstr, RegisterOperand RO> :
265 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
266 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
267 let DecoderMethod = "DecodeMemMMImm12";
271 class LLEBaseMM<string opstr, RegisterOperand RO> :
272 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
273 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
274 let DecoderMethod = "DecodeMemMMImm9";
278 class SCBaseMM<string opstr, RegisterOperand RO> :
279 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
280 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
281 let DecoderMethod = "DecodeMemMMImm12";
283 let Constraints = "$rt = $dst";
286 class SCEBaseMM<string opstr, RegisterOperand RO> :
287 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
288 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
289 let DecoderMethod = "DecodeMemMMImm9";
291 let Constraints = "$rt = $dst";
294 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
295 InstrItinClass Itin = NoItinerary> :
296 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
297 !strconcat(opstr, "\t$rt, $addr"),
298 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
299 let DecoderMethod = "DecodeMemMMImm12";
300 let canFoldAsLoad = 1;
304 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
305 InstrItinClass Itin = NoItinerary,
306 SDPatternOperator OpNode = null_frag> :
307 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
308 !strconcat(opstr, "\t$rd, $rs, $rt"),
309 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
310 let isCommutable = isComm;
313 class AndImmMM16<string opstr, RegisterOperand RO,
314 InstrItinClass Itin = NoItinerary> :
315 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
316 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
318 class LogicRMM16<string opstr, RegisterOperand RO,
319 InstrItinClass Itin = NoItinerary,
320 SDPatternOperator OpNode = null_frag> :
321 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
322 !strconcat(opstr, "\t$rt, $rs"),
323 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
324 let isCommutable = 1;
325 let Constraints = "$rt = $dst";
328 class NotMM16<string opstr, RegisterOperand RO> :
329 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
330 !strconcat(opstr, "\t$rt, $rs"),
331 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
333 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
334 InstrItinClass Itin = NoItinerary> :
335 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
336 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
338 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
339 InstrItinClass Itin, Operand MemOpnd> :
340 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
341 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
342 let DecoderMethod = "DecodeMemMMImm4";
343 let canFoldAsLoad = 1;
347 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
348 SDPatternOperator OpNode, InstrItinClass Itin,
350 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
351 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
352 let DecoderMethod = "DecodeMemMMImm4";
356 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
358 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
359 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
360 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
361 let canFoldAsLoad = 1;
365 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
367 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
368 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
369 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
373 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
375 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
376 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
377 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
378 let canFoldAsLoad = 1;
382 class AddImmUR2<string opstr, RegisterOperand RO> :
383 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
384 !strconcat(opstr, "\t$rd, $rs, $imm"),
385 [], NoItinerary, FrmR> {
386 let isCommutable = 1;
389 class AddImmUS5<string opstr, RegisterOperand RO> :
390 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
391 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
392 let Constraints = "$rd = $dst";
395 class AddImmUR1SP<string opstr, RegisterOperand RO> :
396 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
397 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
399 class AddImmUSP<string opstr> :
400 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
401 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
403 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
404 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
405 [], II_MFHI_MFLO, FrmR> {
407 let hasSideEffects = 0;
410 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
411 InstrItinClass Itin = NoItinerary> :
412 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
413 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
414 let isCommutable = isComm;
415 let isReMaterializable = 1;
418 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
419 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
420 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
421 let isReMaterializable = 1;
424 // 16-bit Jump and Link (Call)
425 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
426 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
427 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
429 let hasDelaySlot = 1;
434 class JumpRegMM16<string opstr, RegisterOperand RO> :
435 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
437 let hasDelaySlot = 1;
439 let isIndirectBranch = 1;
442 // Base class for JRADDIUSP instruction.
443 class JumpRAddiuStackMM16 :
444 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
445 [], II_JRADDIUSP, FrmR> {
446 let isTerminator = 1;
449 let isIndirectBranch = 1;
452 // 16-bit Jump and Link (Call) - Short Delay Slot
453 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
454 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
455 [], II_JALRS, FrmR> {
457 let hasDelaySlot = 1;
461 // 16-bit Jump Register Compact - No delay slot
462 class JumpRegCMM16<string opstr, RegisterOperand RO> :
463 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
465 let isTerminator = 1;
468 let isIndirectBranch = 1;
471 // Break16 and Sdbbp16
472 class BrkSdbbp16MM<string opstr> :
473 MicroMipsInst16<(outs), (ins uimm4:$code_),
474 !strconcat(opstr, "\t$code_"),
475 [], NoItinerary, FrmOther>;
477 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
478 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
479 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
481 let isTerminator = 1;
482 let hasDelaySlot = 1;
486 // MicroMIPS Jump and Link (Call) - Short Delay Slot
487 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
488 class JumpLinkMM<string opstr, DAGOperand opnd> :
489 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
490 [], II_JALS, FrmJ, opstr> {
491 let DecoderMethod = "DecodeJumpTargetMM";
494 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
495 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
498 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
499 RegisterOperand RO> :
500 InstSE<(outs), (ins RO:$rs, opnd:$offset),
501 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
504 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
505 InstrItinClass Itin = NoItinerary,
506 SDPatternOperator OpNode = null_frag> :
507 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
508 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
510 class PrefetchIndexed<string opstr> :
511 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
512 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
514 class AddImmUPC<string opstr, RegisterOperand RO> :
515 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
516 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
518 /// A list of registers used by load/store multiple instructions.
519 def RegListAsmOperand : AsmOperandClass {
520 let Name = "RegList";
521 let ParserMethod = "parseRegisterList";
524 def reglist : Operand<i32> {
525 let EncoderMethod = "getRegisterListOpValue";
526 let ParserMatchClass = RegListAsmOperand;
527 let PrintMethod = "printRegisterList";
528 let DecoderMethod = "DecodeRegListOperand";
531 def RegList16AsmOperand : AsmOperandClass {
532 let Name = "RegList16";
533 let ParserMethod = "parseRegisterList";
534 let PredicateMethod = "isRegList16";
535 let RenderMethod = "addRegListOperands";
538 def reglist16 : Operand<i32> {
539 let EncoderMethod = "getRegisterListOpValue16";
540 let DecoderMethod = "DecodeRegListOperand16";
541 let PrintMethod = "printRegisterList";
542 let ParserMatchClass = RegList16AsmOperand;
545 class StoreMultMM<string opstr,
546 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
547 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
548 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
549 let DecoderMethod = "DecodeMemMMImm12";
553 class LoadMultMM<string opstr,
554 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
555 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
556 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
557 let DecoderMethod = "DecodeMemMMImm12";
561 class StoreMultMM16<string opstr,
562 InstrItinClass Itin = NoItinerary,
563 ComplexPattern Addr = addr> :
564 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
565 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
566 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
570 class LoadMultMM16<string opstr,
571 InstrItinClass Itin = NoItinerary,
572 ComplexPattern Addr = addr> :
573 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
574 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
575 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
579 class UncondBranchMM16<string opstr> :
580 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
581 !strconcat(opstr, "\t$offset"),
584 let isTerminator = 1;
586 let hasDelaySlot = 1;
587 let Predicates = [RelocPIC, InMicroMips];
591 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
592 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
593 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
594 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
595 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
596 ISA_MICROMIPS_NOT_32R6_64R6;
597 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
598 ISA_MICROMIPS_NOT_32R6_64R6;
599 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
600 ISA_MICROMIPS_NOT_32R6_64R6;
601 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
602 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
603 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
604 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
606 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
607 ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
608 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
609 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
610 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
611 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
612 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
613 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
614 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
615 LOAD_STORE_FM_MM16<0x1a>;
616 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
617 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
618 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
619 II_SH, mem_mm_4_lsl1>,
620 LOAD_STORE_FM_MM16<0x2a>;
621 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
622 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
623 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
624 LOAD_GP_FM_MM16<0x19>;
625 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
626 LOAD_STORE_SP_FM_MM16<0x12>;
627 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
628 LOAD_STORE_SP_FM_MM16<0x32>;
629 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
630 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
631 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
632 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
633 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
634 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
635 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
636 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
637 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
639 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
640 ISA_MICROMIPS32_NOT_MIPS32R6;
641 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
642 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
643 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
644 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
645 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
646 BEQNEZ_FM_MM16<0x23>;
647 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
648 BEQNEZ_FM_MM16<0x2b>;
649 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
650 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
651 ISA_MICROMIPS_NOT_32R6_64R6;
652 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
653 ISA_MICROMIPS_NOT_32R6_64R6;
655 class WaitMM<string opstr> :
656 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
657 NoItinerary, FrmOther, opstr>;
659 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
660 /// Compact Branch Instructions
661 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
662 COMPACT_BRANCH_FM_MM<0x7>;
663 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
664 COMPACT_BRANCH_FM_MM<0x5>;
666 /// Arithmetic Instructions (ALU Immediate)
667 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
669 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
671 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
673 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
675 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
677 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
679 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
681 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
683 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
686 /// Arithmetic Instructions (3-Operand, R-Type)
687 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
689 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
691 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
692 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
693 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
694 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
695 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
697 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
699 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
701 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
703 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
704 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
706 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
708 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
710 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
713 /// Arithmetic Instructions with PC and Immediate
714 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
716 /// Shift Instructions
717 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
719 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
721 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
723 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
725 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
727 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
729 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
731 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
734 /// Load and Store Instructions - aligned
735 let DecoderMethod = "DecodeMemMMImm16" in {
736 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
737 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
738 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
739 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
740 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
741 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
742 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
743 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
746 let DecoderMethod = "DecodeMemMMImm9" in {
747 def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
748 def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
749 def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
750 def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
751 def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
752 def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
753 def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
754 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
755 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
758 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
760 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
762 /// Load and Store Instructions - unaligned
763 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
765 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
767 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
769 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
771 let DecoderMethod = "DecodeMemMMImm9" in {
772 def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
773 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
774 def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
775 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
776 def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
777 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
778 def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
779 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
782 /// Load and Store Instructions - multiple
783 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
784 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
785 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
786 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
788 /// Load and Store Pair Instructions
789 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
790 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
792 /// Load and Store multiple pseudo Instructions
793 class LoadWordMultMM<string instr_asm > :
794 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
795 !strconcat(instr_asm, "\t$rt, $addr")> ;
797 class StoreWordMultMM<string instr_asm > :
798 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
799 !strconcat(instr_asm, "\t$rt, $addr")> ;
802 def SWM_MM : StoreWordMultMM<"swm">;
803 def LWM_MM : LoadWordMultMM<"lwm">;
806 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
807 NoItinerary>, ADD_FM_MM<0, 0x58>;
808 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
809 NoItinerary>, ADD_FM_MM<0, 0x18>;
810 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
811 CMov_F_I_FM_MM<0x25>;
812 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
815 /// Move to/from HI/LO
816 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
818 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
820 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
822 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
825 /// Multiply Add/Sub Instructions
826 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
827 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
828 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
829 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
832 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
834 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
837 /// Sign Ext In Register Instructions.
838 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
839 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
840 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
841 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
843 /// Word Swap Bytes Within Halfwords
844 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
845 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
847 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
849 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
852 /// Jump Instructions
853 let DecoderMethod = "DecodeJumpTargetMM" in {
854 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
856 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
857 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
859 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
860 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
862 /// Jump Instructions - Short Delay Slot
863 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
864 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
866 /// Branch Instructions
867 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
869 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
871 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
873 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
875 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
877 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
879 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
881 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
884 /// Branch Instructions - Short Delay Slot
885 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
886 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
887 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
888 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
890 /// Control Instructions
891 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
892 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
893 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
894 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
895 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
896 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
897 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
899 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
902 /// Trap Instructions
903 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
904 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
905 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
906 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
907 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
908 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
910 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
911 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
912 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
913 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
914 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
915 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
917 /// Load-linked, Store-conditional
918 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
919 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
921 def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
922 def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
924 let DecoderMethod = "DecodeCacheOpMM" in {
925 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
926 CACHE_PREF_FM_MM<0x08, 0x6>;
927 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
928 CACHE_PREF_FM_MM<0x18, 0x2>;
931 let DecoderMethod = "DecodePrefeOpMM" in {
932 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
933 CACHE_PREFE_FM_MM<0x18, 0x2>;
934 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
935 CACHE_PREFE_FM_MM<0x18, 0x3>;
937 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
938 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
939 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
941 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
942 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
943 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
944 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
946 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
947 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
949 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
952 let Predicates = [InMicroMips] in {
954 //===----------------------------------------------------------------------===//
955 // MicroMips arbitrary patterns that map to one or more instructions
956 //===----------------------------------------------------------------------===//
958 def : MipsPat<(i32 immLi16:$imm),
959 (LI16_MM immLi16:$imm)>;
960 def : MipsPat<(i32 immSExt16:$imm),
961 (ADDiu_MM ZERO, immSExt16:$imm)>;
962 def : MipsPat<(i32 immZExt16:$imm),
963 (ORi_MM ZERO, immZExt16:$imm)>;
964 def : MipsPat<(not GPR32:$in),
965 (NOR_MM GPR32Opnd:$in, ZERO)>;
967 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
968 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
969 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
970 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
971 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
972 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
974 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
975 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
976 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
977 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
979 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
980 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
981 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
982 (SLL_MM GPR32:$src, immZExt5:$imm)>;
984 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
985 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
986 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
987 (SRL_MM GPR32:$src, immZExt5:$imm)>;
989 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
990 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
991 def : MipsPat<(store GPR32:$src, addr:$addr),
992 (SW_MM GPR32:$src, addr:$addr)>;
994 def : MipsPat<(load addrimm4lsl2:$addr),
995 (LW16_MM addrimm4lsl2:$addr)>;
996 def : MipsPat<(load addr:$addr),
999 //===----------------------------------------------------------------------===//
1000 // MicroMips instruction aliases
1001 //===----------------------------------------------------------------------===//
1003 class UncondBranchMMPseudo<string opstr> :
1004 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1005 !strconcat(opstr, "\t$offset")>;
1007 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1009 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
1010 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
1011 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
1014 let Predicates = [InMicroMips] in {
1015 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
1016 def : MipsInstAlias<"teq $rs, $rt",
1017 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1018 def : MipsInstAlias<"tge $rs, $rt",
1019 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1020 def : MipsInstAlias<"tgeu $rs, $rt",
1021 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1022 def : MipsInstAlias<"tlt $rs, $rt",
1023 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1024 def : MipsInstAlias<"tltu $rs, $rt",
1025 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1026 def : MipsInstAlias<"tne $rs, $rt",
1027 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;