1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def uimm5_lsl2 : Operand<OtherVT> {
17 let EncoderMethod = "getUImm5Lsl2Encoding";
18 let DecoderMethod = "DecodeUImm5lsl2";
21 def uimm6_lsl2 : Operand<i32> {
22 let EncoderMethod = "getUImm6Lsl2Encoding";
23 let DecoderMethod = "DecodeUImm6Lsl2";
26 def simm9_addiusp : Operand<i32> {
27 let EncoderMethod = "getSImm9AddiuspValue";
28 let DecoderMethod = "DecodeSimm9SP";
31 def uimm3_shift : Operand<i32> {
32 let EncoderMethod = "getUImm3Mod8Encoding";
33 let DecoderMethod = "DecodePOOL16BEncodedField";
36 def simm3_lsa2 : Operand<i32> {
37 let EncoderMethod = "getSImm3Lsa2Value";
38 let DecoderMethod = "DecodeAddiur2Simm7";
41 def uimm4_andi : Operand<i32> {
42 let EncoderMethod = "getUImm4AndValue";
43 let DecoderMethod = "DecodeANDI16Imm";
46 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
48 Imm < 28 && Imm > 0);}]>;
50 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
52 def immZExtAndi16 : ImmLeaf<i32,
53 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
54 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
55 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
57 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
59 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
61 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
62 let Name = "MicroMipsMem";
63 let RenderMethod = "addMicroMipsMemOperands";
64 let ParserMethod = "parseMemOperand";
65 let PredicateMethod = "isMemWithGRPMM16Base";
68 class mem_mm_4_generic : Operand<i32> {
69 let PrintMethod = "printMemOperand";
70 let MIOperandInfo = (ops GPRMM16, simm4);
71 let OperandType = "OPERAND_MEMORY";
72 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
75 def mem_mm_4 : mem_mm_4_generic {
76 let EncoderMethod = "getMemEncodingMMImm4";
79 def mem_mm_4_lsl1 : mem_mm_4_generic {
80 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
83 def mem_mm_4_lsl2 : mem_mm_4_generic {
84 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
87 def MicroMipsMemSPAsmOperand : AsmOperandClass {
88 let Name = "MicroMipsMemSP";
89 let RenderMethod = "addMemOperands";
90 let ParserMethod = "parseMemOperand";
91 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
94 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
97 let OperandType = "OPERAND_MEMORY";
98 let ParserMatchClass = MicroMipsMemSPAsmOperand;
99 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
102 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
103 let PrintMethod = "printMemOperand";
104 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
105 let OperandType = "OPERAND_MEMORY";
106 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
109 def mem_mm_9 : Operand<i32> {
110 let PrintMethod = "printMemOperand";
111 let MIOperandInfo = (ops GPR32, simm9);
112 let EncoderMethod = "getMemEncodingMMImm9";
113 let ParserMatchClass = MipsMemAsmOperand;
114 let OperandType = "OPERAND_MEMORY";
117 def mem_mm_12 : Operand<i32> {
118 let PrintMethod = "printMemOperand";
119 let MIOperandInfo = (ops GPR32, simm12);
120 let EncoderMethod = "getMemEncodingMMImm12";
121 let ParserMatchClass = MipsMemAsmOperand;
122 let OperandType = "OPERAND_MEMORY";
125 def MipsMemUimm4AsmOperand : AsmOperandClass {
126 let Name = "MemOffsetUimm4";
127 let SuperClasses = [MipsMemAsmOperand];
128 let RenderMethod = "addMemOperands";
129 let ParserMethod = "parseMemOperand";
130 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
133 def mem_mm_4sp : Operand<i32> {
134 let PrintMethod = "printMemOperand";
135 let MIOperandInfo = (ops GPR32, uimm8);
136 let EncoderMethod = "getMemEncodingMMImm4sp";
137 let ParserMatchClass = MipsMemUimm4AsmOperand;
138 let OperandType = "OPERAND_MEMORY";
141 def jmptarget_mm : Operand<OtherVT> {
142 let EncoderMethod = "getJumpTargetOpValueMM";
145 def calltarget_mm : Operand<iPTR> {
146 let EncoderMethod = "getJumpTargetOpValueMM";
149 def brtarget7_mm : Operand<OtherVT> {
150 let EncoderMethod = "getBranchTarget7OpValueMM";
151 let OperandType = "OPERAND_PCREL";
152 let DecoderMethod = "DecodeBranchTarget7MM";
153 let ParserMatchClass = MipsJumpTargetAsmOperand;
156 def brtarget10_mm : Operand<OtherVT> {
157 let EncoderMethod = "getBranchTargetOpValueMMPC10";
158 let OperandType = "OPERAND_PCREL";
159 let DecoderMethod = "DecodeBranchTarget10MM";
160 let ParserMatchClass = MipsJumpTargetAsmOperand;
163 def brtarget_mm : Operand<OtherVT> {
164 let EncoderMethod = "getBranchTargetOpValueMM";
165 let OperandType = "OPERAND_PCREL";
166 let DecoderMethod = "DecodeBranchTargetMM";
167 let ParserMatchClass = MipsJumpTargetAsmOperand;
170 def simm23_lsl2 : Operand<i32> {
171 let EncoderMethod = "getSimm23Lsl2Encoding";
172 let DecoderMethod = "DecodeSimm23Lsl2";
175 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
176 RegisterOperand RO> :
177 InstSE<(outs), (ins RO:$rs, opnd:$offset),
178 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
180 let isTerminator = 1;
181 let hasDelaySlot = 0;
185 let canFoldAsLoad = 1 in
186 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
188 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
189 !strconcat(opstr, "\t$rt, $addr"),
190 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
192 let DecoderMethod = "DecodeMemMMImm12";
193 string Constraints = "$src = $rt";
196 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
198 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
199 !strconcat(opstr, "\t$rt, $addr"),
200 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
201 let DecoderMethod = "DecodeMemMMImm12";
204 /// A register pair used by movep instruction.
205 def MovePRegPairAsmOperand : AsmOperandClass {
206 let Name = "MovePRegPair";
207 let ParserMethod = "parseMovePRegPair";
208 let PredicateMethod = "isMovePRegPair";
211 def movep_regpair : Operand<i32> {
212 let EncoderMethod = "getMovePRegPairOpValue";
213 let ParserMatchClass = MovePRegPairAsmOperand;
214 let PrintMethod = "printRegisterList";
215 let DecoderMethod = "DecodeMovePRegPair";
216 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
219 class MovePMM16<string opstr, RegisterOperand RO> :
220 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
221 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
223 let isReMaterializable = 1;
226 /// A register pair used by load/store pair instructions.
227 def RegPairAsmOperand : AsmOperandClass {
228 let Name = "RegPair";
229 let ParserMethod = "parseRegisterPair";
232 def regpair : Operand<i32> {
233 let EncoderMethod = "getRegisterPairOpValue";
234 let ParserMatchClass = RegPairAsmOperand;
235 let PrintMethod = "printRegisterPair";
236 let DecoderMethod = "DecodeRegPairOperand";
237 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
240 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
241 ComplexPattern Addr = addr> :
242 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
243 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
244 let DecoderMethod = "DecodeMemMMImm12";
248 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
249 ComplexPattern Addr = addr> :
250 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
251 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
252 let DecoderMethod = "DecodeMemMMImm12";
256 class LLBaseMM<string opstr, RegisterOperand RO> :
257 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
258 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
259 let DecoderMethod = "DecodeMemMMImm12";
263 class SCBaseMM<string opstr, RegisterOperand RO> :
264 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
265 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
266 let DecoderMethod = "DecodeMemMMImm12";
268 let Constraints = "$rt = $dst";
271 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
272 InstrItinClass Itin = NoItinerary> :
273 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
274 !strconcat(opstr, "\t$rt, $addr"),
275 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
276 let DecoderMethod = "DecodeMemMMImm12";
277 let canFoldAsLoad = 1;
281 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
282 InstrItinClass Itin = NoItinerary,
283 SDPatternOperator OpNode = null_frag> :
284 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
285 !strconcat(opstr, "\t$rd, $rs, $rt"),
286 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
287 let isCommutable = isComm;
290 class AndImmMM16<string opstr, RegisterOperand RO,
291 InstrItinClass Itin = NoItinerary> :
292 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
293 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
295 class LogicRMM16<string opstr, RegisterOperand RO,
296 InstrItinClass Itin = NoItinerary,
297 SDPatternOperator OpNode = null_frag> :
298 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
299 !strconcat(opstr, "\t$rt, $rs"),
300 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
301 let isCommutable = 1;
302 let Constraints = "$rt = $dst";
305 class NotMM16<string opstr, RegisterOperand RO> :
306 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
307 !strconcat(opstr, "\t$rt, $rs"),
308 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
310 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
311 InstrItinClass Itin = NoItinerary> :
312 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
313 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
315 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
316 InstrItinClass Itin, Operand MemOpnd> :
317 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
318 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
319 let DecoderMethod = "DecodeMemMMImm4";
320 let canFoldAsLoad = 1;
324 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
325 SDPatternOperator OpNode, InstrItinClass Itin,
327 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
328 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
329 let DecoderMethod = "DecodeMemMMImm4";
333 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
335 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
336 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
337 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
338 let canFoldAsLoad = 1;
342 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
344 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
345 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
346 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
350 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
352 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
353 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
354 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
355 let canFoldAsLoad = 1;
359 class AddImmUR2<string opstr, RegisterOperand RO> :
360 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
361 !strconcat(opstr, "\t$rd, $rs, $imm"),
362 [], NoItinerary, FrmR> {
363 let isCommutable = 1;
366 class AddImmUS5<string opstr, RegisterOperand RO> :
367 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
368 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
369 let Constraints = "$rd = $dst";
372 class AddImmUR1SP<string opstr, RegisterOperand RO> :
373 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
374 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
376 class AddImmUSP<string opstr> :
377 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
378 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
380 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
381 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
382 [], II_MFHI_MFLO, FrmR> {
384 let hasSideEffects = 0;
387 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
388 InstrItinClass Itin = NoItinerary> :
389 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
390 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
391 let isCommutable = isComm;
392 let isReMaterializable = 1;
395 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
396 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
397 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
398 let isReMaterializable = 1;
401 // 16-bit Jump and Link (Call)
402 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
403 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
404 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
406 let hasDelaySlot = 1;
411 class JumpRegMM16<string opstr, RegisterOperand RO> :
412 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
413 [], IIBranch, FrmR> {
414 let hasDelaySlot = 1;
416 let isIndirectBranch = 1;
419 // Base class for JRADDIUSP instruction.
420 class JumpRAddiuStackMM16 :
421 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
422 [], IIBranch, FrmR> {
423 let isTerminator = 1;
426 let isIndirectBranch = 1;
429 // 16-bit Jump and Link (Call) - Short Delay Slot
430 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
431 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
432 [], IIBranch, FrmR> {
434 let hasDelaySlot = 1;
438 // 16-bit Jump Register Compact - No delay slot
439 class JumpRegCMM16<string opstr, RegisterOperand RO> :
440 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
441 [], IIBranch, FrmR> {
442 let isTerminator = 1;
445 let isIndirectBranch = 1;
448 // Break16 and Sdbbp16
449 class BrkSdbbp16MM<string opstr> :
450 MicroMipsInst16<(outs), (ins uimm4:$code_),
451 !strconcat(opstr, "\t$code_"),
452 [], NoItinerary, FrmOther>;
454 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
455 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
456 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
458 let isTerminator = 1;
459 let hasDelaySlot = 1;
463 // MicroMIPS Jump and Link (Call) - Short Delay Slot
464 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
465 class JumpLinkMM<string opstr, DAGOperand opnd> :
466 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
467 [], IIBranch, FrmJ, opstr> {
468 let DecoderMethod = "DecodeJumpTargetMM";
471 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
472 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
475 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
476 RegisterOperand RO> :
477 InstSE<(outs), (ins RO:$rs, opnd:$offset),
478 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
481 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
482 InstrItinClass Itin = NoItinerary,
483 SDPatternOperator OpNode = null_frag> :
484 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
485 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
487 class PrefetchIndexed<string opstr> :
488 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
489 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
491 class AddImmUPC<string opstr, RegisterOperand RO> :
492 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
493 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
495 /// A list of registers used by load/store multiple instructions.
496 def RegListAsmOperand : AsmOperandClass {
497 let Name = "RegList";
498 let ParserMethod = "parseRegisterList";
501 def reglist : Operand<i32> {
502 let EncoderMethod = "getRegisterListOpValue";
503 let ParserMatchClass = RegListAsmOperand;
504 let PrintMethod = "printRegisterList";
505 let DecoderMethod = "DecodeRegListOperand";
508 def RegList16AsmOperand : AsmOperandClass {
509 let Name = "RegList16";
510 let ParserMethod = "parseRegisterList";
511 let PredicateMethod = "isRegList16";
512 let RenderMethod = "addRegListOperands";
515 def reglist16 : Operand<i32> {
516 let EncoderMethod = "getRegisterListOpValue16";
517 let DecoderMethod = "DecodeRegListOperand16";
518 let PrintMethod = "printRegisterList";
519 let ParserMatchClass = RegList16AsmOperand;
522 class StoreMultMM<string opstr,
523 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
524 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
525 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
526 let DecoderMethod = "DecodeMemMMImm12";
530 class LoadMultMM<string opstr,
531 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
532 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
533 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
534 let DecoderMethod = "DecodeMemMMImm12";
538 class StoreMultMM16<string opstr,
539 InstrItinClass Itin = NoItinerary,
540 ComplexPattern Addr = addr> :
541 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
542 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
543 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
547 class LoadMultMM16<string opstr,
548 InstrItinClass Itin = NoItinerary,
549 ComplexPattern Addr = addr> :
550 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
551 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
552 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
556 class UncondBranchMM16<string opstr> :
557 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
558 !strconcat(opstr, "\t$offset"),
559 [], IIBranch, FrmI> {
561 let isTerminator = 1;
563 let hasDelaySlot = 1;
564 let Predicates = [RelocPIC, InMicroMips];
568 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
569 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
570 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
571 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
572 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
573 ISA_MICROMIPS_NOT_32R6_64R6;
574 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
575 ISA_MICROMIPS_NOT_32R6_64R6;
576 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
577 ISA_MICROMIPS_NOT_32R6_64R6;
578 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
579 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
580 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
581 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
583 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
585 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
587 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
588 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
589 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
590 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
591 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
592 LOAD_STORE_FM_MM16<0x1a>;
593 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
594 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
595 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
596 II_SH, mem_mm_4_lsl1>,
597 LOAD_STORE_FM_MM16<0x2a>;
598 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
599 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
600 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
601 LOAD_GP_FM_MM16<0x19>;
602 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
603 LOAD_STORE_SP_FM_MM16<0x12>;
604 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
605 LOAD_STORE_SP_FM_MM16<0x32>;
606 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
607 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
608 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
609 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
610 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
611 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
612 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
613 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
614 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
616 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
617 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
618 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
619 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
620 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
621 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
622 BEQNEZ_FM_MM16<0x23>;
623 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
624 BEQNEZ_FM_MM16<0x2b>;
625 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
626 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
627 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
629 class WaitMM<string opstr> :
630 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
631 NoItinerary, FrmOther, opstr>;
633 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
634 /// Compact Branch Instructions
635 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
636 COMPACT_BRANCH_FM_MM<0x7>;
637 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
638 COMPACT_BRANCH_FM_MM<0x5>;
640 /// Arithmetic Instructions (ALU Immediate)
641 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
643 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
645 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
647 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
649 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
651 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
653 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
655 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
657 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
660 /// Arithmetic Instructions (3-Operand, R-Type)
661 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
663 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
665 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
666 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
667 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
668 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
669 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
671 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
673 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
675 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
677 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
678 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
680 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
682 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
684 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
687 /// Arithmetic Instructions with PC and Immediate
688 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
690 /// Shift Instructions
691 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
693 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
695 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
697 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
699 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
701 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
703 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
705 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
708 /// Load and Store Instructions - aligned
709 let DecoderMethod = "DecodeMemMMImm16" in {
710 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
711 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
712 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
713 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
714 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
715 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
716 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
717 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
720 let DecoderMethod = "DecodeMemMMImm9" in {
721 def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
722 def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
723 def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
724 def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
725 def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
726 def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
727 def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
728 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
729 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
732 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
734 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
736 /// Load and Store Instructions - unaligned
737 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
739 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
741 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
743 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
746 /// Load and Store Instructions - multiple
747 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
748 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
749 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
750 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
752 /// Load and Store Pair Instructions
753 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
754 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
756 /// Load and Store multiple pseudo Instructions
757 class LoadWordMultMM<string instr_asm > :
758 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
759 !strconcat(instr_asm, "\t$rt, $addr")> ;
761 class StoreWordMultMM<string instr_asm > :
762 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
763 !strconcat(instr_asm, "\t$rt, $addr")> ;
766 def SWM_MM : StoreWordMultMM<"swm">;
767 def LWM_MM : LoadWordMultMM<"lwm">;
770 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
771 NoItinerary>, ADD_FM_MM<0, 0x58>;
772 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
773 NoItinerary>, ADD_FM_MM<0, 0x18>;
774 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
775 CMov_F_I_FM_MM<0x25>;
776 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
779 /// Move to/from HI/LO
780 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
782 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
784 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
786 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
789 /// Multiply Add/Sub Instructions
790 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
791 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
792 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
793 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
796 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
798 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
801 /// Sign Ext In Register Instructions.
802 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
803 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
804 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
805 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
807 /// Word Swap Bytes Within Halfwords
808 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
809 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
811 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
813 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
816 /// Jump Instructions
817 let DecoderMethod = "DecodeJumpTargetMM" in {
818 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
820 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
821 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
823 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
824 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
826 /// Jump Instructions - Short Delay Slot
827 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
828 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
830 /// Branch Instructions
831 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
833 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
835 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
837 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
839 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
841 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
843 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
845 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
848 /// Branch Instructions - Short Delay Slot
849 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
850 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
851 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
852 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
854 /// Control Instructions
855 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
856 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
857 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
858 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
859 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
860 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
861 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
863 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
866 /// Trap Instructions
867 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
868 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
869 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
870 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
871 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
872 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
874 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
875 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
876 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
877 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
878 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
879 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
881 /// Load-linked, Store-conditional
882 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
883 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
885 let DecoderMethod = "DecodeCacheOpMM" in {
886 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
887 CACHE_PREF_FM_MM<0x08, 0x6>;
888 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
889 CACHE_PREF_FM_MM<0x18, 0x2>;
892 let DecoderMethod = "DecodePrefeOpMM" in {
893 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
894 CACHE_PREFE_FM_MM<0x18, 0x2>;
895 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
896 CACHE_PREFE_FM_MM<0x18, 0x3>;
898 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
899 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
900 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
902 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
903 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
904 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
905 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
907 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
908 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
910 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
913 let Predicates = [InMicroMips] in {
915 //===----------------------------------------------------------------------===//
916 // MicroMips arbitrary patterns that map to one or more instructions
917 //===----------------------------------------------------------------------===//
919 def : MipsPat<(i32 immLi16:$imm),
920 (LI16_MM immLi16:$imm)>;
921 def : MipsPat<(i32 immSExt16:$imm),
922 (ADDiu_MM ZERO, immSExt16:$imm)>;
923 def : MipsPat<(i32 immZExt16:$imm),
924 (ORi_MM ZERO, immZExt16:$imm)>;
925 def : MipsPat<(not GPR32:$in),
926 (NOR_MM GPR32Opnd:$in, ZERO)>;
928 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
929 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
930 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
931 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
932 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
933 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
935 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
936 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
937 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
938 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
940 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
941 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
942 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
943 (SLL_MM GPR32:$src, immZExt5:$imm)>;
945 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
946 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
947 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
948 (SRL_MM GPR32:$src, immZExt5:$imm)>;
950 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
951 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
952 def : MipsPat<(store GPR32:$src, addr:$addr),
953 (SW_MM GPR32:$src, addr:$addr)>;
955 def : MipsPat<(load addrimm4lsl2:$addr),
956 (LW16_MM addrimm4lsl2:$addr)>;
957 def : MipsPat<(load addr:$addr),
960 //===----------------------------------------------------------------------===//
961 // MicroMips instruction aliases
962 //===----------------------------------------------------------------------===//
964 class UncondBranchMMPseudo<string opstr> :
965 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
966 !strconcat(opstr, "\t$offset")>;
968 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
970 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
971 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
972 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
975 let Predicates = [InMicroMips] in {
976 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
977 def : MipsInstAlias<"teq $rs, $rt",
978 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
979 def : MipsInstAlias<"tge $rs, $rt",
980 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
981 def : MipsInstAlias<"tgeu $rs, $rt",
982 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
983 def : MipsInstAlias<"tlt $rs, $rt",
984 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
985 def : MipsInstAlias<"tltu $rs, $rt",
986 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
987 def : MipsInstAlias<"tne $rs, $rt",
988 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;