1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
4 def simm4 : Operand<i32> {
5 let DecoderMethod = "DecodeSimm4";
7 def simm7 : Operand<i32>;
8 def li_simm7 : Operand<i32> {
9 let DecoderMethod = "DecodeLiSimm7";
12 def simm12 : Operand<i32> {
13 let DecoderMethod = "DecodeSimm12";
16 def MipsUimm5Lsl2AsmOperand : AsmOperandClass {
17 let Name = "Uimm5Lsl2";
18 let RenderMethod = "addImmOperands";
19 let ParserMethod = "parseImm";
20 let PredicateMethod = "isUImm5Lsl2";
23 def uimm5_lsl2 : Operand<OtherVT> {
24 let EncoderMethod = "getUImm5Lsl2Encoding";
25 let DecoderMethod = "DecodeUImm5lsl2";
26 let ParserMatchClass = MipsUimm5Lsl2AsmOperand;
29 def uimm6_lsl2 : Operand<i32> {
30 let EncoderMethod = "getUImm6Lsl2Encoding";
31 let DecoderMethod = "DecodeUImm6Lsl2";
34 def simm9_addiusp : Operand<i32> {
35 let EncoderMethod = "getSImm9AddiuspValue";
36 let DecoderMethod = "DecodeSimm9SP";
39 def uimm3_shift : Operand<i32> {
40 let EncoderMethod = "getUImm3Mod8Encoding";
41 let DecoderMethod = "DecodePOOL16BEncodedField";
44 def simm3_lsa2 : Operand<i32> {
45 let EncoderMethod = "getSImm3Lsa2Value";
46 let DecoderMethod = "DecodeAddiur2Simm7";
49 def uimm4_andi : Operand<i32> {
50 let EncoderMethod = "getUImm4AndValue";
51 let DecoderMethod = "DecodeANDI16Imm";
54 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
56 Imm < 28 && Imm > 0);}]>;
58 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
60 def immZExtAndi16 : ImmLeaf<i32,
61 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
62 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
63 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
65 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
67 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
69 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
70 let Name = "MicroMipsMem";
71 let RenderMethod = "addMicroMipsMemOperands";
72 let ParserMethod = "parseMemOperand";
73 let PredicateMethod = "isMemWithGRPMM16Base";
76 class mem_mm_4_generic : Operand<i32> {
77 let PrintMethod = "printMemOperand";
78 let MIOperandInfo = (ops GPRMM16, simm4);
79 let OperandType = "OPERAND_MEMORY";
80 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
83 def mem_mm_4 : mem_mm_4_generic {
84 let EncoderMethod = "getMemEncodingMMImm4";
87 def mem_mm_4_lsl1 : mem_mm_4_generic {
88 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
91 def mem_mm_4_lsl2 : mem_mm_4_generic {
92 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
95 def MicroMipsMemSPAsmOperand : AsmOperandClass {
96 let Name = "MicroMipsMemSP";
97 let RenderMethod = "addMemOperands";
98 let ParserMethod = "parseMemOperand";
99 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
102 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
103 let PrintMethod = "printMemOperand";
104 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
105 let OperandType = "OPERAND_MEMORY";
106 let ParserMatchClass = MicroMipsMemSPAsmOperand;
107 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
110 def mem_mm_gp_imm7_lsl2 : Operand<i32> {
111 let PrintMethod = "printMemOperand";
112 let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
113 let OperandType = "OPERAND_MEMORY";
114 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
117 def mem_mm_9 : Operand<i32> {
118 let PrintMethod = "printMemOperand";
119 let MIOperandInfo = (ops GPR32, simm9);
120 let EncoderMethod = "getMemEncodingMMImm9";
121 let ParserMatchClass = MipsMemAsmOperand;
122 let OperandType = "OPERAND_MEMORY";
125 def mem_mm_12 : Operand<i32> {
126 let PrintMethod = "printMemOperand";
127 let MIOperandInfo = (ops GPR32, simm12);
128 let EncoderMethod = "getMemEncodingMMImm12";
129 let ParserMatchClass = MipsMemAsmOperand;
130 let OperandType = "OPERAND_MEMORY";
133 def mem_mm_16 : Operand<i32> {
134 let PrintMethod = "printMemOperand";
135 let MIOperandInfo = (ops GPR32, simm16);
136 let EncoderMethod = "getMemEncodingMMImm16";
137 let ParserMatchClass = MipsMemAsmOperand;
138 let OperandType = "OPERAND_MEMORY";
141 def MipsMemUimm4AsmOperand : AsmOperandClass {
142 let Name = "MemOffsetUimm4";
143 let SuperClasses = [MipsMemAsmOperand];
144 let RenderMethod = "addMemOperands";
145 let ParserMethod = "parseMemOperand";
146 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
149 def mem_mm_4sp : Operand<i32> {
150 let PrintMethod = "printMemOperand";
151 let MIOperandInfo = (ops GPR32, uimm8);
152 let EncoderMethod = "getMemEncodingMMImm4sp";
153 let ParserMatchClass = MipsMemUimm4AsmOperand;
154 let OperandType = "OPERAND_MEMORY";
157 def jmptarget_mm : Operand<OtherVT> {
158 let EncoderMethod = "getJumpTargetOpValueMM";
161 def calltarget_mm : Operand<iPTR> {
162 let EncoderMethod = "getJumpTargetOpValueMM";
165 def brtarget7_mm : Operand<OtherVT> {
166 let EncoderMethod = "getBranchTarget7OpValueMM";
167 let OperandType = "OPERAND_PCREL";
168 let DecoderMethod = "DecodeBranchTarget7MM";
169 let ParserMatchClass = MipsJumpTargetAsmOperand;
172 def brtarget10_mm : Operand<OtherVT> {
173 let EncoderMethod = "getBranchTargetOpValueMMPC10";
174 let OperandType = "OPERAND_PCREL";
175 let DecoderMethod = "DecodeBranchTarget10MM";
176 let ParserMatchClass = MipsJumpTargetAsmOperand;
179 def brtarget_mm : Operand<OtherVT> {
180 let EncoderMethod = "getBranchTargetOpValueMM";
181 let OperandType = "OPERAND_PCREL";
182 let DecoderMethod = "DecodeBranchTargetMM";
183 let ParserMatchClass = MipsJumpTargetAsmOperand;
186 def simm23_lsl2 : Operand<i32> {
187 let EncoderMethod = "getSimm23Lsl2Encoding";
188 let DecoderMethod = "DecodeSimm23Lsl2";
191 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
192 RegisterOperand RO> :
193 InstSE<(outs), (ins RO:$rs, opnd:$offset),
194 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
196 let isTerminator = 1;
197 let hasDelaySlot = 0;
201 let canFoldAsLoad = 1 in
202 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
204 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
205 !strconcat(opstr, "\t$rt, $addr"),
206 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
208 let DecoderMethod = "DecodeMemMMImm12";
209 string Constraints = "$src = $rt";
212 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
214 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
215 !strconcat(opstr, "\t$rt, $addr"),
216 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
217 let DecoderMethod = "DecodeMemMMImm12";
220 /// A register pair used by movep instruction.
221 def MovePRegPairAsmOperand : AsmOperandClass {
222 let Name = "MovePRegPair";
223 let ParserMethod = "parseMovePRegPair";
224 let PredicateMethod = "isMovePRegPair";
227 def movep_regpair : Operand<i32> {
228 let EncoderMethod = "getMovePRegPairOpValue";
229 let ParserMatchClass = MovePRegPairAsmOperand;
230 let PrintMethod = "printRegisterList";
231 let DecoderMethod = "DecodeMovePRegPair";
232 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
235 class MovePMM16<string opstr, RegisterOperand RO> :
236 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
237 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
239 let isReMaterializable = 1;
242 /// A register pair used by load/store pair instructions.
243 def RegPairAsmOperand : AsmOperandClass {
244 let Name = "RegPair";
245 let ParserMethod = "parseRegisterPair";
248 def regpair : Operand<i32> {
249 let EncoderMethod = "getRegisterPairOpValue";
250 let ParserMatchClass = RegPairAsmOperand;
251 let PrintMethod = "printRegisterPair";
252 let DecoderMethod = "DecodeRegPairOperand";
253 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
256 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
257 ComplexPattern Addr = addr> :
258 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
259 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
260 let DecoderMethod = "DecodeMemMMImm12";
264 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
265 ComplexPattern Addr = addr> :
266 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
267 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
268 let DecoderMethod = "DecodeMemMMImm12";
272 class LLBaseMM<string opstr, RegisterOperand RO> :
273 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
274 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
275 let DecoderMethod = "DecodeMemMMImm12";
279 class LLEBaseMM<string opstr, RegisterOperand RO> :
280 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
281 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
282 let DecoderMethod = "DecodeMemMMImm9";
286 class SCBaseMM<string opstr, RegisterOperand RO> :
287 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
288 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
289 let DecoderMethod = "DecodeMemMMImm12";
291 let Constraints = "$rt = $dst";
294 class SCEBaseMM<string opstr, RegisterOperand RO> :
295 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
296 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
297 let DecoderMethod = "DecodeMemMMImm9";
299 let Constraints = "$rt = $dst";
302 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
303 InstrItinClass Itin = NoItinerary> :
304 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
305 !strconcat(opstr, "\t$rt, $addr"),
306 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
307 let DecoderMethod = "DecodeMemMMImm12";
308 let canFoldAsLoad = 1;
312 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
313 InstrItinClass Itin = NoItinerary,
314 SDPatternOperator OpNode = null_frag> :
315 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
316 !strconcat(opstr, "\t$rd, $rs, $rt"),
317 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
318 let isCommutable = isComm;
321 class AndImmMM16<string opstr, RegisterOperand RO,
322 InstrItinClass Itin = NoItinerary> :
323 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
324 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
326 class LogicRMM16<string opstr, RegisterOperand RO,
327 InstrItinClass Itin = NoItinerary,
328 SDPatternOperator OpNode = null_frag> :
329 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
330 !strconcat(opstr, "\t$rt, $rs"),
331 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
332 let isCommutable = 1;
333 let Constraints = "$rt = $dst";
336 class NotMM16<string opstr, RegisterOperand RO> :
337 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
338 !strconcat(opstr, "\t$rt, $rs"),
339 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
341 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
342 InstrItinClass Itin = NoItinerary> :
343 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
344 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
346 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
347 InstrItinClass Itin, Operand MemOpnd> :
348 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
349 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
350 let DecoderMethod = "DecodeMemMMImm4";
351 let canFoldAsLoad = 1;
355 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
356 SDPatternOperator OpNode, InstrItinClass Itin,
358 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
359 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
360 let DecoderMethod = "DecodeMemMMImm4";
364 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
366 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
367 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
368 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
369 let canFoldAsLoad = 1;
373 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
375 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
376 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
377 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
381 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
383 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
384 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
385 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
386 let canFoldAsLoad = 1;
390 class AddImmUR2<string opstr, RegisterOperand RO> :
391 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
392 !strconcat(opstr, "\t$rd, $rs, $imm"),
393 [], NoItinerary, FrmR> {
394 let isCommutable = 1;
397 class AddImmUS5<string opstr, RegisterOperand RO> :
398 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
399 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
400 let Constraints = "$rd = $dst";
403 class AddImmUR1SP<string opstr, RegisterOperand RO> :
404 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
405 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
407 class AddImmUSP<string opstr> :
408 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
409 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
411 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
412 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
413 [], II_MFHI_MFLO, FrmR> {
415 let hasSideEffects = 0;
418 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
419 InstrItinClass Itin = NoItinerary> :
420 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
421 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
422 let isCommutable = isComm;
423 let isReMaterializable = 1;
426 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
427 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
428 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
429 let isReMaterializable = 1;
432 // 16-bit Jump and Link (Call)
433 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
434 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
435 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
437 let hasDelaySlot = 1;
442 class JumpRegMM16<string opstr, RegisterOperand RO> :
443 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
445 let hasDelaySlot = 1;
447 let isIndirectBranch = 1;
450 // Base class for JRADDIUSP instruction.
451 class JumpRAddiuStackMM16 :
452 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
453 [], II_JRADDIUSP, FrmR> {
454 let isTerminator = 1;
457 let isIndirectBranch = 1;
460 // 16-bit Jump and Link (Call) - Short Delay Slot
461 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
462 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
463 [], II_JALRS, FrmR> {
465 let hasDelaySlot = 1;
469 // 16-bit Jump Register Compact - No delay slot
470 class JumpRegCMM16<string opstr, RegisterOperand RO> :
471 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
473 let isTerminator = 1;
476 let isIndirectBranch = 1;
479 // Break16 and Sdbbp16
480 class BrkSdbbp16MM<string opstr> :
481 MicroMipsInst16<(outs), (ins uimm4:$code_),
482 !strconcat(opstr, "\t$code_"),
483 [], NoItinerary, FrmOther>;
485 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
486 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
487 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
489 let isTerminator = 1;
490 let hasDelaySlot = 1;
494 // MicroMIPS Jump and Link (Call) - Short Delay Slot
495 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
496 class JumpLinkMM<string opstr, DAGOperand opnd> :
497 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
498 [], II_JALS, FrmJ, opstr> {
499 let DecoderMethod = "DecodeJumpTargetMM";
502 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
503 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
506 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
507 RegisterOperand RO> :
508 InstSE<(outs), (ins RO:$rs, opnd:$offset),
509 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
512 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
513 InstrItinClass Itin = NoItinerary,
514 SDPatternOperator OpNode = null_frag> :
515 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
516 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
518 class PrefetchIndexed<string opstr> :
519 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
520 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
522 class AddImmUPC<string opstr, RegisterOperand RO> :
523 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
524 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
526 /// A list of registers used by load/store multiple instructions.
527 def RegListAsmOperand : AsmOperandClass {
528 let Name = "RegList";
529 let ParserMethod = "parseRegisterList";
532 def reglist : Operand<i32> {
533 let EncoderMethod = "getRegisterListOpValue";
534 let ParserMatchClass = RegListAsmOperand;
535 let PrintMethod = "printRegisterList";
536 let DecoderMethod = "DecodeRegListOperand";
539 def RegList16AsmOperand : AsmOperandClass {
540 let Name = "RegList16";
541 let ParserMethod = "parseRegisterList";
542 let PredicateMethod = "isRegList16";
543 let RenderMethod = "addRegListOperands";
546 def reglist16 : Operand<i32> {
547 let EncoderMethod = "getRegisterListOpValue16";
548 let DecoderMethod = "DecodeRegListOperand16";
549 let PrintMethod = "printRegisterList";
550 let ParserMatchClass = RegList16AsmOperand;
553 class StoreMultMM<string opstr,
554 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
555 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
556 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
557 let DecoderMethod = "DecodeMemMMImm12";
561 class LoadMultMM<string opstr,
562 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
563 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
564 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
565 let DecoderMethod = "DecodeMemMMImm12";
569 class StoreMultMM16<string opstr,
570 InstrItinClass Itin = NoItinerary,
571 ComplexPattern Addr = addr> :
572 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
573 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
574 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
578 class LoadMultMM16<string opstr,
579 InstrItinClass Itin = NoItinerary,
580 ComplexPattern Addr = addr> :
581 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
582 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
583 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
587 class UncondBranchMM16<string opstr> :
588 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
589 !strconcat(opstr, "\t$offset"),
592 let isTerminator = 1;
594 let hasDelaySlot = 1;
595 let Predicates = [RelocPIC, InMicroMips];
599 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
600 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
601 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
602 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
603 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
604 ISA_MICROMIPS_NOT_32R6_64R6;
605 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
606 ISA_MICROMIPS_NOT_32R6_64R6;
607 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
608 ISA_MICROMIPS_NOT_32R6_64R6;
609 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
610 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
611 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
612 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
614 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
615 ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
616 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
617 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
618 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
619 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
620 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
621 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
622 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
623 LOAD_STORE_FM_MM16<0x1a>;
624 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
625 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
626 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
627 II_SH, mem_mm_4_lsl1>,
628 LOAD_STORE_FM_MM16<0x2a>;
629 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
630 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
631 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
632 LOAD_GP_FM_MM16<0x19>;
633 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
634 LOAD_STORE_SP_FM_MM16<0x12>;
635 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
636 LOAD_STORE_SP_FM_MM16<0x32>;
637 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
638 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
639 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
640 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
641 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
642 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
643 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
644 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
645 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
647 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
648 ISA_MICROMIPS32_NOT_MIPS32R6;
649 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
650 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
651 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
652 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
653 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
654 BEQNEZ_FM_MM16<0x23>;
655 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
656 BEQNEZ_FM_MM16<0x2b>;
657 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
658 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
659 ISA_MICROMIPS_NOT_32R6_64R6;
660 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
661 ISA_MICROMIPS_NOT_32R6_64R6;
663 class WaitMM<string opstr> :
664 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
665 NoItinerary, FrmOther, opstr>;
667 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
668 /// Compact Branch Instructions
669 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
670 COMPACT_BRANCH_FM_MM<0x7>;
671 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
672 COMPACT_BRANCH_FM_MM<0x5>;
674 /// Arithmetic Instructions (ALU Immediate)
675 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
677 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
679 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
681 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
683 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
685 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
687 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
689 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
691 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
694 /// Arithmetic Instructions (3-Operand, R-Type)
695 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
697 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
699 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
700 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
701 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
702 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
703 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
705 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
707 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
709 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
711 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
712 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
714 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
716 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
718 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
721 /// Arithmetic Instructions with PC and Immediate
722 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
724 /// Shift Instructions
725 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
727 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
729 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
731 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
733 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
735 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
737 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
739 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
742 /// Load and Store Instructions - aligned
743 let DecoderMethod = "DecodeMemMMImm16" in {
744 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
745 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
746 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
747 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
748 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
749 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
750 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
751 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
754 let DecoderMethod = "DecodeMemMMImm9" in {
755 def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
756 def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
757 def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
758 def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
759 def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
760 def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
761 def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
762 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
763 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
766 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
768 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
770 /// Load and Store Instructions - unaligned
771 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
773 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
775 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
777 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
779 let DecoderMethod = "DecodeMemMMImm9" in {
780 def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
781 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
782 def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
783 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
784 def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
785 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
786 def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
787 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
790 /// Load and Store Instructions - multiple
791 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
792 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
793 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
794 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
796 /// Load and Store Pair Instructions
797 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
798 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
800 /// Load and Store multiple pseudo Instructions
801 class LoadWordMultMM<string instr_asm > :
802 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
803 !strconcat(instr_asm, "\t$rt, $addr")> ;
805 class StoreWordMultMM<string instr_asm > :
806 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
807 !strconcat(instr_asm, "\t$rt, $addr")> ;
810 def SWM_MM : StoreWordMultMM<"swm">;
811 def LWM_MM : LoadWordMultMM<"lwm">;
814 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
815 NoItinerary>, ADD_FM_MM<0, 0x58>;
816 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
817 NoItinerary>, ADD_FM_MM<0, 0x18>;
818 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
819 CMov_F_I_FM_MM<0x25>;
820 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
823 /// Move to/from HI/LO
824 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
826 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
828 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
830 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
833 /// Multiply Add/Sub Instructions
834 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
835 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
836 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
837 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
840 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
842 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
845 /// Sign Ext In Register Instructions.
846 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
847 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
848 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
849 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
851 /// Word Swap Bytes Within Halfwords
852 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
853 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
855 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
857 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
860 /// Jump Instructions
861 let DecoderMethod = "DecodeJumpTargetMM" in {
862 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
864 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
865 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
867 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
868 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
870 /// Jump Instructions - Short Delay Slot
871 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
872 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
874 /// Branch Instructions
875 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
877 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
879 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
881 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
883 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
885 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
887 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
889 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
892 /// Branch Instructions - Short Delay Slot
893 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
894 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
895 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
896 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
898 /// Control Instructions
899 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
900 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
901 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
902 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
903 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
904 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
905 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
907 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
910 /// Trap Instructions
911 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
912 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
913 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
914 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
915 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
916 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
918 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
919 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
920 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
921 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
922 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
923 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
925 /// Load-linked, Store-conditional
926 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
927 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
929 def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
930 def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
932 let DecoderMethod = "DecodeCacheOpMM" in {
933 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
934 CACHE_PREF_FM_MM<0x08, 0x6>;
935 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
936 CACHE_PREF_FM_MM<0x18, 0x2>;
939 let DecoderMethod = "DecodePrefeOpMM" in {
940 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
941 CACHE_PREFE_FM_MM<0x18, 0x2>;
942 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
943 CACHE_PREFE_FM_MM<0x18, 0x3>;
945 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
946 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
947 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
949 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
950 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
951 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
952 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
954 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
956 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
959 let DecoderNamespace = "MicroMips" in {
960 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
961 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
964 let Predicates = [InMicroMips] in {
966 //===----------------------------------------------------------------------===//
967 // MicroMips arbitrary patterns that map to one or more instructions
968 //===----------------------------------------------------------------------===//
970 def : MipsPat<(i32 immLi16:$imm),
971 (LI16_MM immLi16:$imm)>;
972 def : MipsPat<(i32 immSExt16:$imm),
973 (ADDiu_MM ZERO, immSExt16:$imm)>;
974 def : MipsPat<(i32 immZExt16:$imm),
975 (ORi_MM ZERO, immZExt16:$imm)>;
976 def : MipsPat<(not GPR32:$in),
977 (NOR_MM GPR32Opnd:$in, ZERO)>;
979 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
980 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
981 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
982 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
983 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
984 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
986 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
987 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
988 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
989 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
991 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
992 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
993 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
994 (SLL_MM GPR32:$src, immZExt5:$imm)>;
996 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
997 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
998 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
999 (SRL_MM GPR32:$src, immZExt5:$imm)>;
1001 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1002 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
1003 def : MipsPat<(store GPR32:$src, addr:$addr),
1004 (SW_MM GPR32:$src, addr:$addr)>;
1006 def : MipsPat<(load addrimm4lsl2:$addr),
1007 (LW16_MM addrimm4lsl2:$addr)>;
1008 def : MipsPat<(load addr:$addr),
1009 (LW_MM addr:$addr)>;
1011 //===----------------------------------------------------------------------===//
1012 // MicroMips instruction aliases
1013 //===----------------------------------------------------------------------===//
1015 class UncondBranchMMPseudo<string opstr> :
1016 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1017 !strconcat(opstr, "\t$offset")>;
1019 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1021 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
1022 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
1023 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
1026 let Predicates = [InMicroMips] in {
1027 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
1028 def : MipsInstAlias<"teq $rs, $rt",
1029 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1030 def : MipsInstAlias<"tge $rs, $rt",
1031 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1032 def : MipsInstAlias<"tgeu $rs, $rt",
1033 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1034 def : MipsInstAlias<"tlt $rs, $rt",
1035 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1036 def : MipsInstAlias<"tltu $rs, $rt",
1037 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1038 def : MipsInstAlias<"tne $rs, $rt",
1039 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;