1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
23 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
24 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
25 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
26 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
28 //===----------------------------------------------------------------------===//
30 // Instruction Descriptions
32 //===----------------------------------------------------------------------===//
34 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
35 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
36 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
38 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
39 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
40 dag InOperandList = (ins opnd:$offset);
41 dag OutOperandList = (outs);
42 string AsmString = !strconcat(instr_asm, "\t$offset");
46 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
48 list<Register> Defs = [RA];
50 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
52 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
53 : MMR6Arch<instr_asm> {
54 dag OutOperandList = (outs GPROpnd:$rd);
55 dag InOperandList = (ins GPROpnd:$rt);
56 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
57 list<dag> Pattern = [];
60 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
62 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
63 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
64 dag OutOperandList = (outs);
65 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
66 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
67 list<dag> Pattern = [];
68 string DecoderMethod = "DecodeCacheOpMM";
71 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
72 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
74 //===----------------------------------------------------------------------===//
76 // Instruction Definitions
78 //===----------------------------------------------------------------------===//
80 let DecoderNamespace = "MicroMips32r6" in {
81 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
82 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
83 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
84 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
85 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
86 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
88 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
89 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;