lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 //
  16 // Instruction Encodings
  17 //
  18 //===----------------------------------------------------------------------===//
  19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  28 class AUI_MMR6_ENC : AUI_FM_MMR6;
  29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  51 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  52 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  53 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  54 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  55 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  56 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  57 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  58 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  59 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  60 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  61 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  62 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  63 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  64 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  65 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  66 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  67 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  68 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  69 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  70 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  71 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  72 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  73 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  74 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  75 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  76 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  77 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  78 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
  79 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
  80 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
  81 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
  82 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
  83 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
  84 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
  85 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
  86 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
  87 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
  88 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
  89 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
  90 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
  91 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
  92 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
  93 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
  94 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
  95 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
  96 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
  97 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
  98 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
  99 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 100 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 101 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 102 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 103 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 104 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 105
 106 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 107 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 108 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 109 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 110 class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
 111 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 112 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 113
 114 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 115                                   RegisterOperand GPROpnd>
 116     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 117   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 118   dag OutOperandList = (outs);
 119   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 120   list<Register> Defs = [AT];
 121 }
 122
 123 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 124                                                       GPR32Opnd> {
 125   list<Register> Defs = [RA];
 126 }
 127
 128 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 129                                                       GPR32Opnd> {
 130   list<Register> Defs = [RA];
 131 }
 132
 133 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 134                                                       GPR32Opnd> {
 135   list<Register> Defs = [RA];
 136 }
 137
 138 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 139                                                       GPR32Opnd> {
 140   list<Register> Defs = [RA];
 141 }
 142
 143 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 144                                                       GPR32Opnd> {
 145   list<Register> Defs = [RA];
 146 }
 147
 148 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 149                                                       GPR32Opnd> {
 150   list<Register> Defs = [RA];
 151 }
 152
 153 /// Floating Point Instructions
 154 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 155 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 156 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 157 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 158 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 159 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 160 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 161 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 162 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 163 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 164 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 165 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 166 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 167 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 168 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 169 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 170 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 171 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 172 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 173 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 174 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 175 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 176 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 177 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 178
 179 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 180 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 181 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 182 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 183 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 184 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 185 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 186 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 187 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 188 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 189
 190 //===----------------------------------------------------------------------===//
 191 //
 192 // Instruction Descriptions
 193 //
 194 //===----------------------------------------------------------------------===//
 195
 196 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 197 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 198 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 199 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 200 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 201 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 202 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 203
 204 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 205     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 206   dag InOperandList = (ins opnd:$offset);
 207   dag OutOperandList = (outs);
 208   string AsmString = !strconcat(instr_asm, "\t$offset");
 209   bit isBarrier = 1;
 210 }
 211
 212 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 213   bit isCall = 1;
 214   list<Register> Defs = [RA];
 215 }
 216 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 217
 218 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 219                                        !strconcat("bc16", "\t$offset"), [],
 220                                        IIBranch, FrmI>,
 221                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 222   let isBranch = 1;
 223   let isTerminator = 1;
 224   let isBarrier = 1;
 225   let hasDelaySlot = 0;
 226   let AdditionalPredicates = [RelocPIC];
 227   let Defs = [AT];
 228 }
 229
 230 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 231     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 232   let isBranch = 1;
 233   let isTerminator = 1;
 234   let hasDelaySlot = 0;
 235   let Defs = [AT];
 236 }
 237 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 238 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 239
 240 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 241 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 242
 243 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 244     : MMR6Arch<instr_asm> {
 245   dag OutOperandList = (outs GPROpnd:$rd);
 246   dag InOperandList = (ins GPROpnd:$rt);
 247   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 248   list<dag> Pattern = [];
 249 }
 250
 251 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 252
 253 class BRK_MMR6_DESC : BRK_FT<"break">;
 254
 255 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 256                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 257   dag OutOperandList = (outs);
 258   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 259   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 260   list<dag> Pattern = [];
 261   string DecoderMethod = "DecodeCacheOpMM";
 262 }
 263
 264 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 265 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 266
 267 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 268                                   RegisterOperand GPROpnd> :
 269                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 270                                   GPROpnd> {
 271   string DecoderMethod = "DecodePrefeOpMM";
 272 }
 273
 274 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 275 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 276
 277 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 278     : MMR6Arch<instr_asm> {
 279   dag OutOperandList = (outs GPROpnd:$rt);
 280   dag InOperandList = (ins GPROpnd:$rs);
 281   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 282 }
 283
 284 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 285 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 286
 287 class EHB_MMR6_DESC : Barrier<"ehb">;
 288 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 289
 290 class ERET_MMR6_DESC : ER_FT<"eret">;
 291 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 292
 293 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 294                                      RegisterOperand GPROpnd>
 295     : MMR6Arch<opstr> {
 296   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 297   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 298   list<dag> Pattern = [];
 299   bit isTerminator = 1;
 300   bit hasDelaySlot = 0;
 301 }
 302
 303 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 304                                                        GPR32Opnd> {
 305   bit isCall = 1;
 306   list<Register> Defs = [RA];
 307 }
 308
 309 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 310                                                      GPR32Opnd> {
 311   bit isBarrier = 1;
 312   list<Register> Defs = [AT];
 313 }
 314
 315 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 316                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 317   dag OutOperandList = (outs GPROpnd:$rd);
 318   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 319   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 320   list<dag> Pattern = [];
 321 }
 322
 323 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 324
 325 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 326     : MMR6Arch<instr_asm> {
 327   dag OutOperandList = (outs GPROpnd:$rt);
 328   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 329   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 330   list<dag> Pattern = [];
 331 }
 332
 333 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 334
 335 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 336 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 337 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 338     : MMR6Arch<instr_asm> {
 339   dag OutOperandList = (outs GPROpnd:$rt);
 340   dag InOperandList = (ins simm16:$imm);
 341   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 342   list<dag> Pattern = [];
 343 }
 344
 345 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 346 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 347
 348 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 349                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 350   dag OutOperandList = (outs GPROpnd:$rd);
 351   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 352   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 353   list<dag> Pattern = [];
 354 }
 355
 356 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 357
 358 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 359                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 360   dag OutOperandList = (outs GPROpnd:$rt);
 361   dag InOperandList = (ins ImmOpnd:$imm);
 362   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 363   list<dag> Pattern = [];
 364 }
 365
 366 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 367 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 368
 369 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 370     : MMR6Arch<instr_asm> {
 371   dag OutOperandList = (outs GPROpnd:$rd);
 372   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 373   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 374   list<dag> Pattern = [];
 375 }
 376
 377 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 378 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 379 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 380 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 381 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 382 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 383 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 384 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 385 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 386 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 387 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 388 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 389 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 390 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 391
 392 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 393                   SDPatternOperator OpNode = null_frag,
 394                   InstrItinClass Itin = NoItinerary,
 395                   ComplexPattern Addr = addr> :
 396   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 397          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 398   let DecoderMethod = "DecodeMem";
 399   let mayStore = 1;
 400 }
 401 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 402 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 403
 404 /// Floating Point Instructions
 405 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 406                             InstrItinClass Itin, bit isComm,
 407                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 408   dag OutOperandList = (outs RC:$fd);
 409   dag InOperandList = (ins RC:$ft, RC:$fs);
 410   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 411   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 412   InstrItinClass Itinerary = Itin;
 413   bit isCommutable = isComm;
 414 }
 415 class FADD_S_MMR6_DESC
 416   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 417 class FADD_D_MMR6_DESC
 418   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 419 class FSUB_S_MMR6_DESC
 420   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 421 class FSUB_D_MMR6_DESC
 422   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 423 class FMUL_S_MMR6_DESC
 424   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 425 class FMUL_D_MMR6_DESC
 426   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 427 class FDIV_S_MMR6_DESC
 428   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 429 class FDIV_D_MMR6_DESC
 430   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 431 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 432 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 433 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 434 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 435
 436 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 437                                RegisterOperand SrcRC, InstrItinClass Itin,
 438                                SDPatternOperator OpNode = null_frag>
 439                                : HARDFLOAT, NeverHasSideEffects {
 440   dag OutOperandList = (outs DstRC:$ft);
 441   dag InOperandList = (ins SrcRC:$fs);
 442   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 443   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 444   InstrItinClass Itinerary = Itin;
 445   Format Form = FrmFR;
 446 }
 447 class FMOV_S_MMR6_DESC
 448   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 449 class FMOV_D_MMR6_DESC
 450   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 451 class FNEG_S_MMR6_DESC
 452   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 453 class FNEG_D_MMR6_DESC
 454   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 455
 456 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 457 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 458 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 459 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 460
 461 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 462 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 463 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 464 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 465
 466 class CVT_MMR6_DESC_BASE<
 467     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 468     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 469     : HARDFLOAT, NeverHasSideEffects {
 470   dag OutOperandList = (outs DstRC:$ft);
 471   dag InOperandList = (ins SrcRC:$fs);
 472   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 473   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 474   InstrItinClass Itinerary = Itin;
 475   Format Form = FrmFR;
 476 }
 477
 478 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 479                                              II_CVT>;
 480 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 481                                              II_CVT>;
 482 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 483                                              II_CVT>;
 484 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 485                                              II_CVT>;
 486 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 487                                              II_CVT>;
 488 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 489                                              II_CVT>;
 490 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 491                                              II_CVT>, FGR_64;
 492 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 493                                              II_CVT>;
 494 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 495                                              II_CVT>;
 496 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 497                                              II_CVT>, FGR_64;
 498
 499 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 500                        RegisterOperand FGROpnd> {
 501   def CMP_AF_#NAME : POOL32F_CMP_FM<
 502       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 503       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 504       ISA_MICROMIPS32R6;
 505   def CMP_UN_#NAME : POOL32F_CMP_FM<
 506       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 507       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 508       ISA_MICROMIPS32R6;
 509   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 510       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 511       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 512       ISA_MICROMIPS32R6;
 513   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 514       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 515       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 516       ISA_MICROMIPS32R6;
 517   def CMP_LT_#NAME : POOL32F_CMP_FM<
 518       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 519       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 520       ISA_MICROMIPS32R6;
 521   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 522       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 523       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 524       ISA_MICROMIPS32R6;
 525   def CMP_LE_#NAME : POOL32F_CMP_FM<
 526       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 527       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 528       ISA_MICROMIPS32R6;
 529   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 530       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 531       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 532       ISA_MICROMIPS32R6;
 533   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 534       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 535       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 536       ISA_MICROMIPS32R6;
 537   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 538       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 539       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 540       ISA_MICROMIPS32R6;
 541   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 542       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 543       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 544       ISA_MICROMIPS32R6;
 545   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 546       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 547       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 548       ISA_MICROMIPS32R6;
 549   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 550       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 551       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 552       ISA_MICROMIPS32R6;
 553   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 554       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 555       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 556       ISA_MICROMIPS32R6;
 557   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 558       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 559       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 560       ISA_MICROMIPS32R6;
 561   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 562       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 563       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 564       ISA_MICROMIPS32R6;
 565 }
 566
 567 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 568                              RegisterOperand SrcRC, InstrItinClass Itin,
 569                              SDPatternOperator OpNode = null_frag>
 570     : HARDFLOAT, NeverHasSideEffects {
 571   dag OutOperandList = (outs DstRC:$ft);
 572   dag InOperandList  = (ins SrcRC:$fs);
 573   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 574   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 575   InstrItinClass Itinerary = Itin;
 576   Format Form = FrmFR;
 577   list<Predicate> EncodingPredicates = [HasStdEnc];
 578 }
 579
 580 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 581                                                 II_ABS, fabs>;
 582 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 583                                                 II_ABS, fabs>;
 584 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 585                                                     FGR32Opnd, II_FLOOR>;
 586 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 587                                                     FGR64Opnd, II_FLOOR>;
 588 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 589                                                     FGR32Opnd, II_FLOOR>;
 590 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 591                                                     AFGR64Opnd, II_FLOOR>;
 592 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 593                                                    FGR32Opnd, II_CEIL>;
 594 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 595                                                    FGR64Opnd, II_CEIL>;
 596 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 597                                                    FGR32Opnd, II_CEIL>;
 598 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 599                                                    AFGR64Opnd, II_CEIL>;
 600 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 601                                                     FGR32Opnd, II_TRUNC>;
 602 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 603                                                     FGR64Opnd, II_TRUNC>;
 604 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 605                                                     FGR32Opnd, II_TRUNC>;
 606 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 607                                                     AFGR64Opnd, II_TRUNC>;
 608 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 609                                                  II_SQRT_S, fsqrt>;
 610 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 611                                                  II_SQRT_D, fsqrt>;
 612 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 613                                                   FGR32Opnd, II_TRUNC>;
 614 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 615                                                   AFGR64Opnd, II_TRUNC>;
 616
 617 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 618     : Store<opstr, RO>, MMR6Arch<opstr> {
 619   let DecoderMethod = "DecodeMemMMImm16";
 620 }
 621 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 622
 623 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 624     : MMR6Arch<instr_asm>, MipsR6Inst {
 625   dag OutOperandList = (outs);
 626   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 627   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 628   string DecoderMethod = "DecodeStoreEvaOpMM";
 629   bit mayStore = 1;
 630 }
 631 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 632 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 633 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 634 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 635
 636 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 637             MMR6Arch<instr_asm>, MipsR6Inst {
 638   dag OutOperandList = (outs RO:$rt);
 639   dag InOperandList = (ins mem_mm_12:$addr);
 640   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 641   string DecoderMethod = "DecodeMemMMImm9";
 642   bit mayLoad = 1;
 643 }
 644 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 645 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 646 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 647   MMR6Arch<"addu16">;
 648 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 649   MMR6Arch<"and16">;
 650 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 651   MMR6Arch<"andi16">;
 652 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 653 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 654   MMR6Arch<"or16">;
 655 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 656   MMR6Arch<"sll16">;
 657 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 658   MMR6Arch<"srl16">;
 659
 660 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 661   dag OutOperandList = (outs GPR32Opnd:$rt);
 662   dag InOperandList = (ins mem:$addr);
 663   string AsmString = "lw\t$rt, $addr";
 664   let DecoderMethod = "DecodeMemMMImm16";
 665   let canFoldAsLoad = 1;
 666   let mayLoad = 1;
 667   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 668   InstrItinClass Itinerary = II_LW;
 669 }
 670
 671 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 672   dag OutOperandList = (outs GPR32Opnd:$rt);
 673   dag InOperandList = (ins uimm16:$imm16);
 674   string AsmString = "lui\t$rt, $imm16";
 675   list<dag> Pattern = [];
 676   bit hasSideEffects = 0;
 677   bit isReMaterializable = 1;
 678   InstrItinClass Itinerary = II_LUI;
 679   Format Form = FrmI;
 680 }
 681
 682 //===----------------------------------------------------------------------===//
 683 //
 684 // Instruction Definitions
 685 //
 686 //===----------------------------------------------------------------------===//
 687
 688 let DecoderNamespace = "MicroMipsR6" in {
 689 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 690 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 691 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 692 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 693                    ISA_MICROMIPS32R6;
 694 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 695                   ISA_MICROMIPS32R6;
 696 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 697 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 698 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 699 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 700 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 701 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 702 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 703 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 704 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 705                    ISA_MICROMIPS32R6;
 706 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 707                    ISA_MICROMIPS32R6;
 708 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 709                    ISA_MICROMIPS32R6;
 710 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 711                    ISA_MICROMIPS32R6;
 712 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 713                    ISA_MICROMIPS32R6;
 714 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 715                    ISA_MICROMIPS32R6;
 716 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 717                    ISA_MICROMIPS32R6;
 718 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 719                    ISA_MICROMIPS32R6;
 720 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 721                    ISA_MICROMIPS32R6;
 722 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 723 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 724 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 725 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 726 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 727 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 728 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 729 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 730 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 731 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 732                   ISA_MICROMIPS32R6;
 733 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 734 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 735 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 736 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 737 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 738 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 739 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 740 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 741 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 742 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 743 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 744 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 745 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 746 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 747 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 748 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 749 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 750                   ISA_MICROMIPS32R6;
 751 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 752                   ISA_MICROMIPS32R6;
 753 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 754 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 755 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 756 def PREFE_MMR6 : R6MMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
 757 def CACHEE_MMR6 : R6MMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC, ISA_MICROMIPS32R6;
 758 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 759 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 760 let DecoderMethod = "DecodeMemMMImm16" in {
 761   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 762 }
 763 let DecoderMethod = "DecodeMemMMImm9" in {
 764   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 765 }
 766 /// Floating Point Instructions
 767 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 768                   ISA_MICROMIPS32R6;
 769 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 770                   ISA_MICROMIPS32R6;
 771 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 772                   ISA_MICROMIPS32R6;
 773 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 774                   ISA_MICROMIPS32R6;
 775 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 776                   ISA_MICROMIPS32R6;
 777 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 778                   ISA_MICROMIPS32R6;
 779 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 780                   ISA_MICROMIPS32R6;
 781 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 782                   ISA_MICROMIPS32R6;
 783 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 784                    ISA_MICROMIPS32R6;
 785 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 786                    ISA_MICROMIPS32R6;
 787 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 788                    ISA_MICROMIPS32R6;
 789 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 790                    ISA_MICROMIPS32R6;
 791 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 792                   ISA_MICROMIPS32R6;
 793 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 794                   ISA_MICROMIPS32R6;
 795 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 796                   ISA_MICROMIPS32R6;
 797 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 798                   ISA_MICROMIPS32R6;
 799 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 800 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 801 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 802 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 803 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 804                   ISA_MICROMIPS32R6;
 805 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 806                   ISA_MICROMIPS32R6;
 807 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 808                   ISA_MICROMIPS32R6;
 809 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 810                   ISA_MICROMIPS32R6;
 811 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 812                    ISA_MICROMIPS32R6;
 813 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 814                    ISA_MICROMIPS32R6;
 815 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 816                    ISA_MICROMIPS32R6;
 817 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 818                    ISA_MICROMIPS32R6;
 819 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 820                    ISA_MICROMIPS32R6;
 821 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 822                    ISA_MICROMIPS32R6;
 823 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 824                    ISA_MICROMIPS32R6;
 825 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 826                    ISA_MICROMIPS32R6;
 827 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 828                    ISA_MICROMIPS32R6;
 829 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 830                    ISA_MICROMIPS32R6;
 831 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 832 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 833 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 834 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 835 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
 836                      ISA_MICROMIPS32R6;
 837 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
 838                      ISA_MICROMIPS32R6;
 839 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
 840                      ISA_MICROMIPS32R6;
 841 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
 842                      ISA_MICROMIPS32R6;
 843 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
 844                     ISA_MICROMIPS32R6;
 845 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
 846                     ISA_MICROMIPS32R6;
 847 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
 848                     ISA_MICROMIPS32R6;
 849 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
 850                     ISA_MICROMIPS32R6;
 851 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
 852                      ISA_MICROMIPS32R6;
 853 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
 854                      ISA_MICROMIPS32R6;
 855 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
 856                      ISA_MICROMIPS32R6;
 857 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
 858                      ISA_MICROMIPS32R6;
 859 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
 860                   ISA_MICROMIPS32R6;
 861 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
 862                   ISA_MICROMIPS32R6;
 863 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
 864                    ISA_MICROMIPS32R6;
 865 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
 866                    ISA_MICROMIPS32R6;
 867 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 868 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 869 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 870 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 871 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 872 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
 873 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 874 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 875 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
 876
 877 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
 878                   ISA_MICROMIPS32R6;
 879 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
 880                   ISA_MICROMIPS32R6;
 881 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
 882                   ISA_MICROMIPS32R6;
 883 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
 884                   ISA_MICROMIPS32R6;
 885 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
 886                   ISA_MICROMIPS32R6;
 887 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
 888                   ISA_MICROMIPS32R6;
 889 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
 890                   ISA_MICROMIPS32R6;
 891 }
 892
 893 //===----------------------------------------------------------------------===//
 894 //
 895 // MicroMips instruction aliases
 896 //
 897 //===----------------------------------------------------------------------===//
 898
 899 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 900 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 901 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
 902                                       !strconcat("b", "\t$offset")> {
 903   string DecoderNamespace = "MicroMipsR6";
 904 }