lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 //
  16 // Instruction Encodings
  17 //
  18 //===----------------------------------------------------------------------===//
  19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  28 class AUI_MMR6_ENC : AUI_FM_MMR6;
  29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  51 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  52 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  53 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  54 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  55 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  56 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  57 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  58 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  59 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  60 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  61 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  62 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  63 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  64 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  65 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  66 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  67 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  68 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  69 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  70 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  71 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  72 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  73 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  74 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  75 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  76 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
  77 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
  78 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  79 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  80 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
  81 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
  82 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
  83 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
  84 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
  85 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
  86 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
  87 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
  88 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
  89 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
  90 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
  91 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
  92 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
  93 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
  94 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
  95 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
  96 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
  97 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
  98 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
  99 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 100 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 101 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 102 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 103 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 104 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 105 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 106 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 107
 108 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 109 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 110 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 111 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 112 class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
 113 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 114 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 115
 116 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 117                                   RegisterOperand GPROpnd>
 118     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 119   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 120   dag OutOperandList = (outs);
 121   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 122   list<Register> Defs = [AT];
 123 }
 124
 125 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 126                                                       GPR32Opnd> {
 127   list<Register> Defs = [RA];
 128 }
 129
 130 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 131                                                       GPR32Opnd> {
 132   list<Register> Defs = [RA];
 133 }
 134
 135 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 136                                                       GPR32Opnd> {
 137   list<Register> Defs = [RA];
 138 }
 139
 140 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 141                                                       GPR32Opnd> {
 142   list<Register> Defs = [RA];
 143 }
 144
 145 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 146                                                       GPR32Opnd> {
 147   list<Register> Defs = [RA];
 148 }
 149
 150 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 151                                                       GPR32Opnd> {
 152   list<Register> Defs = [RA];
 153 }
 154
 155 /// Floating Point Instructions
 156 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 157 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 158 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 159 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 160 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 161 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 162 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 163 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 164 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 165 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 166 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 167 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 168 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 169 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 170 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 171 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 172 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 173 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 174 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 175 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 176 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 177 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 178 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 179 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 180
 181 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 182 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 183 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 184 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 185 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 186 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 187 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 188 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 189 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 190 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 191
 192 //===----------------------------------------------------------------------===//
 193 //
 194 // Instruction Descriptions
 195 //
 196 //===----------------------------------------------------------------------===//
 197
 198 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 199 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 200 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 201 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 202 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 203 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 204 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 205
 206 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 207     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 208   dag InOperandList = (ins opnd:$offset);
 209   dag OutOperandList = (outs);
 210   string AsmString = !strconcat(instr_asm, "\t$offset");
 211   bit isBarrier = 1;
 212 }
 213
 214 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 215   bit isCall = 1;
 216   list<Register> Defs = [RA];
 217 }
 218 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 219
 220 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 221                                        !strconcat("bc16", "\t$offset"), [],
 222                                        II_BC, FrmI>,
 223                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 224   let isBranch = 1;
 225   let isTerminator = 1;
 226   let isBarrier = 1;
 227   let hasDelaySlot = 0;
 228   let AdditionalPredicates = [RelocPIC];
 229   let Defs = [AT];
 230 }
 231
 232 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 233     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 234   let isBranch = 1;
 235   let isTerminator = 1;
 236   let hasDelaySlot = 0;
 237   let Defs = [AT];
 238 }
 239 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 240 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 241
 242 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 243 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 244
 245 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 246     : MMR6Arch<instr_asm> {
 247   dag OutOperandList = (outs GPROpnd:$rd);
 248   dag InOperandList = (ins GPROpnd:$rt);
 249   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 250   list<dag> Pattern = [];
 251 }
 252
 253 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 254
 255 class BRK_MMR6_DESC : BRK_FT<"break">;
 256
 257 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 258                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 259   dag OutOperandList = (outs);
 260   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 261   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 262   list<dag> Pattern = [];
 263   string DecoderMethod = "DecodeCacheOpMM";
 264 }
 265
 266 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 267 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 268
 269 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 270                                   RegisterOperand GPROpnd> :
 271                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 272                                   GPROpnd> {
 273   string DecoderMethod = "DecodePrefeOpMM";
 274 }
 275
 276 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 277 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 278
 279 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 280     : MMR6Arch<instr_asm> {
 281   dag OutOperandList = (outs GPROpnd:$rt);
 282   dag InOperandList = (ins GPROpnd:$rs);
 283   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 284 }
 285
 286 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 287 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 288
 289 class EHB_MMR6_DESC : Barrier<"ehb">;
 290 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 291
 292 class ERET_MMR6_DESC : ER_FT<"eret">;
 293 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 294
 295 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 296                                      RegisterOperand GPROpnd>
 297     : MMR6Arch<opstr> {
 298   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 299   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 300   list<dag> Pattern = [];
 301   bit isTerminator = 1;
 302   bit hasDelaySlot = 0;
 303 }
 304
 305 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 306                                                        GPR32Opnd> {
 307   bit isCall = 1;
 308   list<Register> Defs = [RA];
 309 }
 310
 311 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 312                                                      GPR32Opnd> {
 313   bit isBarrier = 1;
 314   list<Register> Defs = [AT];
 315 }
 316
 317 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 318                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 319   dag OutOperandList = (outs GPROpnd:$rd);
 320   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 321   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 322   list<dag> Pattern = [];
 323 }
 324
 325 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 326
 327 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 328     : MMR6Arch<instr_asm> {
 329   dag OutOperandList = (outs GPROpnd:$rt);
 330   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 331   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 332   list<dag> Pattern = [];
 333 }
 334
 335 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 336
 337 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 338 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 339 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 340     : MMR6Arch<instr_asm> {
 341   dag OutOperandList = (outs GPROpnd:$rt);
 342   dag InOperandList = (ins simm16:$imm);
 343   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 344   list<dag> Pattern = [];
 345 }
 346
 347 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 348 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 349
 350 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 351                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 352   dag OutOperandList = (outs GPROpnd:$rd);
 353   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 354   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 355   list<dag> Pattern = [];
 356 }
 357
 358 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 359
 360 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 361                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 362   dag OutOperandList = (outs GPROpnd:$rt);
 363   dag InOperandList = (ins ImmOpnd:$imm);
 364   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 365   list<dag> Pattern = [];
 366 }
 367
 368 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 369 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 370
 371 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 372     : MMR6Arch<instr_asm> {
 373   dag OutOperandList = (outs GPROpnd:$rd);
 374   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 375   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 376   list<dag> Pattern = [];
 377 }
 378
 379 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 380 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 381 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 382 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 383 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 384 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 385 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 386 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 387 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 388 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 389 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 390 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 391 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 392 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 393
 394 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 395                   SDPatternOperator OpNode = null_frag,
 396                   InstrItinClass Itin = NoItinerary,
 397                   ComplexPattern Addr = addr> :
 398   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 399          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 400   let DecoderMethod = "DecodeMem";
 401   let mayStore = 1;
 402 }
 403 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 404 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 405
 406 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 407     : MMR6Arch<instr_asm> {
 408   dag InOperandList = (ins RO:$rs);
 409   dag OutOperandList = (outs RO:$rt);
 410   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 411   list<dag> Pattern = [];
 412   Format f = FrmR;
 413   string BaseOpcode = instr_asm;
 414   bit hasSideEffects = 0;
 415 }
 416 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 417 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 418
 419 /// Floating Point Instructions
 420 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 421                             InstrItinClass Itin, bit isComm,
 422                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 423   dag OutOperandList = (outs RC:$fd);
 424   dag InOperandList = (ins RC:$ft, RC:$fs);
 425   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 426   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 427   InstrItinClass Itinerary = Itin;
 428   bit isCommutable = isComm;
 429 }
 430 class FADD_S_MMR6_DESC
 431   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 432 class FADD_D_MMR6_DESC
 433   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 434 class FSUB_S_MMR6_DESC
 435   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 436 class FSUB_D_MMR6_DESC
 437   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 438 class FMUL_S_MMR6_DESC
 439   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 440 class FMUL_D_MMR6_DESC
 441   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 442 class FDIV_S_MMR6_DESC
 443   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 444 class FDIV_D_MMR6_DESC
 445   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 446 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 447 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 448 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 449 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 450
 451 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 452                                RegisterOperand SrcRC, InstrItinClass Itin,
 453                                SDPatternOperator OpNode = null_frag>
 454                                : HARDFLOAT, NeverHasSideEffects {
 455   dag OutOperandList = (outs DstRC:$ft);
 456   dag InOperandList = (ins SrcRC:$fs);
 457   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 458   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 459   InstrItinClass Itinerary = Itin;
 460   Format Form = FrmFR;
 461 }
 462 class FMOV_S_MMR6_DESC
 463   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 464 class FMOV_D_MMR6_DESC
 465   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 466 class FNEG_S_MMR6_DESC
 467   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 468 class FNEG_D_MMR6_DESC
 469   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 470
 471 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 472 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 473 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 474 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 475
 476 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 477 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 478 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 479 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 480
 481 class CVT_MMR6_DESC_BASE<
 482     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 483     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 484     : HARDFLOAT, NeverHasSideEffects {
 485   dag OutOperandList = (outs DstRC:$ft);
 486   dag InOperandList = (ins SrcRC:$fs);
 487   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 488   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 489   InstrItinClass Itinerary = Itin;
 490   Format Form = FrmFR;
 491 }
 492
 493 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 494                                              II_CVT>;
 495 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 496                                              II_CVT>;
 497 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 498                                              II_CVT>;
 499 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 500                                              II_CVT>;
 501 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 502                                              II_CVT>;
 503 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 504                                              II_CVT>;
 505 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 506                                              II_CVT>, FGR_64;
 507 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 508                                              II_CVT>;
 509 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 510                                              II_CVT>;
 511 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 512                                              II_CVT>, FGR_64;
 513
 514 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 515                        RegisterOperand FGROpnd> {
 516   def CMP_AF_#NAME : POOL32F_CMP_FM<
 517       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 518       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 519       ISA_MICROMIPS32R6;
 520   def CMP_UN_#NAME : POOL32F_CMP_FM<
 521       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 522       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 523       ISA_MICROMIPS32R6;
 524   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 525       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 526       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 527       ISA_MICROMIPS32R6;
 528   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 529       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 530       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 531       ISA_MICROMIPS32R6;
 532   def CMP_LT_#NAME : POOL32F_CMP_FM<
 533       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 534       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 535       ISA_MICROMIPS32R6;
 536   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 537       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 538       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 539       ISA_MICROMIPS32R6;
 540   def CMP_LE_#NAME : POOL32F_CMP_FM<
 541       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 542       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 543       ISA_MICROMIPS32R6;
 544   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 545       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 546       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 547       ISA_MICROMIPS32R6;
 548   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 549       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 550       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 551       ISA_MICROMIPS32R6;
 552   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 553       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 554       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 555       ISA_MICROMIPS32R6;
 556   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 557       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 558       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 559       ISA_MICROMIPS32R6;
 560   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 561       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 562       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 563       ISA_MICROMIPS32R6;
 564   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 565       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 566       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 567       ISA_MICROMIPS32R6;
 568   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 569       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 570       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 571       ISA_MICROMIPS32R6;
 572   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 573       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 574       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 575       ISA_MICROMIPS32R6;
 576   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 577       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 578       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 579       ISA_MICROMIPS32R6;
 580 }
 581
 582 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 583                              RegisterOperand SrcRC, InstrItinClass Itin,
 584                              SDPatternOperator OpNode = null_frag>
 585     : HARDFLOAT, NeverHasSideEffects {
 586   dag OutOperandList = (outs DstRC:$ft);
 587   dag InOperandList  = (ins SrcRC:$fs);
 588   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 589   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 590   InstrItinClass Itinerary = Itin;
 591   Format Form = FrmFR;
 592   list<Predicate> EncodingPredicates = [HasStdEnc];
 593 }
 594
 595 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 596                                                 II_ABS, fabs>;
 597 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 598                                                 II_ABS, fabs>;
 599 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 600                                                     FGR32Opnd, II_FLOOR>;
 601 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 602                                                     FGR64Opnd, II_FLOOR>;
 603 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 604                                                     FGR32Opnd, II_FLOOR>;
 605 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 606                                                     AFGR64Opnd, II_FLOOR>;
 607 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 608                                                    FGR32Opnd, II_CEIL>;
 609 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 610                                                    FGR64Opnd, II_CEIL>;
 611 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 612                                                    FGR32Opnd, II_CEIL>;
 613 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 614                                                    AFGR64Opnd, II_CEIL>;
 615 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 616                                                     FGR32Opnd, II_TRUNC>;
 617 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 618                                                     FGR64Opnd, II_TRUNC>;
 619 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 620                                                     FGR32Opnd, II_TRUNC>;
 621 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 622                                                     AFGR64Opnd, II_TRUNC>;
 623 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 624                                                  II_SQRT_S, fsqrt>;
 625 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 626                                                  II_SQRT_D, fsqrt>;
 627 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 628                                                   FGR32Opnd, II_TRUNC>;
 629 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 630                                                   AFGR64Opnd, II_TRUNC>;
 631
 632 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 633     : Store<opstr, RO>, MMR6Arch<opstr> {
 634   let DecoderMethod = "DecodeMemMMImm16";
 635 }
 636 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 637
 638 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 639     : MMR6Arch<instr_asm>, MipsR6Inst {
 640   dag OutOperandList = (outs);
 641   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 642   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 643   string DecoderMethod = "DecodeStoreEvaOpMM";
 644   bit mayStore = 1;
 645 }
 646 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 647 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 648 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 649 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 650
 651 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 652             MMR6Arch<instr_asm>, MipsR6Inst {
 653   dag OutOperandList = (outs RO:$rt);
 654   dag InOperandList = (ins mem_mm_12:$addr);
 655   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 656   string DecoderMethod = "DecodeMemMMImm9";
 657   bit mayLoad = 1;
 658 }
 659 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 660 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 661 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 662   MMR6Arch<"addu16">;
 663 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 664   MMR6Arch<"and16">;
 665 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 666   MMR6Arch<"andi16">;
 667 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 668 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 669   MMR6Arch<"or16">;
 670 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 671   MMR6Arch<"sll16">;
 672 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 673   MMR6Arch<"srl16">;
 674
 675 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 676   dag OutOperandList = (outs GPR32Opnd:$rt);
 677   dag InOperandList = (ins mem:$addr);
 678   string AsmString = "lw\t$rt, $addr";
 679   let DecoderMethod = "DecodeMemMMImm16";
 680   let canFoldAsLoad = 1;
 681   let mayLoad = 1;
 682   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 683   InstrItinClass Itinerary = II_LW;
 684 }
 685
 686 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 687   dag OutOperandList = (outs GPR32Opnd:$rt);
 688   dag InOperandList = (ins uimm16:$imm16);
 689   string AsmString = "lui\t$rt, $imm16";
 690   list<dag> Pattern = [];
 691   bit hasSideEffects = 0;
 692   bit isReMaterializable = 1;
 693   InstrItinClass Itinerary = II_LUI;
 694   Format Form = FrmI;
 695 }
 696
 697 //===----------------------------------------------------------------------===//
 698 //
 699 // Instruction Definitions
 700 //
 701 //===----------------------------------------------------------------------===//
 702
 703 let DecoderNamespace = "MicroMipsR6" in {
 704 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 705 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 706 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 707 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 708                    ISA_MICROMIPS32R6;
 709 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 710                   ISA_MICROMIPS32R6;
 711 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 712 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 713 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 714 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 715 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 716 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 717 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 718 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 719 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 720                    ISA_MICROMIPS32R6;
 721 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 722                    ISA_MICROMIPS32R6;
 723 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 724                    ISA_MICROMIPS32R6;
 725 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 726                    ISA_MICROMIPS32R6;
 727 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 728                    ISA_MICROMIPS32R6;
 729 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 730                    ISA_MICROMIPS32R6;
 731 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 732                    ISA_MICROMIPS32R6;
 733 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 734                    ISA_MICROMIPS32R6;
 735 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 736                    ISA_MICROMIPS32R6;
 737 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 738 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 739 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 740 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 741 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 742 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 743 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 744 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 745 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 746 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 747                   ISA_MICROMIPS32R6;
 748 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 749 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 750 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 751 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 752 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 753 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 754 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 755 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 756 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 757 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 758 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 759 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 760 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 761 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 762 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 763 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 764 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 765                   ISA_MICROMIPS32R6;
 766 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 767                   ISA_MICROMIPS32R6;
 768 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 769 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 770 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 771 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
 772 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
 773                   ISA_MICROMIPS32R6;
 774 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
 775                   ISA_MICROMIPS32R6;
 776 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
 777 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 778 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 779 let DecoderMethod = "DecodeMemMMImm16" in {
 780   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 781 }
 782 let DecoderMethod = "DecodeMemMMImm9" in {
 783   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 784 }
 785 /// Floating Point Instructions
 786 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 787                   ISA_MICROMIPS32R6;
 788 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 789                   ISA_MICROMIPS32R6;
 790 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 791                   ISA_MICROMIPS32R6;
 792 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 793                   ISA_MICROMIPS32R6;
 794 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 795                   ISA_MICROMIPS32R6;
 796 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 797                   ISA_MICROMIPS32R6;
 798 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 799                   ISA_MICROMIPS32R6;
 800 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 801                   ISA_MICROMIPS32R6;
 802 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 803                    ISA_MICROMIPS32R6;
 804 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 805                    ISA_MICROMIPS32R6;
 806 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 807                    ISA_MICROMIPS32R6;
 808 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 809                    ISA_MICROMIPS32R6;
 810 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 811                   ISA_MICROMIPS32R6;
 812 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 813                   ISA_MICROMIPS32R6;
 814 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 815                   ISA_MICROMIPS32R6;
 816 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 817                   ISA_MICROMIPS32R6;
 818 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 819 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 820 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 821 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 822 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 823                   ISA_MICROMIPS32R6;
 824 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 825                   ISA_MICROMIPS32R6;
 826 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 827                   ISA_MICROMIPS32R6;
 828 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 829                   ISA_MICROMIPS32R6;
 830 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 831                    ISA_MICROMIPS32R6;
 832 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 833                    ISA_MICROMIPS32R6;
 834 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 835                    ISA_MICROMIPS32R6;
 836 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 837                    ISA_MICROMIPS32R6;
 838 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 839                    ISA_MICROMIPS32R6;
 840 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 841                    ISA_MICROMIPS32R6;
 842 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 843                    ISA_MICROMIPS32R6;
 844 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 845                    ISA_MICROMIPS32R6;
 846 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 847                    ISA_MICROMIPS32R6;
 848 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 849                    ISA_MICROMIPS32R6;
 850 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 851 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 852 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 853 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 854 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
 855                      ISA_MICROMIPS32R6;
 856 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
 857                      ISA_MICROMIPS32R6;
 858 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
 859                      ISA_MICROMIPS32R6;
 860 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
 861                      ISA_MICROMIPS32R6;
 862 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
 863                     ISA_MICROMIPS32R6;
 864 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
 865                     ISA_MICROMIPS32R6;
 866 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
 867                     ISA_MICROMIPS32R6;
 868 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
 869                     ISA_MICROMIPS32R6;
 870 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
 871                      ISA_MICROMIPS32R6;
 872 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
 873                      ISA_MICROMIPS32R6;
 874 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
 875                      ISA_MICROMIPS32R6;
 876 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
 877                      ISA_MICROMIPS32R6;
 878 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
 879                   ISA_MICROMIPS32R6;
 880 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
 881                   ISA_MICROMIPS32R6;
 882 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
 883                    ISA_MICROMIPS32R6;
 884 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
 885                    ISA_MICROMIPS32R6;
 886 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 887 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 888 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 889 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 890 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 891 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
 892 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 893 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 894 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
 895
 896 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
 897                   ISA_MICROMIPS32R6;
 898 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
 899                   ISA_MICROMIPS32R6;
 900 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
 901                   ISA_MICROMIPS32R6;
 902 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
 903                   ISA_MICROMIPS32R6;
 904 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
 905                   ISA_MICROMIPS32R6;
 906 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
 907                   ISA_MICROMIPS32R6;
 908 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
 909                   ISA_MICROMIPS32R6;
 910 }
 911
 912 //===----------------------------------------------------------------------===//
 913 //
 914 // MicroMips instruction aliases
 915 //
 916 //===----------------------------------------------------------------------===//
 917
 918 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 919 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 920 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
 921                                       !strconcat("b", "\t$offset")> {
 922   string DecoderNamespace = "MicroMipsR6";
 923 }