lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 //
  16 // Instruction Encodings
  17 //
  18 //===----------------------------------------------------------------------===//
  19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  28 class AUI_MMR6_ENC : AUI_FM_MMR6;
  29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  51 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
  52 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  53 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  54 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
  55 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
  56 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  57 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  58 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  59 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  60 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  61 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  62 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  63 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  64 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  65 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  66 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  67 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  68 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  69 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  70 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  71 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  72 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  73 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  74 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  75 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  76 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  77 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  78 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  79 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
  80 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
  81 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
  82 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
  83 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
  84 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
  85 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
  86 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
  87 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
  88 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
  89 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
  90 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
  91 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
  92 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
  93 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
  94 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
  95 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
  96 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
  97 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
  98 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
  99 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 100 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 101 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 102 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 103 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 104 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 105 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 106 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 107 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 108 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 109 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 110
 111 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 112 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 113 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 114 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 115 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 116 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 117 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 118 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 119 class LI16_MMR6_ENC : LI_FM_MM16;
 120 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 121 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 122 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 123 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 124
 125 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 126                                   RegisterOperand GPROpnd>
 127     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 128   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 129   dag OutOperandList = (outs);
 130   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 131   list<Register> Defs = [AT];
 132 }
 133
 134 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 135                                                       GPR32Opnd> {
 136   list<Register> Defs = [RA];
 137 }
 138
 139 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 140                                                       GPR32Opnd> {
 141   list<Register> Defs = [RA];
 142 }
 143
 144 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 145                                                       GPR32Opnd> {
 146   list<Register> Defs = [RA];
 147 }
 148
 149 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 150                                                       GPR32Opnd> {
 151   list<Register> Defs = [RA];
 152 }
 153
 154 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 155                                                       GPR32Opnd> {
 156   list<Register> Defs = [RA];
 157 }
 158
 159 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 160                                                       GPR32Opnd> {
 161   list<Register> Defs = [RA];
 162 }
 163
 164 /// Floating Point Instructions
 165 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 166 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 167 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 168 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 169 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 170 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 171 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 172 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 173 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 174 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 175 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 176 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 177 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 178 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 179 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 180 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 181 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 182 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 183 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 184 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 185 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 186 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 187 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 188 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 189
 190 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 191 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 192 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 193 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 194 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 195 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 196 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 197 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 198 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 199 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 200
 201 //===----------------------------------------------------------------------===//
 202 //
 203 // Instruction Descriptions
 204 //
 205 //===----------------------------------------------------------------------===//
 206
 207 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 208 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 209 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 210 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 211 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 212 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 213 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 214
 215 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 216     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 217   dag InOperandList = (ins opnd:$offset);
 218   dag OutOperandList = (outs);
 219   string AsmString = !strconcat(instr_asm, "\t$offset");
 220   bit isBarrier = 1;
 221 }
 222
 223 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 224   bit isCall = 1;
 225   list<Register> Defs = [RA];
 226 }
 227 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 228
 229 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 230                                        !strconcat("bc16", "\t$offset"), [],
 231                                        II_BC, FrmI>,
 232                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 233   let isBranch = 1;
 234   let isTerminator = 1;
 235   let isBarrier = 1;
 236   let hasDelaySlot = 0;
 237   let AdditionalPredicates = [RelocPIC];
 238   let Defs = [AT];
 239 }
 240
 241 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 242     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 243   let isBranch = 1;
 244   let isTerminator = 1;
 245   let hasDelaySlot = 0;
 246   let Defs = [AT];
 247 }
 248 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 249 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 250
 251 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 252 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 253
 254 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 255     : MMR6Arch<instr_asm> {
 256   dag OutOperandList = (outs GPROpnd:$rd);
 257   dag InOperandList = (ins GPROpnd:$rt);
 258   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 259   list<dag> Pattern = [];
 260 }
 261
 262 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 263
 264 class BRK_MMR6_DESC : BRK_FT<"break">;
 265
 266 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 267                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 268   dag OutOperandList = (outs);
 269   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 270   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 271   list<dag> Pattern = [];
 272   string DecoderMethod = "DecodeCacheOpMM";
 273 }
 274
 275 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 276 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 277
 278 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 279                                   RegisterOperand GPROpnd> :
 280                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 281                                   GPROpnd> {
 282   string DecoderMethod = "DecodePrefeOpMM";
 283 }
 284
 285 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 286 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 287
 288 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 289     : MMR6Arch<instr_asm> {
 290   dag OutOperandList = (outs GPROpnd:$rt);
 291   dag InOperandList = (ins GPROpnd:$rs);
 292   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 293 }
 294
 295 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 296 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 297
 298 class EHB_MMR6_DESC : Barrier<"ehb">;
 299 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 300
 301 class ERET_MMR6_DESC : ER_FT<"eret">;
 302 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 303
 304 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 305     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 306                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 307       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 308   let isCall = 1;
 309   let hasDelaySlot = 0;
 310   let Defs = [RA];
 311 }
 312 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 313
 314 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 315                                      RegisterOperand GPROpnd>
 316     : MMR6Arch<opstr> {
 317   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 318   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 319   list<dag> Pattern = [];
 320   bit isTerminator = 1;
 321   bit hasDelaySlot = 0;
 322 }
 323
 324 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 325                                                        GPR32Opnd> {
 326   bit isCall = 1;
 327   list<Register> Defs = [RA];
 328 }
 329
 330 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 331                                                      GPR32Opnd> {
 332   bit isBarrier = 1;
 333   list<Register> Defs = [AT];
 334 }
 335
 336 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 337     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 338                       [], II_JR, FrmR>,
 339       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 340   let hasDelaySlot = 0;
 341   let isBranch = 1;
 342   let isIndirectBranch = 1;
 343 }
 344 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 345
 346 class JRCADDIUSP_MMR6_DESC
 347     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 348                       [], II_JRADDIUSP, FrmR>,
 349       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
 350   let hasDelaySlot = 0;
 351   let isTerminator = 1;
 352   let isBarrier = 1;
 353   let isBranch = 1;
 354   let isIndirectBranch = 1;
 355 }
 356
 357 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 358                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 359   dag OutOperandList = (outs GPROpnd:$rd);
 360   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 361   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 362   list<dag> Pattern = [];
 363 }
 364
 365 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 366
 367 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 368     : MMR6Arch<instr_asm> {
 369   dag OutOperandList = (outs GPROpnd:$rt);
 370   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 371   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 372   list<dag> Pattern = [];
 373 }
 374
 375 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 376
 377 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 378 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 379 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 380     : MMR6Arch<instr_asm> {
 381   dag OutOperandList = (outs GPROpnd:$rt);
 382   dag InOperandList = (ins simm16:$imm);
 383   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 384   list<dag> Pattern = [];
 385 }
 386
 387 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 388 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 389
 390 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 391                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 392   dag OutOperandList = (outs GPROpnd:$rd);
 393   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 394   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 395   list<dag> Pattern = [];
 396 }
 397
 398 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
 399
 400 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 401                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 402   dag OutOperandList = (outs GPROpnd:$rt);
 403   dag InOperandList = (ins ImmOpnd:$imm);
 404   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 405   list<dag> Pattern = [];
 406 }
 407
 408 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 409 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 410
 411 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 412     : MMR6Arch<instr_asm> {
 413   dag OutOperandList = (outs GPROpnd:$rd);
 414   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 415   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 416   list<dag> Pattern = [];
 417 }
 418
 419 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 420 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 421 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 422 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 423 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 424 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 425 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 426 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 427 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 428 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 429 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 430 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 431 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 432 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 433
 434 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 435                   SDPatternOperator OpNode = null_frag,
 436                   InstrItinClass Itin = NoItinerary,
 437                   ComplexPattern Addr = addr> :
 438   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 439          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 440   let DecoderMethod = "DecodeMem";
 441   let mayStore = 1;
 442 }
 443 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 444 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 445
 446 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 447     : MMR6Arch<instr_asm> {
 448   dag InOperandList = (ins RO:$rs);
 449   dag OutOperandList = (outs RO:$rt);
 450   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 451   list<dag> Pattern = [];
 452   Format f = FrmR;
 453   string BaseOpcode = instr_asm;
 454   bit hasSideEffects = 0;
 455 }
 456 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 457 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 458
 459 /// Floating Point Instructions
 460 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 461                             InstrItinClass Itin, bit isComm,
 462                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 463   dag OutOperandList = (outs RC:$fd);
 464   dag InOperandList = (ins RC:$ft, RC:$fs);
 465   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 466   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 467   InstrItinClass Itinerary = Itin;
 468   bit isCommutable = isComm;
 469 }
 470 class FADD_S_MMR6_DESC
 471   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 472 class FADD_D_MMR6_DESC
 473   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 474 class FSUB_S_MMR6_DESC
 475   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 476 class FSUB_D_MMR6_DESC
 477   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 478 class FMUL_S_MMR6_DESC
 479   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 480 class FMUL_D_MMR6_DESC
 481   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 482 class FDIV_S_MMR6_DESC
 483   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 484 class FDIV_D_MMR6_DESC
 485   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 486 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 487 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 488 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 489 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 490
 491 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 492                                RegisterOperand SrcRC, InstrItinClass Itin,
 493                                SDPatternOperator OpNode = null_frag>
 494                                : HARDFLOAT, NeverHasSideEffects {
 495   dag OutOperandList = (outs DstRC:$ft);
 496   dag InOperandList = (ins SrcRC:$fs);
 497   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 498   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 499   InstrItinClass Itinerary = Itin;
 500   Format Form = FrmFR;
 501 }
 502 class FMOV_S_MMR6_DESC
 503   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 504 class FMOV_D_MMR6_DESC
 505   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 506 class FNEG_S_MMR6_DESC
 507   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 508 class FNEG_D_MMR6_DESC
 509   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 510
 511 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 512 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 513 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 514 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 515
 516 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 517 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 518 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 519 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 520
 521 class CVT_MMR6_DESC_BASE<
 522     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 523     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 524     : HARDFLOAT, NeverHasSideEffects {
 525   dag OutOperandList = (outs DstRC:$ft);
 526   dag InOperandList = (ins SrcRC:$fs);
 527   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 528   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 529   InstrItinClass Itinerary = Itin;
 530   Format Form = FrmFR;
 531 }
 532
 533 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 534                                              II_CVT>;
 535 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 536                                              II_CVT>;
 537 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 538                                              II_CVT>;
 539 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 540                                              II_CVT>;
 541 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 542                                              II_CVT>;
 543 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 544                                              II_CVT>;
 545 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 546                                              II_CVT>, FGR_64;
 547 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 548                                              II_CVT>;
 549 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 550                                              II_CVT>;
 551 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 552                                              II_CVT>, FGR_64;
 553
 554 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 555                        RegisterOperand FGROpnd> {
 556   def CMP_AF_#NAME : POOL32F_CMP_FM<
 557       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 558       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 559       ISA_MICROMIPS32R6;
 560   def CMP_UN_#NAME : POOL32F_CMP_FM<
 561       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 562       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 563       ISA_MICROMIPS32R6;
 564   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 565       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 566       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 567       ISA_MICROMIPS32R6;
 568   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 569       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 570       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 571       ISA_MICROMIPS32R6;
 572   def CMP_LT_#NAME : POOL32F_CMP_FM<
 573       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 574       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 575       ISA_MICROMIPS32R6;
 576   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 577       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 578       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 579       ISA_MICROMIPS32R6;
 580   def CMP_LE_#NAME : POOL32F_CMP_FM<
 581       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 582       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 583       ISA_MICROMIPS32R6;
 584   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 585       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 586       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 587       ISA_MICROMIPS32R6;
 588   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 589       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 590       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 591       ISA_MICROMIPS32R6;
 592   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 593       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 594       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 595       ISA_MICROMIPS32R6;
 596   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 597       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 598       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 599       ISA_MICROMIPS32R6;
 600   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 601       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 602       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 603       ISA_MICROMIPS32R6;
 604   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 605       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 606       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 607       ISA_MICROMIPS32R6;
 608   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 609       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 610       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 611       ISA_MICROMIPS32R6;
 612   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 613       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 614       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 615       ISA_MICROMIPS32R6;
 616   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 617       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 618       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 619       ISA_MICROMIPS32R6;
 620 }
 621
 622 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 623                              RegisterOperand SrcRC, InstrItinClass Itin,
 624                              SDPatternOperator OpNode = null_frag>
 625     : HARDFLOAT, NeverHasSideEffects {
 626   dag OutOperandList = (outs DstRC:$ft);
 627   dag InOperandList  = (ins SrcRC:$fs);
 628   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 629   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 630   InstrItinClass Itinerary = Itin;
 631   Format Form = FrmFR;
 632   list<Predicate> EncodingPredicates = [HasStdEnc];
 633 }
 634
 635 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 636                                                 II_ABS, fabs>;
 637 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 638                                                 II_ABS, fabs>;
 639 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 640                                                     FGR32Opnd, II_FLOOR>;
 641 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 642                                                     FGR64Opnd, II_FLOOR>;
 643 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 644                                                     FGR32Opnd, II_FLOOR>;
 645 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 646                                                     AFGR64Opnd, II_FLOOR>;
 647 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 648                                                    FGR32Opnd, II_CEIL>;
 649 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 650                                                    FGR64Opnd, II_CEIL>;
 651 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 652                                                    FGR32Opnd, II_CEIL>;
 653 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 654                                                    AFGR64Opnd, II_CEIL>;
 655 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 656                                                     FGR32Opnd, II_TRUNC>;
 657 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 658                                                     FGR64Opnd, II_TRUNC>;
 659 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 660                                                     FGR32Opnd, II_TRUNC>;
 661 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 662                                                     AFGR64Opnd, II_TRUNC>;
 663 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 664                                                  II_SQRT_S, fsqrt>;
 665 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 666                                                  II_SQRT_D, fsqrt>;
 667 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 668                                                   FGR32Opnd, II_TRUNC>;
 669 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 670                                                   AFGR64Opnd, II_TRUNC>;
 671
 672 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 673     : Store<opstr, RO>, MMR6Arch<opstr> {
 674   let DecoderMethod = "DecodeMemMMImm16";
 675 }
 676 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 677
 678 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 679     : MMR6Arch<instr_asm>, MipsR6Inst {
 680   dag OutOperandList = (outs);
 681   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 682   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 683   string DecoderMethod = "DecodeStoreEvaOpMM";
 684   bit mayStore = 1;
 685 }
 686 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 687 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 688 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 689 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 690 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 691             MMR6Arch<instr_asm>, MipsR6Inst {
 692   dag OutOperandList = (outs RO:$rt);
 693   dag InOperandList = (ins mem_mm_12:$addr);
 694   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 695   string DecoderMethod = "DecodeMemMMImm9";
 696   bit mayLoad = 1;
 697 }
 698 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 699 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 700 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 701       MMR6Arch<"addu16">;
 702 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 703       MMR6Arch<"and16">;
 704 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 705       MMR6Arch<"andi16">;
 706 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 707 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 708       MMR6Arch<"or16">;
 709 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 710       MMR6Arch<"sll16">;
 711 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 712       MMR6Arch<"srl16">;
 713 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
 714       MicroMipsR6Inst16;
 715 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
 716       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
 717 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
 718       MicroMipsR6Inst16;
 719 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
 720       MicroMipsR6Inst16;
 721 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
 722       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 723 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
 724       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 725
 726 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 727   dag OutOperandList = (outs GPR32Opnd:$rt);
 728   dag InOperandList = (ins mem:$addr);
 729   string AsmString = "lw\t$rt, $addr";
 730   let DecoderMethod = "DecodeMemMMImm16";
 731   let canFoldAsLoad = 1;
 732   let mayLoad = 1;
 733   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 734   InstrItinClass Itinerary = II_LW;
 735 }
 736
 737 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 738   dag OutOperandList = (outs GPR32Opnd:$rt);
 739   dag InOperandList = (ins uimm16:$imm16);
 740   string AsmString = "lui\t$rt, $imm16";
 741   list<dag> Pattern = [];
 742   bit hasSideEffects = 0;
 743   bit isReMaterializable = 1;
 744   InstrItinClass Itinerary = II_LUI;
 745   Format Form = FrmI;
 746 }
 747
 748 //===----------------------------------------------------------------------===//
 749 //
 750 // Instruction Definitions
 751 //
 752 //===----------------------------------------------------------------------===//
 753
 754 let DecoderNamespace = "MicroMipsR6" in {
 755 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 756 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 757 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 758 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 759                    ISA_MICROMIPS32R6;
 760 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 761                   ISA_MICROMIPS32R6;
 762 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 763 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 764 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 765 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 766 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 767 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 768 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 769 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 770 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 771                    ISA_MICROMIPS32R6;
 772 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 773                    ISA_MICROMIPS32R6;
 774 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 775                    ISA_MICROMIPS32R6;
 776 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 777                    ISA_MICROMIPS32R6;
 778 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 779                    ISA_MICROMIPS32R6;
 780 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 781                    ISA_MICROMIPS32R6;
 782 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 783                    ISA_MICROMIPS32R6;
 784 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 785                    ISA_MICROMIPS32R6;
 786 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 787                    ISA_MICROMIPS32R6;
 788 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 789 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 790 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 791 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 792 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 793 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 794 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 795 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 796 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 797 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 798                   ISA_MICROMIPS32R6;
 799 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
 800                    ISA_MICROMIPS32R6;
 801 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 802 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 803 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 804 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
 805                       ISA_MICROMIPS32R6;
 806 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 807 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 808 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 809 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 810 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 811 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 812 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 813 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 814 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 815 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 816 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 817 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 818 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 819 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 820 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 821                   ISA_MICROMIPS32R6;
 822 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 823                   ISA_MICROMIPS32R6;
 824 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 825 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 826 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 827 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
 828 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
 829                   ISA_MICROMIPS32R6;
 830 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
 831                   ISA_MICROMIPS32R6;
 832 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
 833 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 834 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 835 let DecoderMethod = "DecodeMemMMImm16" in {
 836   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 837 }
 838 let DecoderMethod = "DecodeMemMMImm9" in {
 839   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 840 }
 841 /// Floating Point Instructions
 842 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 843                   ISA_MICROMIPS32R6;
 844 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 845                   ISA_MICROMIPS32R6;
 846 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 847                   ISA_MICROMIPS32R6;
 848 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 849                   ISA_MICROMIPS32R6;
 850 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 851                   ISA_MICROMIPS32R6;
 852 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 853                   ISA_MICROMIPS32R6;
 854 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 855                   ISA_MICROMIPS32R6;
 856 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 857                   ISA_MICROMIPS32R6;
 858 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 859                    ISA_MICROMIPS32R6;
 860 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
 861                    ISA_MICROMIPS32R6;
 862 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
 863                    ISA_MICROMIPS32R6;
 864 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
 865                    ISA_MICROMIPS32R6;
 866 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
 867                   ISA_MICROMIPS32R6;
 868 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
 869                   ISA_MICROMIPS32R6;
 870 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
 871                   ISA_MICROMIPS32R6;
 872 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
 873                   ISA_MICROMIPS32R6;
 874 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
 875 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
 876 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
 877 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
 878 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
 879                   ISA_MICROMIPS32R6;
 880 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
 881                   ISA_MICROMIPS32R6;
 882 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
 883                   ISA_MICROMIPS32R6;
 884 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
 885                   ISA_MICROMIPS32R6;
 886 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
 887                    ISA_MICROMIPS32R6;
 888 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
 889                    ISA_MICROMIPS32R6;
 890 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
 891                    ISA_MICROMIPS32R6;
 892 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
 893                    ISA_MICROMIPS32R6;
 894 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
 895                    ISA_MICROMIPS32R6;
 896 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
 897                    ISA_MICROMIPS32R6;
 898 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
 899                    ISA_MICROMIPS32R6;
 900 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
 901                    ISA_MICROMIPS32R6;
 902 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
 903                    ISA_MICROMIPS32R6;
 904 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
 905                    ISA_MICROMIPS32R6;
 906 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
 907 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
 908 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 909 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 910 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
 911                      ISA_MICROMIPS32R6;
 912 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
 913                      ISA_MICROMIPS32R6;
 914 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
 915                      ISA_MICROMIPS32R6;
 916 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
 917                      ISA_MICROMIPS32R6;
 918 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
 919                     ISA_MICROMIPS32R6;
 920 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
 921                     ISA_MICROMIPS32R6;
 922 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
 923                     ISA_MICROMIPS32R6;
 924 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
 925                     ISA_MICROMIPS32R6;
 926 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
 927                      ISA_MICROMIPS32R6;
 928 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
 929                      ISA_MICROMIPS32R6;
 930 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
 931                      ISA_MICROMIPS32R6;
 932 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
 933                      ISA_MICROMIPS32R6;
 934 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
 935                   ISA_MICROMIPS32R6;
 936 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
 937                   ISA_MICROMIPS32R6;
 938 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
 939                    ISA_MICROMIPS32R6;
 940 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
 941                    ISA_MICROMIPS32R6;
 942 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 943 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 944 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
 945 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 946 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 947 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
 948 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 949 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 950 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
 951 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
 952                   ISA_MICROMIPS32R6;
 953 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
 954                   ISA_MICROMIPS32R6;
 955 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
 956                   ISA_MICROMIPS32R6;
 957 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
 958                   ISA_MICROMIPS32R6;
 959 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
 960                   ISA_MICROMIPS32R6;
 961 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
 962                   ISA_MICROMIPS32R6;
 963 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
 964                   ISA_MICROMIPS32R6;
 965 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
 966                    ISA_MICROMIPS32R6;
 967 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
 968                 ISA_MICROMIPS32R6;
 969 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
 970                   ISA_MICROMIPS32R6;
 971 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
 972                    ISA_MICROMIPS32R6;
 973 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
 974                   ISA_MICROMIPS32R6;
 975 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
 976                  ISA_MICROMIPS32R6;
 977 }
 978
 979 //===----------------------------------------------------------------------===//
 980 //
 981 // MicroMips instruction aliases
 982 //
 983 //===----------------------------------------------------------------------===//
 984
 985 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 986 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 987 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
 988                                       !strconcat("b", "\t$offset")> {
 989   string DecoderNamespace = "MicroMipsR6";
 990 }