lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 //
  16 // Instruction Encodings
  17 //
  18 //===----------------------------------------------------------------------===//
  19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  28 class AUI_MMR6_ENC : AUI_FM_MMR6;
  29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  51 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
  52 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  53 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  54 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
  55 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
  56 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  57 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  58 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
  59 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  60 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  61 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  62 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  63 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  64 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  65 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  66 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  67 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  68 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  69 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
  70 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  71 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  72 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  73 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  74 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
  75 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  76 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  77 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  78 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  79 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  80 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
  81 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
  82 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
  83 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  84 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  85 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
  86 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
  87 class LB_MMR6_ENC : LB32_FM_MMR6;
  88 class LBU_MMR6_ENC : LBU32_FM_MMR6;
  89 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
  90 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
  91 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
  92 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
  93 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
  94 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
  95 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
  96 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
  97 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
  98 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
  99 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 100 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 101 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 102 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 103 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 104 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 105 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 106 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 107 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 108 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 109 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 110 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 111 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 112 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 113 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 114 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 115 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 116 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 117 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 118 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 119 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 120 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 121 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 122 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 123 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 124 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 125 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 126 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 127 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 128
 129 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 130 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 131 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 132 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 133 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 134 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 135 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 136 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 137 class LI16_MMR6_ENC : LI_FM_MM16;
 138 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 139 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 140 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 141 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 142
 143 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 144                                   RegisterOperand GPROpnd>
 145     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 146   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 147   dag OutOperandList = (outs);
 148   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 149   list<Register> Defs = [AT];
 150 }
 151
 152 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 153                                                       GPR32Opnd> {
 154   list<Register> Defs = [RA];
 155 }
 156
 157 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 158                                                       GPR32Opnd> {
 159   list<Register> Defs = [RA];
 160 }
 161
 162 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 163                                                       GPR32Opnd> {
 164   list<Register> Defs = [RA];
 165 }
 166
 167 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 168                                                       GPR32Opnd> {
 169   list<Register> Defs = [RA];
 170 }
 171
 172 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 173                                                       GPR32Opnd> {
 174   list<Register> Defs = [RA];
 175 }
 176
 177 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 178                                                       GPR32Opnd> {
 179   list<Register> Defs = [RA];
 180 }
 181
 182 /// Floating Point Instructions
 183 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 184 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 185 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 186 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 187 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 188 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 189 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 190 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 191 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 192 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 193 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 194 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 195 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 196 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 197 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 198 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 199 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 200 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 201 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 202 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 203 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 204 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 205 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 206 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 207
 208 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 209 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 210 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 211 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 212 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 213 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 214 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 215 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 216 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 217 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 218
 219 //===----------------------------------------------------------------------===//
 220 //
 221 // Instruction Descriptions
 222 //
 223 //===----------------------------------------------------------------------===//
 224
 225 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 226 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 227 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 228 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 229 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 230 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 231 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 232
 233 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 234     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 235   dag InOperandList = (ins opnd:$offset);
 236   dag OutOperandList = (outs);
 237   string AsmString = !strconcat(instr_asm, "\t$offset");
 238   bit isBarrier = 1;
 239 }
 240
 241 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
 242   bit isCall = 1;
 243   list<Register> Defs = [RA];
 244 }
 245 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
 246
 247 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 248                                        !strconcat("bc16", "\t$offset"), [],
 249                                        II_BC, FrmI>,
 250                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 251   let isBranch = 1;
 252   let isTerminator = 1;
 253   let isBarrier = 1;
 254   let hasDelaySlot = 0;
 255   let AdditionalPredicates = [RelocPIC];
 256   let Defs = [AT];
 257 }
 258
 259 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 260     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 261   let isBranch = 1;
 262   let isTerminator = 1;
 263   let hasDelaySlot = 0;
 264   let Defs = [AT];
 265 }
 266 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 267 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 268
 269 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 270 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 271
 272 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 273     : MMR6Arch<instr_asm> {
 274   dag OutOperandList = (outs GPROpnd:$rd);
 275   dag InOperandList = (ins GPROpnd:$rt);
 276   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 277   list<dag> Pattern = [];
 278 }
 279
 280 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 281
 282 class BRK_MMR6_DESC : BRK_FT<"break">;
 283
 284 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 285                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 286   dag OutOperandList = (outs);
 287   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 288   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 289   list<dag> Pattern = [];
 290   string DecoderMethod = "DecodeCacheOpMM";
 291 }
 292
 293 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 294 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 295
 296 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 297                                   RegisterOperand GPROpnd> :
 298                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 299                                   GPROpnd> {
 300   string DecoderMethod = "DecodePrefeOpMM";
 301 }
 302
 303 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 304 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 305
 306 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 307                             RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 308   dag OutOperandList = (outs GPROpnd:$rt);
 309   dag InOperandList = (ins MemOpnd:$addr);
 310   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 311   string DecoderMethod = "DecodeLoadByte15";
 312   bit mayLoad = 1;
 313 }
 314 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
 315 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
 316
 317 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 318                               RegisterOperand GPROpnd>
 319     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
 320   let DecoderMethod = "DecodeLoadByte9";
 321 }
 322 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
 323 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
 324
 325 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 326     : MMR6Arch<instr_asm> {
 327   dag OutOperandList = (outs GPROpnd:$rt);
 328   dag InOperandList = (ins GPROpnd:$rs);
 329   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 330 }
 331
 332 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 333 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 334
 335 class EHB_MMR6_DESC : Barrier<"ehb">;
 336 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 337
 338 class ERET_MMR6_DESC : ER_FT<"eret">;
 339 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 340
 341 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 342     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 343                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 344       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 345   let isCall = 1;
 346   let hasDelaySlot = 0;
 347   let Defs = [RA];
 348 }
 349 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 350
 351 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 352                                      RegisterOperand GPROpnd>
 353     : MMR6Arch<opstr> {
 354   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 355   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 356   list<dag> Pattern = [];
 357   bit isTerminator = 1;
 358   bit hasDelaySlot = 0;
 359 }
 360
 361 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 362                                                        GPR32Opnd> {
 363   bit isCall = 1;
 364   list<Register> Defs = [RA];
 365 }
 366
 367 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 368                                                      GPR32Opnd> {
 369   bit isBarrier = 1;
 370   list<Register> Defs = [AT];
 371 }
 372
 373 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 374     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 375                       [], II_JR, FrmR>,
 376       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 377   let hasDelaySlot = 0;
 378   let isBranch = 1;
 379   let isIndirectBranch = 1;
 380 }
 381 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 382
 383 class JRCADDIUSP_MMR6_DESC
 384     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 385                       [], II_JRADDIUSP, FrmR>,
 386       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
 387   let hasDelaySlot = 0;
 388   let isTerminator = 1;
 389   let isBarrier = 1;
 390   let isBranch = 1;
 391   let isIndirectBranch = 1;
 392 }
 393
 394 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 395                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 396   dag OutOperandList = (outs GPROpnd:$rd);
 397   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 398   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 399   list<dag> Pattern = [];
 400 }
 401
 402 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 403
 404 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 405     : MMR6Arch<instr_asm> {
 406   dag OutOperandList = (outs GPROpnd:$rt);
 407   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 408   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 409   list<dag> Pattern = [];
 410 }
 411
 412 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 413
 414 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 415 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 416 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 417     : MMR6Arch<instr_asm> {
 418   dag OutOperandList = (outs GPROpnd:$rt);
 419   dag InOperandList = (ins simm16:$imm);
 420   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 421   list<dag> Pattern = [];
 422 }
 423
 424 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 425 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 426
 427 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 428                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 429   dag OutOperandList = (outs GPROpnd:$rd);
 430   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 431   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 432   list<dag> Pattern = [];
 433 }
 434
 435 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
 436
 437 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 438                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 439   dag OutOperandList = (outs GPROpnd:$rt);
 440   dag InOperandList = (ins ImmOpnd:$imm);
 441   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 442   list<dag> Pattern = [];
 443 }
 444
 445 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 446 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 447
 448 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 449     : MMR6Arch<instr_asm> {
 450   dag OutOperandList = (outs GPROpnd:$rd);
 451   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 452   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 453   list<dag> Pattern = [];
 454 }
 455
 456 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 457 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 458 class PAUSE_MMR6_DESC : Barrier<"pause">;
 459 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 460   dag OutOperandList = (outs GPR32Opnd:$rt);
 461   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 462   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 463   list<dag> Pattern = [];
 464   InstrItinClass Itinerary = II_RDHWR;
 465   Format Form = FrmR;
 466 }
 467
 468 class WAIT_MMR6_DESC : WaitMM<"wait">;
 469 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
 470 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 471 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 472 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 473 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 474 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 475 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 476 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 477 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 478 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 479 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 480 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 481 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 482
 483 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 484                   SDPatternOperator OpNode = null_frag,
 485                   InstrItinClass Itin = NoItinerary,
 486                   ComplexPattern Addr = addr> :
 487   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 488          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 489   let DecoderMethod = "DecodeMem";
 490   let mayStore = 1;
 491 }
 492 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 493 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 494
 495 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 496     : MMR6Arch<instr_asm> {
 497   dag InOperandList = (ins RO:$rs);
 498   dag OutOperandList = (outs RO:$rt);
 499   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 500   list<dag> Pattern = [];
 501   Format f = FrmR;
 502   string BaseOpcode = instr_asm;
 503   bit hasSideEffects = 0;
 504 }
 505 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 506 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 507
 508 /// Floating Point Instructions
 509 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 510                             InstrItinClass Itin, bit isComm,
 511                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 512   dag OutOperandList = (outs RC:$fd);
 513   dag InOperandList = (ins RC:$ft, RC:$fs);
 514   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 515   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 516   InstrItinClass Itinerary = Itin;
 517   bit isCommutable = isComm;
 518 }
 519 class FADD_S_MMR6_DESC
 520   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 521 class FADD_D_MMR6_DESC
 522   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 523 class FSUB_S_MMR6_DESC
 524   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 525 class FSUB_D_MMR6_DESC
 526   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 527 class FMUL_S_MMR6_DESC
 528   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 529 class FMUL_D_MMR6_DESC
 530   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 531 class FDIV_S_MMR6_DESC
 532   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 533 class FDIV_D_MMR6_DESC
 534   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 535 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 536 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 537 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 538 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 539
 540 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 541                                RegisterOperand SrcRC, InstrItinClass Itin,
 542                                SDPatternOperator OpNode = null_frag>
 543                                : HARDFLOAT, NeverHasSideEffects {
 544   dag OutOperandList = (outs DstRC:$ft);
 545   dag InOperandList = (ins SrcRC:$fs);
 546   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 547   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 548   InstrItinClass Itinerary = Itin;
 549   Format Form = FrmFR;
 550 }
 551 class FMOV_S_MMR6_DESC
 552   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 553 class FMOV_D_MMR6_DESC
 554   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 555 class FNEG_S_MMR6_DESC
 556   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 557 class FNEG_D_MMR6_DESC
 558   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 559
 560 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 561 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 562 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 563 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 564
 565 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 566 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 567 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 568 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 569
 570 class CVT_MMR6_DESC_BASE<
 571     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 572     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 573     : HARDFLOAT, NeverHasSideEffects {
 574   dag OutOperandList = (outs DstRC:$ft);
 575   dag InOperandList = (ins SrcRC:$fs);
 576   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 577   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 578   InstrItinClass Itinerary = Itin;
 579   Format Form = FrmFR;
 580 }
 581
 582 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 583                                              II_CVT>;
 584 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 585                                              II_CVT>;
 586 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 587                                              II_CVT>;
 588 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 589                                              II_CVT>;
 590 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 591                                              II_CVT>;
 592 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 593                                              II_CVT>;
 594 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 595                                              II_CVT>, FGR_64;
 596 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 597                                              II_CVT>;
 598 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 599                                              II_CVT>;
 600 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 601                                              II_CVT>, FGR_64;
 602
 603 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 604                        RegisterOperand FGROpnd> {
 605   def CMP_AF_#NAME : POOL32F_CMP_FM<
 606       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 607       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 608       ISA_MICROMIPS32R6;
 609   def CMP_UN_#NAME : POOL32F_CMP_FM<
 610       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 611       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 612       ISA_MICROMIPS32R6;
 613   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 614       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 615       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 616       ISA_MICROMIPS32R6;
 617   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 618       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 619       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 620       ISA_MICROMIPS32R6;
 621   def CMP_LT_#NAME : POOL32F_CMP_FM<
 622       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 623       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 624       ISA_MICROMIPS32R6;
 625   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 626       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 627       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 628       ISA_MICROMIPS32R6;
 629   def CMP_LE_#NAME : POOL32F_CMP_FM<
 630       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 631       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 632       ISA_MICROMIPS32R6;
 633   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 634       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 635       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 636       ISA_MICROMIPS32R6;
 637   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 638       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 639       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 640       ISA_MICROMIPS32R6;
 641   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 642       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 643       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 644       ISA_MICROMIPS32R6;
 645   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 646       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 647       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 648       ISA_MICROMIPS32R6;
 649   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 650       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 651       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 652       ISA_MICROMIPS32R6;
 653   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 654       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 655       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 656       ISA_MICROMIPS32R6;
 657   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 658       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 659       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 660       ISA_MICROMIPS32R6;
 661   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 662       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 663       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 664       ISA_MICROMIPS32R6;
 665   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 666       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 667       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 668       ISA_MICROMIPS32R6;
 669 }
 670
 671 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 672                              RegisterOperand SrcRC, InstrItinClass Itin,
 673                              SDPatternOperator OpNode = null_frag>
 674     : HARDFLOAT, NeverHasSideEffects {
 675   dag OutOperandList = (outs DstRC:$ft);
 676   dag InOperandList  = (ins SrcRC:$fs);
 677   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 678   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 679   InstrItinClass Itinerary = Itin;
 680   Format Form = FrmFR;
 681   list<Predicate> EncodingPredicates = [HasStdEnc];
 682 }
 683
 684 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 685                                                 II_ABS, fabs>;
 686 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 687                                                 II_ABS, fabs>;
 688 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 689                                                     FGR32Opnd, II_FLOOR>;
 690 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 691                                                     FGR64Opnd, II_FLOOR>;
 692 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 693                                                     FGR32Opnd, II_FLOOR>;
 694 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 695                                                     AFGR64Opnd, II_FLOOR>;
 696 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 697                                                    FGR32Opnd, II_CEIL>;
 698 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 699                                                    FGR64Opnd, II_CEIL>;
 700 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 701                                                    FGR32Opnd, II_CEIL>;
 702 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 703                                                    AFGR64Opnd, II_CEIL>;
 704 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 705                                                     FGR32Opnd, II_TRUNC>;
 706 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 707                                                     FGR64Opnd, II_TRUNC>;
 708 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 709                                                     FGR32Opnd, II_TRUNC>;
 710 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 711                                                     AFGR64Opnd, II_TRUNC>;
 712 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 713                                                  II_SQRT_S, fsqrt>;
 714 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 715                                                  II_SQRT_D, fsqrt>;
 716 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 717                                                   FGR32Opnd, II_TRUNC>;
 718 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 719                                                   AFGR64Opnd, II_TRUNC>;
 720
 721 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 722     : Store<opstr, RO>, MMR6Arch<opstr> {
 723   let DecoderMethod = "DecodeMemMMImm16";
 724 }
 725 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 726
 727 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 728     : MMR6Arch<instr_asm>, MipsR6Inst {
 729   dag OutOperandList = (outs);
 730   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 731   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 732   string DecoderMethod = "DecodeStoreEvaOpMM";
 733   bit mayStore = 1;
 734 }
 735 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 736 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 737 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 738 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 739 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 740             MMR6Arch<instr_asm>, MipsR6Inst {
 741   dag OutOperandList = (outs RO:$rt);
 742   dag InOperandList = (ins mem_mm_12:$addr);
 743   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 744   string DecoderMethod = "DecodeMemMMImm9";
 745   bit mayLoad = 1;
 746 }
 747 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 748 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 749 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 750       MMR6Arch<"addu16">;
 751 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 752       MMR6Arch<"and16">;
 753 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 754       MMR6Arch<"andi16">;
 755 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 756 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 757       MMR6Arch<"or16">;
 758 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 759       MMR6Arch<"sll16">;
 760 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 761       MMR6Arch<"srl16">;
 762 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
 763       MicroMipsR6Inst16;
 764 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
 765       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
 766 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
 767       MicroMipsR6Inst16;
 768 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
 769       MicroMipsR6Inst16;
 770 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
 771       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 772 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
 773       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 774
 775 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 776   dag OutOperandList = (outs GPR32Opnd:$rt);
 777   dag InOperandList = (ins mem:$addr);
 778   string AsmString = "lw\t$rt, $addr";
 779   let DecoderMethod = "DecodeMemMMImm16";
 780   let canFoldAsLoad = 1;
 781   let mayLoad = 1;
 782   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 783   InstrItinClass Itinerary = II_LW;
 784 }
 785
 786 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 787   dag OutOperandList = (outs GPR32Opnd:$rt);
 788   dag InOperandList = (ins uimm16:$imm16);
 789   string AsmString = "lui\t$rt, $imm16";
 790   list<dag> Pattern = [];
 791   bit hasSideEffects = 0;
 792   bit isReMaterializable = 1;
 793   InstrItinClass Itinerary = II_LUI;
 794   Format Form = FrmI;
 795 }
 796
 797 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
 798   dag OutOperandList = (outs);
 799   dag InOperandList = (ins i32imm:$stype);
 800   string AsmString = !strconcat("sync", "\t$stype");
 801   list<dag> Pattern = [(MipsSync imm:$stype)];
 802   InstrItinClass Itinerary = NoItinerary;
 803   bit HasSideEffects = 1;
 804 }
 805
 806 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
 807   let DecoderMethod = "DecodeSynciR6";
 808 }
 809
 810 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
 811   dag OutOperandList = (outs GPR32Opnd:$rt);
 812   dag InOperandList = (ins GPR32Opnd:$rd);
 813   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
 814 }
 815
 816 class SDBBP_MMR6_DESC : MipsR6Inst {
 817   dag OutOperandList = (outs);
 818   dag InOperandList = (ins uimm20:$code_);
 819   string AsmString = !strconcat("sdbbp", "\t$code_");
 820   list<dag> Pattern = [];
 821 }
 822
 823 class LWM16_MMR6_DESC
 824     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
 825                       !strconcat("lwm16", "\t$rt, $addr"), [],
 826                       NoItinerary, FrmI>,
 827       MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
 828   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 829   let mayLoad = 1;
 830   InstrItinClass Itin = NoItinerary;
 831   ComplexPattern Addr = addr;
 832 }
 833
 834 class SWM16_MMR6_DESC
 835     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
 836                       !strconcat("swm16", "\t$rt, $addr"), [],
 837                       NoItinerary, FrmI>,
 838       MMR6Arch<"swm16">, MicroMipsR6Inst16 {
 839   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 840   let mayStore = 1;
 841   InstrItinClass Itin = NoItinerary;
 842   ComplexPattern Addr = addr;
 843 }
 844
 845 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
 846                           SDPatternOperator OpNode, InstrItinClass Itin,
 847                           Operand MemOpnd>
 848     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
 849                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
 850       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 851   let DecoderMethod = "DecodeMemMMImm4";
 852   let mayStore = 1;
 853 }
 854 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
 855                                            truncstorei8, II_SB, mem_mm_4>;
 856 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
 857                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
 858 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
 859                                            store, II_SW, mem_mm_4_lsl2>;
 860
 861 class SWSP_MMR6_DESC
 862     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
 863                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
 864       MMR6Arch<"sw">, MicroMipsR6Inst16 {
 865   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
 866   let mayStore = 1;
 867 }
 868
 869 //===----------------------------------------------------------------------===//
 870 //
 871 // Instruction Definitions
 872 //
 873 //===----------------------------------------------------------------------===//
 874
 875 let DecoderNamespace = "MicroMipsR6" in {
 876 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 877 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 878 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 879 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 880                    ISA_MICROMIPS32R6;
 881 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 882                   ISA_MICROMIPS32R6;
 883 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 884 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 885 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 886 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 887 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 888 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 889 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 890 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 891 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 892                    ISA_MICROMIPS32R6;
 893 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 894                    ISA_MICROMIPS32R6;
 895 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 896                    ISA_MICROMIPS32R6;
 897 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 898                    ISA_MICROMIPS32R6;
 899 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 900                    ISA_MICROMIPS32R6;
 901 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 902                    ISA_MICROMIPS32R6;
 903 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 904                    ISA_MICROMIPS32R6;
 905 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 906                    ISA_MICROMIPS32R6;
 907 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 908                    ISA_MICROMIPS32R6;
 909 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 910 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 911 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 912 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 913 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 914 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 915 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 916 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 917 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 918 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 919                   ISA_MICROMIPS32R6;
 920 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
 921                    ISA_MICROMIPS32R6;
 922 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 923 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 924 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 925 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
 926                       ISA_MICROMIPS32R6;
 927 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 928 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 929 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
 930 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 931 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 932 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 933 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 934 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 935 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 936 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 937 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 938 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 939 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 940 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
 941 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 942 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 943 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 944                   ISA_MICROMIPS32R6;
 945 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
 946                   ISA_MICROMIPS32R6;
 947 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
 948 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 949 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 950 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 951 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
 952 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
 953 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
 954 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
 955 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
 956                   ISA_MICROMIPS32R6;
 957 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
 958                   ISA_MICROMIPS32R6;
 959 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
 960 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
 961 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
 962 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
 963 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
 964 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
 965 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
 966 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
 967 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
 968 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
 969 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
 970 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
 971                   ISA_MICROMIPS32R6;
 972 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
 973 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 974 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 975 let DecoderMethod = "DecodeMemMMImm16" in {
 976   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
 977 }
 978 let DecoderMethod = "DecodeMemMMImm9" in {
 979   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
 980 }
 981 /// Floating Point Instructions
 982 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
 983                   ISA_MICROMIPS32R6;
 984 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
 985                   ISA_MICROMIPS32R6;
 986 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
 987                   ISA_MICROMIPS32R6;
 988 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
 989                   ISA_MICROMIPS32R6;
 990 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
 991                   ISA_MICROMIPS32R6;
 992 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
 993                   ISA_MICROMIPS32R6;
 994 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
 995                   ISA_MICROMIPS32R6;
 996 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
 997                   ISA_MICROMIPS32R6;
 998 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
 999                    ISA_MICROMIPS32R6;
1000 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1001                    ISA_MICROMIPS32R6;
1002 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1003                    ISA_MICROMIPS32R6;
1004 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1005                    ISA_MICROMIPS32R6;
1006 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1007                   ISA_MICROMIPS32R6;
1008 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1009                   ISA_MICROMIPS32R6;
1010 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1011                   ISA_MICROMIPS32R6;
1012 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1013                   ISA_MICROMIPS32R6;
1014 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1015 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1016 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1017 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1018 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1019                   ISA_MICROMIPS32R6;
1020 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1021                   ISA_MICROMIPS32R6;
1022 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1023                   ISA_MICROMIPS32R6;
1024 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1025                   ISA_MICROMIPS32R6;
1026 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1027                    ISA_MICROMIPS32R6;
1028 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1029                    ISA_MICROMIPS32R6;
1030 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1031                    ISA_MICROMIPS32R6;
1032 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1033                    ISA_MICROMIPS32R6;
1034 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1035                    ISA_MICROMIPS32R6;
1036 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1037                    ISA_MICROMIPS32R6;
1038 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1039                    ISA_MICROMIPS32R6;
1040 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1041                    ISA_MICROMIPS32R6;
1042 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1043                    ISA_MICROMIPS32R6;
1044 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1045                    ISA_MICROMIPS32R6;
1046 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
1047 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
1048 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1049 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1050 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1051                      ISA_MICROMIPS32R6;
1052 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1053                      ISA_MICROMIPS32R6;
1054 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1055                      ISA_MICROMIPS32R6;
1056 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1057                      ISA_MICROMIPS32R6;
1058 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1059                     ISA_MICROMIPS32R6;
1060 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1061                     ISA_MICROMIPS32R6;
1062 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1063                     ISA_MICROMIPS32R6;
1064 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1065                     ISA_MICROMIPS32R6;
1066 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1067                      ISA_MICROMIPS32R6;
1068 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1069                      ISA_MICROMIPS32R6;
1070 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1071                      ISA_MICROMIPS32R6;
1072 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1073                      ISA_MICROMIPS32R6;
1074 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1075                   ISA_MICROMIPS32R6;
1076 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1077                   ISA_MICROMIPS32R6;
1078 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1079                    ISA_MICROMIPS32R6;
1080 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1081                    ISA_MICROMIPS32R6;
1082 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1083 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1084 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1085 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1086 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1087 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1088 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1089 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1090 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1091 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1092                   ISA_MICROMIPS32R6;
1093 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1094                   ISA_MICROMIPS32R6;
1095 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1096                   ISA_MICROMIPS32R6;
1097 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1098                   ISA_MICROMIPS32R6;
1099 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1100                   ISA_MICROMIPS32R6;
1101 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1102                   ISA_MICROMIPS32R6;
1103 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1104                   ISA_MICROMIPS32R6;
1105 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1106                    ISA_MICROMIPS32R6;
1107 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1108                 ISA_MICROMIPS32R6;
1109 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1110                   ISA_MICROMIPS32R6;
1111 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1112                    ISA_MICROMIPS32R6;
1113 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1114                   ISA_MICROMIPS32R6;
1115 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1116                  ISA_MICROMIPS32R6;
1117 }
1118
1119 //===----------------------------------------------------------------------===//
1120 //
1121 // MicroMips instruction aliases
1122 //
1123 //===----------------------------------------------------------------------===//
1124
1125 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1126 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1127 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1128                                       !strconcat("b", "\t$offset")> {
1129   string DecoderNamespace = "MicroMipsR6";
1130 }
1131 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1132 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1133 def : MipsInstAlias<"rdhwr $rt, $rs",
1134                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1135                     ISA_MICROMIPS32R6;
1136
1137 //===----------------------------------------------------------------------===//
1138 //
1139 // MicroMips arbitrary patterns that map to one or more instructions
1140 //
1141 //===----------------------------------------------------------------------===//
1142
1143 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1144               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;