1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 def brtarget26_mm : Operand<OtherVT> {
15 let EncoderMethod = "getBranchTarget26OpValueMM";
16 let OperandType = "OPERAND_PCREL";
17 let DecoderMethod = "DecodeBranchTarget26MM";
18 let ParserMatchClass = MipsJumpTargetAsmOperand;
21 //===----------------------------------------------------------------------===//
23 // Instruction Encodings
25 //===----------------------------------------------------------------------===//
26 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
27 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
28 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
29 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
30 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
31 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
32 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
33 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
34 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
35 class AUI_MMR6_ENC : AUI_FM_MMR6;
36 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
37 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
38 class BC16_MMR6_ENC : BC16_FM_MM16R6;
39 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
40 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
41 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
42 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
43 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
44 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
45 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
46 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
47 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
48 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
49 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
50 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
51 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
52 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
53 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
54 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
55 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
56 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
57 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
58 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
59 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
60 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
61 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
62 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
63 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
64 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
65 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
66 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
67 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
68 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
69 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
70 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
71 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
72 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
73 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
74 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
75 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
76 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
77 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
78 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
79 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
80 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
81 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
82 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
83 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
84 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
85 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
86 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
87 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
88 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
89 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
90 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
91 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
92 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
93 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
94 class LB_MMR6_ENC : LB32_FM_MMR6;
95 class LBU_MMR6_ENC : LBU32_FM_MMR6;
96 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
97 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
98 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
99 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
100 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
101 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
102 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
103 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
104 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
105 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
106 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
107 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
108 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
109 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
110 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
111 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
112 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
113 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
114 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
115 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
116 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
117 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
118 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
119 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
120 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
121 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
122 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
123 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
124 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
125 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
126 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
127 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
128 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
129 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
130 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
131 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
132 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
133 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
134 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
136 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
137 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
138 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
139 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
140 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
141 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
142 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
143 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
144 class LI16_MMR6_ENC : LI_FM_MM16;
145 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
146 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
147 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
148 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
150 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
151 RegisterOperand GPROpnd>
152 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
153 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
154 dag OutOperandList = (outs);
155 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
156 list<Register> Defs = [AT];
159 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
161 list<Register> Defs = [RA];
164 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
166 list<Register> Defs = [RA];
169 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
171 list<Register> Defs = [RA];
174 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
176 list<Register> Defs = [RA];
179 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
181 list<Register> Defs = [RA];
184 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
186 list<Register> Defs = [RA];
189 /// Floating Point Instructions
190 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
191 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
192 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
193 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
194 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
195 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
196 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
197 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
198 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
199 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
200 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
201 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
202 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
203 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
204 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
205 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
206 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
207 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
208 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
209 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
210 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
211 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
212 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
213 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
215 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
216 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
217 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
218 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
219 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
220 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
221 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
222 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
223 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
224 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
226 //===----------------------------------------------------------------------===//
228 // Instruction Descriptions
230 //===----------------------------------------------------------------------===//
232 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
233 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
234 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
235 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
236 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
237 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
238 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
240 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
241 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
242 dag InOperandList = (ins opnd:$offset);
243 dag OutOperandList = (outs);
244 string AsmString = !strconcat(instr_asm, "\t$offset");
248 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
250 list<Register> Defs = [RA];
252 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>;
254 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
255 !strconcat("bc16", "\t$offset"), [],
257 MMR6Arch<"bc16">, MicroMipsR6Inst16 {
259 let isTerminator = 1;
261 let hasDelaySlot = 0;
262 let AdditionalPredicates = [RelocPIC];
266 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
267 : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
269 let isTerminator = 1;
270 let hasDelaySlot = 0;
273 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
274 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
276 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
277 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
279 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
280 : MMR6Arch<instr_asm> {
281 dag OutOperandList = (outs GPROpnd:$rd);
282 dag InOperandList = (ins GPROpnd:$rt);
283 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
284 list<dag> Pattern = [];
287 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
289 class BRK_MMR6_DESC : BRK_FT<"break">;
291 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
292 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
293 dag OutOperandList = (outs);
294 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
295 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
296 list<dag> Pattern = [];
297 string DecoderMethod = "DecodeCacheOpMM";
300 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
301 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
303 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
304 RegisterOperand GPROpnd> :
305 CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
307 string DecoderMethod = "DecodePrefeOpMM";
310 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
311 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
313 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
314 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
315 dag OutOperandList = (outs GPROpnd:$rt);
316 dag InOperandList = (ins MemOpnd:$addr);
317 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
318 string DecoderMethod = "DecodeLoadByte15";
321 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
322 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
324 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
325 RegisterOperand GPROpnd>
326 : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
327 let DecoderMethod = "DecodeLoadByte9";
329 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
330 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
332 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
333 : MMR6Arch<instr_asm> {
334 dag OutOperandList = (outs GPROpnd:$rt);
335 dag InOperandList = (ins GPROpnd:$rs);
336 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
339 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
340 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
342 class EHB_MMR6_DESC : Barrier<"ehb">;
343 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
345 class ERET_MMR6_DESC : ER_FT<"eret">;
346 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
348 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
349 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
350 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
351 MMR6Arch<opstr>, MicroMipsR6Inst16 {
353 let hasDelaySlot = 0;
356 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
358 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
359 RegisterOperand GPROpnd>
361 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
362 string AsmString = !strconcat(opstr, "\t$rt, $offset");
363 list<dag> Pattern = [];
364 bit isTerminator = 1;
365 bit hasDelaySlot = 0;
368 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
371 list<Register> Defs = [RA];
374 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
377 list<Register> Defs = [AT];
380 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
381 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
383 MMR6Arch<opstr>, MicroMipsR6Inst16 {
384 let hasDelaySlot = 0;
386 let isIndirectBranch = 1;
388 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
390 class JRCADDIUSP_MMR6_DESC
391 : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
392 [], II_JRADDIUSP, FrmR>,
393 MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
394 let hasDelaySlot = 0;
395 let isTerminator = 1;
398 let isIndirectBranch = 1;
401 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
402 Operand ImmOpnd> : MMR6Arch<instr_asm> {
403 dag OutOperandList = (outs GPROpnd:$rd);
404 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
405 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
406 list<dag> Pattern = [];
409 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
411 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
412 : MMR6Arch<instr_asm> {
413 dag OutOperandList = (outs GPROpnd:$rt);
414 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
415 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
416 list<dag> Pattern = [];
419 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
421 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
422 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
423 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
424 : MMR6Arch<instr_asm> {
425 dag OutOperandList = (outs GPROpnd:$rt);
426 dag InOperandList = (ins simm16:$imm);
427 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
428 list<dag> Pattern = [];
431 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
432 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
434 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
435 Operand ImmOpnd> : MMR6Arch<instr_asm> {
436 dag OutOperandList = (outs GPROpnd:$rd);
437 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
438 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
439 list<dag> Pattern = [];
442 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
444 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
445 Operand ImmOpnd> : MMR6Arch<instr_asm> {
446 dag OutOperandList = (outs GPROpnd:$rt);
447 dag InOperandList = (ins ImmOpnd:$imm);
448 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
449 list<dag> Pattern = [];
452 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
453 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
455 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
456 : MMR6Arch<instr_asm> {
457 dag OutOperandList = (outs GPROpnd:$rd);
458 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
459 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
460 list<dag> Pattern = [];
463 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
464 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
465 class PAUSE_MMR6_DESC : Barrier<"pause">;
466 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
467 dag OutOperandList = (outs GPR32Opnd:$rt);
468 dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
469 string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
470 list<dag> Pattern = [];
471 InstrItinClass Itinerary = II_RDHWR;
475 class WAIT_MMR6_DESC : WaitMM<"wait">;
476 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
477 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
478 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
479 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
480 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
481 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
482 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
483 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
484 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
485 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
486 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
487 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
488 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
490 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
491 SDPatternOperator OpNode = null_frag,
492 InstrItinClass Itin = NoItinerary,
493 ComplexPattern Addr = addr> :
494 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
495 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
496 let DecoderMethod = "DecodeMem";
499 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
500 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
502 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
503 : MMR6Arch<instr_asm> {
504 dag InOperandList = (ins RO:$rs);
505 dag OutOperandList = (outs RO:$rt);
506 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
507 list<dag> Pattern = [];
509 string BaseOpcode = instr_asm;
510 bit hasSideEffects = 0;
512 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
513 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
515 /// Floating Point Instructions
516 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
517 InstrItinClass Itin, bit isComm,
518 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
519 dag OutOperandList = (outs RC:$fd);
520 dag InOperandList = (ins RC:$ft, RC:$fs);
521 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
522 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
523 InstrItinClass Itinerary = Itin;
524 bit isCommutable = isComm;
526 class FADD_S_MMR6_DESC
527 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
528 class FADD_D_MMR6_DESC
529 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
530 class FSUB_S_MMR6_DESC
531 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
532 class FSUB_D_MMR6_DESC
533 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
534 class FMUL_S_MMR6_DESC
535 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
536 class FMUL_D_MMR6_DESC
537 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
538 class FDIV_S_MMR6_DESC
539 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
540 class FDIV_D_MMR6_DESC
541 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
542 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
543 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
544 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
545 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
547 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
548 RegisterOperand SrcRC, InstrItinClass Itin,
549 SDPatternOperator OpNode = null_frag>
550 : HARDFLOAT, NeverHasSideEffects {
551 dag OutOperandList = (outs DstRC:$ft);
552 dag InOperandList = (ins SrcRC:$fs);
553 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
554 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
555 InstrItinClass Itinerary = Itin;
558 class FMOV_S_MMR6_DESC
559 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
560 class FMOV_D_MMR6_DESC
561 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
562 class FNEG_S_MMR6_DESC
563 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
564 class FNEG_D_MMR6_DESC
565 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
567 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
568 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
569 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
570 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
572 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
573 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
574 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
575 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
577 class CVT_MMR6_DESC_BASE<
578 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
579 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
580 : HARDFLOAT, NeverHasSideEffects {
581 dag OutOperandList = (outs DstRC:$ft);
582 dag InOperandList = (ins SrcRC:$fs);
583 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
584 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
585 InstrItinClass Itinerary = Itin;
589 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
591 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
593 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
595 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
597 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
599 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
601 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
603 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
605 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
607 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
610 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
611 RegisterOperand FGROpnd> {
612 def CMP_AF_#NAME : POOL32F_CMP_FM<
613 !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
614 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
616 def CMP_UN_#NAME : POOL32F_CMP_FM<
617 !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
618 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
620 def CMP_EQ_#NAME : POOL32F_CMP_FM<
621 !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
622 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
624 def CMP_UEQ_#NAME : POOL32F_CMP_FM<
625 !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
626 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
628 def CMP_LT_#NAME : POOL32F_CMP_FM<
629 !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
630 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
632 def CMP_ULT_#NAME : POOL32F_CMP_FM<
633 !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
634 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
636 def CMP_LE_#NAME : POOL32F_CMP_FM<
637 !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
638 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
640 def CMP_ULE_#NAME : POOL32F_CMP_FM<
641 !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
642 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
644 def CMP_SAF_#NAME : POOL32F_CMP_FM<
645 !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
646 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
648 def CMP_SUN_#NAME : POOL32F_CMP_FM<
649 !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
650 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
652 def CMP_SEQ_#NAME : POOL32F_CMP_FM<
653 !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
654 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
656 def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
657 !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
658 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
660 def CMP_SLT_#NAME : POOL32F_CMP_FM<
661 !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
662 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
664 def CMP_SULT_#NAME : POOL32F_CMP_FM<
665 !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
666 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
668 def CMP_SLE_#NAME : POOL32F_CMP_FM<
669 !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
670 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
672 def CMP_SULE_#NAME : POOL32F_CMP_FM<
673 !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
674 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
678 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
679 RegisterOperand SrcRC, InstrItinClass Itin,
680 SDPatternOperator OpNode = null_frag>
681 : HARDFLOAT, NeverHasSideEffects {
682 dag OutOperandList = (outs DstRC:$ft);
683 dag InOperandList = (ins SrcRC:$fs);
684 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
685 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
686 InstrItinClass Itinerary = Itin;
688 list<Predicate> EncodingPredicates = [HasStdEnc];
691 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
693 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
695 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
696 FGR32Opnd, II_FLOOR>;
697 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
698 FGR64Opnd, II_FLOOR>;
699 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
700 FGR32Opnd, II_FLOOR>;
701 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
702 AFGR64Opnd, II_FLOOR>;
703 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
705 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
707 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
709 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
710 AFGR64Opnd, II_CEIL>;
711 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
712 FGR32Opnd, II_TRUNC>;
713 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
714 FGR64Opnd, II_TRUNC>;
715 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
716 FGR32Opnd, II_TRUNC>;
717 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
718 AFGR64Opnd, II_TRUNC>;
719 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
721 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
723 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
724 FGR32Opnd, II_TRUNC>;
725 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
726 AFGR64Opnd, II_TRUNC>;
728 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
729 : Store<opstr, RO>, MMR6Arch<opstr> {
730 let DecoderMethod = "DecodeMemMMImm16";
732 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
734 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
735 : MMR6Arch<instr_asm>, MipsR6Inst {
736 dag OutOperandList = (outs);
737 dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
738 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
739 string DecoderMethod = "DecodeStoreEvaOpMM";
742 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
743 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
744 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
745 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
746 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
747 MMR6Arch<instr_asm>, MipsR6Inst {
748 dag OutOperandList = (outs RO:$rt);
749 dag InOperandList = (ins mem_mm_12:$addr);
750 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
751 string DecoderMethod = "DecodeMemMMImm9";
754 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
755 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
756 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
758 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
760 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
762 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
763 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
765 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
767 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
769 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
771 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
772 MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
773 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
775 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
777 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
778 MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
779 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
780 MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
782 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
783 dag OutOperandList = (outs GPR32Opnd:$rt);
784 dag InOperandList = (ins mem:$addr);
785 string AsmString = "lw\t$rt, $addr";
786 let DecoderMethod = "DecodeMemMMImm16";
787 let canFoldAsLoad = 1;
789 list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
790 InstrItinClass Itinerary = II_LW;
793 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
794 dag OutOperandList = (outs GPR32Opnd:$rt);
795 dag InOperandList = (ins uimm16:$imm16);
796 string AsmString = "lui\t$rt, $imm16";
797 list<dag> Pattern = [];
798 bit hasSideEffects = 0;
799 bit isReMaterializable = 1;
800 InstrItinClass Itinerary = II_LUI;
804 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
805 dag OutOperandList = (outs);
806 dag InOperandList = (ins i32imm:$stype);
807 string AsmString = !strconcat("sync", "\t$stype");
808 list<dag> Pattern = [(MipsSync imm:$stype)];
809 InstrItinClass Itinerary = NoItinerary;
810 bit HasSideEffects = 1;
813 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
814 let DecoderMethod = "DecodeSynciR6";
817 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
818 dag OutOperandList = (outs GPR32Opnd:$rt);
819 dag InOperandList = (ins GPR32Opnd:$rd);
820 string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
823 class SDBBP_MMR6_DESC : MipsR6Inst {
824 dag OutOperandList = (outs);
825 dag InOperandList = (ins uimm20:$code_);
826 string AsmString = !strconcat("sdbbp", "\t$code_");
827 list<dag> Pattern = [];
830 class LWM16_MMR6_DESC
831 : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
832 !strconcat("lwm16", "\t$rt, $addr"), [],
834 MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
835 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
837 InstrItinClass Itin = NoItinerary;
838 ComplexPattern Addr = addr;
841 class SWM16_MMR6_DESC
842 : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
843 !strconcat("swm16", "\t$rt, $addr"), [],
845 MMR6Arch<"swm16">, MicroMipsR6Inst16 {
846 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
848 InstrItinClass Itin = NoItinerary;
849 ComplexPattern Addr = addr;
852 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
853 SDPatternOperator OpNode, InstrItinClass Itin,
855 : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
856 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
857 MMR6Arch<opstr>, MicroMipsR6Inst16 {
858 let DecoderMethod = "DecodeMemMMImm4";
861 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
862 truncstorei8, II_SB, mem_mm_4>;
863 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
864 truncstorei16, II_SH, mem_mm_4_lsl1>;
865 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
866 store, II_SW, mem_mm_4_lsl2>;
869 : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
870 !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
871 MMR6Arch<"sw">, MicroMipsR6Inst16 {
872 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
876 //===----------------------------------------------------------------------===//
878 // Instruction Definitions
880 //===----------------------------------------------------------------------===//
882 let DecoderNamespace = "MicroMipsR6" in {
883 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
884 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
885 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
886 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
888 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
890 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
891 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
892 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
893 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
894 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
895 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
896 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
897 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
898 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
900 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
902 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
904 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
906 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
908 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
910 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
912 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
914 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
916 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
917 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
918 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
919 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
920 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
921 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
922 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
923 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
924 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
925 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
927 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
929 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
930 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
931 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
932 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
934 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
935 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
936 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
937 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
938 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
939 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
940 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
941 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
942 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
943 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
944 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
945 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
946 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
947 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
948 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
949 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
950 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
952 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
954 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
955 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
956 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
957 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
958 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
959 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
960 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
961 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
962 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
964 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
966 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
967 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
968 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
969 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
970 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
971 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
972 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
973 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
974 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
975 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
976 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
977 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
979 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
980 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
981 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
982 let DecoderMethod = "DecodeMemMMImm16" in {
983 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
985 let DecoderMethod = "DecodeMemMMImm9" in {
986 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
988 /// Floating Point Instructions
989 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
991 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
993 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
995 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
997 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
999 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
1001 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1003 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
1005 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1007 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1009 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1011 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1013 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1015 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1017 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1019 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1021 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1022 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1023 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1024 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1025 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1027 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1029 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1031 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1033 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1035 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1037 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1039 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1041 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1043 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1045 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1047 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1049 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1051 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1053 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
1054 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
1055 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1056 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1057 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1059 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1061 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1063 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1065 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1067 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1069 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1071 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1073 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1075 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1077 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1079 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1081 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1083 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1085 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1087 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1089 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1090 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1091 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1092 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1093 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1094 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1095 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1096 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1097 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1098 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1100 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1102 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1104 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1106 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1108 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1110 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1112 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1114 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1116 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1118 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1120 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1122 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1126 //===----------------------------------------------------------------------===//
1128 // MicroMips instruction aliases
1130 //===----------------------------------------------------------------------===//
1132 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1133 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1134 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1135 !strconcat("b", "\t$offset")> {
1136 string DecoderNamespace = "MicroMipsR6";
1138 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1139 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1140 def : MipsInstAlias<"rdhwr $rt, $rs",
1141 (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1144 //===----------------------------------------------------------------------===//
1146 // MicroMips arbitrary patterns that map to one or more instructions
1148 //===----------------------------------------------------------------------===//
1150 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1151 (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;