1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
32 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
33 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
34 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
35 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
36 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
37 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
38 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
39 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
40 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
41 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
42 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
43 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
44 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
45 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
46 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
47 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
48 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
49 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
50 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
51 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
52 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
53 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
54 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
55 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
56 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
57 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
58 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
59 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
60 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
61 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
62 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
63 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
64 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
66 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
67 RegisterOperand GPROpnd>
68 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
69 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
70 dag OutOperandList = (outs);
71 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
72 list<Register> Defs = [AT];
75 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
77 list<Register> Defs = [RA];
80 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
82 list<Register> Defs = [RA];
85 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
87 list<Register> Defs = [RA];
90 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
92 list<Register> Defs = [RA];
95 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
97 list<Register> Defs = [RA];
100 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
102 list<Register> Defs = [RA];
105 //===----------------------------------------------------------------------===//
107 // Instruction Descriptions
109 //===----------------------------------------------------------------------===//
111 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
112 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
113 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
114 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
115 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
116 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
117 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
119 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
120 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
121 dag InOperandList = (ins opnd:$offset);
122 dag OutOperandList = (outs);
123 string AsmString = !strconcat(instr_asm, "\t$offset");
127 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
129 list<Register> Defs = [RA];
131 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
132 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
133 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
135 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
136 : MMR6Arch<instr_asm> {
137 dag OutOperandList = (outs GPROpnd:$rd);
138 dag InOperandList = (ins GPROpnd:$rt);
139 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
140 list<dag> Pattern = [];
143 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
145 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
146 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
147 dag OutOperandList = (outs);
148 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
149 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
150 list<dag> Pattern = [];
151 string DecoderMethod = "DecodeCacheOpMM";
154 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
155 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
157 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
158 : MMR6Arch<instr_asm> {
159 dag OutOperandList = (outs GPROpnd:$rt);
160 dag InOperandList = (ins GPROpnd:$rs);
161 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
164 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
165 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
167 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
168 RegisterOperand GPROpnd>
170 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
171 string AsmString = !strconcat(opstr, "\t$rt, $offset");
172 list<dag> Pattern = [];
173 bit isTerminator = 1;
174 bit hasDelaySlot = 0;
177 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
180 list<Register> Defs = [RA];
183 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
186 list<Register> Defs = [AT];
189 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
190 Operand ImmOpnd> : MMR6Arch<instr_asm> {
191 dag OutOperandList = (outs GPROpnd:$rd);
192 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
193 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
194 list<dag> Pattern = [];
197 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
199 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
200 : MMR6Arch<instr_asm> {
201 dag OutOperandList = (outs GPROpnd:$rt);
202 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
203 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
204 list<dag> Pattern = [];
207 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
209 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
210 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
211 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
212 : MMR6Arch<instr_asm> {
213 dag OutOperandList = (outs GPROpnd:$rt);
214 dag InOperandList = (ins simm16:$imm);
215 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
216 list<dag> Pattern = [];
219 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
220 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
222 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
223 Operand ImmOpnd> : MMR6Arch<instr_asm> {
224 dag OutOperandList = (outs GPROpnd:$rd);
225 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
226 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
227 list<dag> Pattern = [];
230 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
232 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
233 Operand ImmOpnd> : MMR6Arch<instr_asm> {
234 dag OutOperandList = (outs GPROpnd:$rt);
235 dag InOperandList = (ins ImmOpnd:$imm);
236 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
237 list<dag> Pattern = [];
240 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
241 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
243 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
244 : MMR6Arch<instr_asm> {
245 dag OutOperandList = (outs GPROpnd:$rd);
246 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
247 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
248 list<dag> Pattern = [];
251 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
252 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
253 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
254 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
255 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
256 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
257 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
258 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
259 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
260 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
261 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
262 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
263 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
265 //===----------------------------------------------------------------------===//
267 // Instruction Definitions
269 //===----------------------------------------------------------------------===//
271 let DecoderNamespace = "MicroMips32r6" in {
272 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
273 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
274 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
275 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
277 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
279 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
280 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
281 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
282 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
283 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
284 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
285 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
286 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
288 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
290 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
292 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
294 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
296 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
298 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
300 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
301 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
302 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
303 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
304 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
305 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
306 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
307 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
308 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
309 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
310 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
311 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
312 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
313 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
314 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
315 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
316 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
317 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
318 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
319 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
320 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
321 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
323 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
325 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
326 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
327 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
328 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;