1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
50 let Inst{15-10} = 0x11;
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
60 let Inst{15-10} = 0x11;
65 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
71 let Inst{31-26} = 0b000000;
74 let Inst{15-12} = 0b0000;
75 let Inst{11-6} = funct;
76 let Inst{5-0} = 0b111100;
79 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
85 let Inst{31-26} = opgroup;
86 let Inst{25-21} = hint;
87 let Inst{20-16} = addr{20-16};
88 let Inst{15-12} = funct;
89 let Inst{11-0} = addr{11-0};
92 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
100 let Inst{25-21} = rt;
101 let Inst{20-16} = rs;
102 let Inst{15-11} = rd;
104 let Inst{9-0} = funct;
107 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
114 let Inst{31-26} = op;
115 let Inst{25-21} = rt;
116 let Inst{20-16} = rs;
117 let Inst{15-0} = imm16;
120 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
123 bits<5> base = addr{20-16};
124 bits<9> offset = addr{8-0};
128 let Inst{31-26} = op;
129 let Inst{25-21} = hint;
130 let Inst{20-16} = base;
131 let Inst{15-12} = 0b1010;
132 let Inst{11-9} = funct;
133 let Inst{8-0} = offset;
136 class LB32_FM_MMR6 : MipsR6Inst {
139 bits<5> base = addr{20-16};
140 bits<16> offset = addr{15-0};
144 let Inst{31-26} = 0b000111;
145 let Inst{25-21} = rt;
146 let Inst{20-16} = base;
147 let Inst{15-0} = offset;
150 class LBU32_FM_MMR6 : MipsR6Inst {
153 bits<5> base = addr{20-16};
154 bits<16> offset = addr{15-0};
158 let Inst{31-26} = 0b000101;
159 let Inst{25-21} = rt;
160 let Inst{20-16} = base;
161 let Inst{15-0} = offset;
164 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
170 let Inst{31-26} = 0b011000;
171 let Inst{25-21} = rt;
172 let Inst{20-16} = addr{20-16};
173 let Inst{15-12} = 0b0110;
174 let Inst{11-9} = funct;
175 let Inst{8-0} = addr{8-0};
178 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
179 : MMR6Arch<instr_asm> {
185 let Inst{31-26} = 0b000000;
186 let Inst{25-21} = rd;
187 let Inst{20-16} = rt;
188 let Inst{15-6} = funct;
189 let Inst{5-0} = 0b111100;
192 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
198 let Inst{31-26} = 0b011110;
199 let Inst{25-21} = rt;
200 let Inst{20-19} = funct;
201 let Inst{18-0} = imm;
204 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
210 let Inst{31-26} = 0b011110;
211 let Inst{25-21} = rt;
212 let Inst{20-16} = funct;
213 let Inst{15-0} = imm;
216 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
223 let Inst{31-26} = 0b000000;
224 let Inst{25-21} = rt;
225 let Inst{20-16} = rs;
226 let Inst{15-11} = rd;
228 let Inst{9-0} = funct;
231 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
237 let Inst{31-26} = 0b000000;
238 let Inst{25-21} = rt;
239 let Inst{20-16} = rs;
240 let Inst{15-6} = funct;
241 let Inst{5-0} = 0b111100;
244 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
250 let Inst{31-26} = 0b000000;
251 let Inst{25-21} = rs;
252 let Inst{20-16} = 0b00000;
253 let Inst{15-11} = rt;
254 let Inst{10-6} = 0b00001;
255 let Inst{5-0} = funct;
258 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
266 let Inst{31-26} = 0b000000;
267 let Inst{25-21} = rs;
268 let Inst{20-16} = rt;
269 let Inst{15-11} = rd;
271 let Inst{8-6} = 0b000;
272 let Inst{5-0} = funct;
275 class AUI_FM_MMR6 : MipsR6Inst {
282 let Inst{31-26} = 0b000100;
283 let Inst{25-21} = rt;
284 let Inst{20-16} = rs;
285 let Inst{15-0} = imm;
288 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
296 let Inst{31-26} = 0b000000;
297 let Inst{25-21} = rt;
298 let Inst{20-16} = rs;
299 let Inst{15-11} = rd;
300 let Inst{10-9} = imm2;
301 let Inst{8-6} = 0b000;
302 let Inst{5-0} = funct;
305 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
308 bits<5> base = addr{20-16};
309 bits<16> offset = addr{15-0};
313 let Inst{31-26} = op;
314 let Inst{25-21} = rt;
315 let Inst{20-16} = base;
316 let Inst{15-0} = offset;
319 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
322 bits<5> base = addr{20-16};
323 bits<9> offset = addr{8-0};
327 let Inst{31-26} = 0b011000;
328 let Inst{25-21} = rt;
329 let Inst{20-16} = base;
330 let Inst{15-12} = 0b1010;
331 let Inst{11-9} = funct;
332 let Inst{8-0} = offset;
335 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
338 bits<5> base = addr{20-16};
339 bits<9> offset = addr{8-0};
343 let Inst{31-26} = 0b011000;
344 let Inst{25-21} = rt;
345 let Inst{20-16} = base;
346 let Inst{15-12} = 0b0110;
347 let Inst{11-9} = funct;
348 let Inst{8-0} = offset;
351 class LOAD_WORD_FM_MMR6 {
354 bits<5> base = addr{20-16};
355 bits<16> offset = addr{15-0};
359 let Inst{31-26} = 0b111111;
360 let Inst{25-21} = rt;
361 let Inst{20-16} = base;
362 let Inst{15-0} = offset;
365 class LOAD_UPPER_IMM_FM_MMR6 {
371 let Inst{31-26} = 0b000100;
372 let Inst{25-21} = rt;
374 let Inst{15-0} = imm16;
377 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
383 let Inst{31-26} = funct;
384 let Inst{25-21} = rt;
385 let Inst{20-16} = 0b00000;
386 let Inst{15-0} = offset;
389 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
395 let Inst{31-26} = funct;
396 let Inst{25-21} = rt;
397 let Inst{20-16} = rt;
398 let Inst{15-0} = offset;
401 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
404 let Inst{31-26} = 0x00;
405 let Inst{25-16} = 0x00;
406 let Inst{15-6} = 0x3cd;
407 let Inst{5-0} = 0x3c;
410 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
413 let Inst{31-26} = 0x00;
414 let Inst{25-17} = 0x00;
415 let Inst{16-16} = 0x01;
416 let Inst{15-6} = 0x3cd;
417 let Inst{5-0} = 0x3c;
420 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
424 let Inst{31-26} = 0x0;
425 let Inst{25-16} = code_1;
426 let Inst{15-6} = code_2;
427 let Inst{5-0} = 0x07;
430 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
433 let Inst{31-26} = 0x0;
434 let Inst{25-21} = 0x0;
435 let Inst{20-16} = 0x0;
436 let Inst{15-11} = op;
437 let Inst{10-6} = 0x0;
441 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
443 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
445 let Inst{31-26} = 0x00;
446 let Inst{25-21} = 0x00;
447 let Inst{20-16} = rt;
448 let Inst{15-6} = funct;
449 let Inst{5-0} = 0x3c;
452 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
460 let Inst{25-21} = rd;
461 let Inst{20-16} = rt;
462 let Inst{15-11} = shamt;
463 let Inst{10} = rotate;
464 let Inst{9-0} = funct;
467 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
473 let Inst{31-26} = op;
474 let Inst{25-21} = rt;
475 let Inst{20-16} = addr{20-16};
476 let Inst{15-0} = addr{15-0};
479 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
480 bits<3> funct> : MMR6Arch<instr_asm> {
483 bits<5> base = addr{20-16};
484 bits<9> offset = addr{8-0};
488 let Inst{31-26} = op;
489 let Inst{25-21} = rt;
490 let Inst{20-16} = base;
491 let Inst{15-12} = fmt;
492 let Inst{11-9} = funct;
493 let Inst{8-0} = offset;
496 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
497 : MMR6Arch<instr_asm>, MipsR6Inst {
504 let Inst{31-26} = 0b010101;
505 let Inst{25-21} = ft;
506 let Inst{20-16} = fs;
507 let Inst{15-11} = fd;
510 let Inst{7-0} = funct;
513 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
514 : MMR6Arch<instr_asm>, MipsR6Inst {
521 let Inst{31-26} = 0b010101;
522 let Inst{25-21} = ft;
523 let Inst{20-16} = fs;
524 let Inst{15-11} = fd;
525 let Inst{10-9} = fmt;
526 let Inst{8-0} = funct;
529 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
530 : MMR6Arch<instr_asm>, MipsR6Inst {
536 let Inst{31-26} = 0b010101;
537 let Inst{25-21} = ft;
538 let Inst{20-16} = fs;
540 let Inst{14-13} = fmt;
541 let Inst{12-6} = funct;
542 let Inst{5-0} = 0b111011;
545 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
546 : MMR6Arch<instr_asm>, MipsR6Inst {
553 let Inst{31-26} = 0b010101;
554 let Inst{25-21} = ft;
555 let Inst{20-16} = fs;
556 let Inst{15-11} = fd;
557 let Inst{10-9} = fmt;
558 let Inst{8-0} = funct;
561 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
562 : MMR6Arch<instr_asm>, MipsR6Inst {
569 let Inst{31-26} = 0b010101;
570 let Inst{25-21} = ft;
571 let Inst{20-16} = fs;
572 let Inst{15-11} = fd;
573 let Inst{10-6} = Cond.Value;
574 let Inst{5-0} = format;
577 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
578 : MMR6Arch<instr_asm>, MipsR6Inst {
583 let Inst{31-26} = 0b010101;
584 let Inst{25-21} = ft;
585 let Inst{20-16} = fs;
588 let Inst{13-6} = funct;
589 let Inst{5-0} = 0b111011;
592 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
593 : MMR6Arch<instr_asm>, MipsR6Inst {
598 let Inst{31-26} = 0b010101;
599 let Inst{25-21} = ft;
600 let Inst{20-16} = fs;
602 let Inst{14-13} = fmt;
603 let Inst{12-6} = funct;
604 let Inst{5-0} = 0b111011;
607 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
608 : MMR6Arch<instr_asm>, MipsR6Inst {
614 let Inst{31-26} = 0b010101;
615 let Inst{25-21} = ft;
616 let Inst{20-16} = fs;
618 let Inst{14-13} = fmt;
619 let Inst{12-6} = funct;
620 let Inst{5-0} = 0b111011;
623 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
624 : MMR6Arch<instr_asm>, MipsR6Inst {
630 let Inst{31-26} = 0b010101;
631 let Inst{25-21} = ft;
632 let Inst{20-16} = fs;
635 let Inst{13-6} = funct;
636 let Inst{5-0} = 0b111011;
639 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
646 let Inst{15-10} = 0b000001;
653 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
659 let Inst{15-10} = 0b010001;
662 let Inst{3-0} = 0b0001;
665 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
671 let Inst{15-10} = 0x11;
674 let Inst{3-0} = 0b0000;
677 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
683 let Inst{15-10} = 0b010001;
689 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
693 let Inst{15-10} = 0b010001;
694 let Inst{9-6} = code_;
698 class POOL16A_SUBU16_FM_MMR6 {
705 let Inst{15-10} = 0b000001;
712 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
718 let Inst{31-26} = 0x00;
719 let Inst{25-21} = rt;
720 let Inst{20-16} = rs;
721 let Inst{15-6} = funct;
722 let Inst{5-0} = 0x3c;