1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
50 let Inst{15-10} = 0x11;
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
60 let Inst{15-10} = 0x11;
65 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
71 let Inst{15-10} = 0x11;
74 let Inst{3-0} = funct;
77 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
83 let Inst{31-26} = 0b000000;
86 let Inst{15-12} = 0b0000;
87 let Inst{11-6} = funct;
88 let Inst{5-0} = 0b111100;
91 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
97 let Inst{31-26} = opgroup;
98 let Inst{25-21} = hint;
99 let Inst{20-16} = addr{20-16};
100 let Inst{15-12} = funct;
101 let Inst{11-0} = addr{11-0};
104 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
112 let Inst{25-21} = rt;
113 let Inst{20-16} = rs;
114 let Inst{15-11} = rd;
116 let Inst{9-0} = funct;
119 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
126 let Inst{31-26} = op;
127 let Inst{25-21} = rt;
128 let Inst{20-16} = rs;
129 let Inst{15-0} = imm16;
132 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
135 bits<5> base = addr{20-16};
136 bits<9> offset = addr{8-0};
140 let Inst{31-26} = op;
141 let Inst{25-21} = hint;
142 let Inst{20-16} = base;
143 let Inst{15-12} = 0b1010;
144 let Inst{11-9} = funct;
145 let Inst{8-0} = offset;
148 class LB32_FM_MMR6 : MipsR6Inst {
151 bits<5> base = addr{20-16};
152 bits<16> offset = addr{15-0};
156 let Inst{31-26} = 0b000111;
157 let Inst{25-21} = rt;
158 let Inst{20-16} = base;
159 let Inst{15-0} = offset;
162 class LBU32_FM_MMR6 : MipsR6Inst {
165 bits<5> base = addr{20-16};
166 bits<16> offset = addr{15-0};
170 let Inst{31-26} = 0b000101;
171 let Inst{25-21} = rt;
172 let Inst{20-16} = base;
173 let Inst{15-0} = offset;
176 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
182 let Inst{31-26} = 0b011000;
183 let Inst{25-21} = rt;
184 let Inst{20-16} = addr{20-16};
185 let Inst{15-12} = 0b0110;
186 let Inst{11-9} = funct;
187 let Inst{8-0} = addr{8-0};
190 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
191 : MMR6Arch<instr_asm> {
197 let Inst{31-26} = 0b000000;
198 let Inst{25-21} = rd;
199 let Inst{20-16} = rt;
200 let Inst{15-6} = funct;
201 let Inst{5-0} = 0b111100;
204 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
210 let Inst{31-26} = 0b011110;
211 let Inst{25-21} = rt;
212 let Inst{20-19} = funct;
213 let Inst{18-0} = imm;
216 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
222 let Inst{31-26} = 0b011110;
223 let Inst{25-21} = rt;
224 let Inst{20-16} = funct;
225 let Inst{15-0} = imm;
228 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
235 let Inst{31-26} = 0b000000;
236 let Inst{25-21} = rt;
237 let Inst{20-16} = rs;
238 let Inst{15-11} = rd;
240 let Inst{9-0} = funct;
243 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
249 let Inst{15-11} = op;
254 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
260 let Inst{25-21} = rt;
261 let Inst{20-16} = rd;
262 let Inst{15-6} = funct;
263 let Inst{5-0} = 0b111100;
266 class POOL32A_RDHWR_FM_MMR6 {
273 let Inst{25-21} = rt;
274 let Inst{20-16} = rs;
276 let Inst{13-11} = sel;
278 let Inst{9-0} = 0b0111000000;
281 class POOL32A_SYNC_FM_MMR6 {
288 let Inst{20-16} = stype;
289 let Inst{15-6} = 0b0110101101;
290 let Inst{5-0} = 0b111100;
293 class POOL32I_SYNCI_FM_MMR6 {
295 bits<5> base = addr{20-16};
296 bits<16> immediate = addr{15-0};
300 let Inst{31-26} = 0b010000;
301 let Inst{25-21} = 0b01100;
302 let Inst{20-16} = base;
303 let Inst{15-0} = immediate;
306 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
312 let Inst{31-26} = 0b000000;
313 let Inst{25-21} = rt;
314 let Inst{20-16} = rs;
315 let Inst{15-6} = funct;
316 let Inst{5-0} = 0b111100;
319 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
325 let Inst{31-26} = 0b000000;
326 let Inst{25-21} = rs;
327 let Inst{20-16} = 0b00000;
328 let Inst{15-11} = rt;
329 let Inst{10-6} = 0b00001;
330 let Inst{5-0} = funct;
333 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
341 let Inst{31-26} = 0b000000;
342 let Inst{25-21} = rs;
343 let Inst{20-16} = rt;
344 let Inst{15-11} = rd;
346 let Inst{8-6} = 0b000;
347 let Inst{5-0} = funct;
350 class AUI_FM_MMR6 : MipsR6Inst {
357 let Inst{31-26} = 0b000100;
358 let Inst{25-21} = rt;
359 let Inst{20-16} = rs;
360 let Inst{15-0} = imm;
363 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
371 let Inst{31-26} = 0b000000;
372 let Inst{25-21} = rt;
373 let Inst{20-16} = rs;
374 let Inst{15-11} = rd;
375 let Inst{10-9} = imm2;
376 let Inst{8-6} = 0b000;
377 let Inst{5-0} = funct;
380 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
383 bits<5> base = addr{20-16};
384 bits<16> offset = addr{15-0};
388 let Inst{31-26} = op;
389 let Inst{25-21} = rt;
390 let Inst{20-16} = base;
391 let Inst{15-0} = offset;
394 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
397 bits<5> base = addr{20-16};
398 bits<9> offset = addr{8-0};
402 let Inst{31-26} = 0b011000;
403 let Inst{25-21} = rt;
404 let Inst{20-16} = base;
405 let Inst{15-12} = 0b1010;
406 let Inst{11-9} = funct;
407 let Inst{8-0} = offset;
410 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
413 bits<5> base = addr{20-16};
414 bits<9> offset = addr{8-0};
418 let Inst{31-26} = 0b011000;
419 let Inst{25-21} = rt;
420 let Inst{20-16} = base;
421 let Inst{15-12} = 0b0110;
422 let Inst{11-9} = funct;
423 let Inst{8-0} = offset;
426 class LOAD_WORD_FM_MMR6 {
429 bits<5> base = addr{20-16};
430 bits<16> offset = addr{15-0};
434 let Inst{31-26} = 0b111111;
435 let Inst{25-21} = rt;
436 let Inst{20-16} = base;
437 let Inst{15-0} = offset;
440 class LOAD_UPPER_IMM_FM_MMR6 {
446 let Inst{31-26} = 0b000100;
447 let Inst{25-21} = rt;
449 let Inst{15-0} = imm16;
452 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
458 let Inst{31-26} = funct;
459 let Inst{25-21} = rt;
460 let Inst{20-16} = 0b00000;
461 let Inst{15-0} = offset;
464 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
470 let Inst{31-26} = funct;
471 let Inst{25-21} = rt;
472 let Inst{20-16} = rt;
473 let Inst{15-0} = offset;
476 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
479 let Inst{31-26} = 0x00;
480 let Inst{25-16} = 0x00;
481 let Inst{15-6} = 0x3cd;
482 let Inst{5-0} = 0x3c;
485 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
488 let Inst{31-26} = 0x00;
489 let Inst{25-17} = 0x00;
490 let Inst{16-16} = 0x01;
491 let Inst{15-6} = 0x3cd;
492 let Inst{5-0} = 0x3c;
495 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
499 let Inst{31-26} = 0x0;
500 let Inst{25-16} = code_1;
501 let Inst{15-6} = code_2;
502 let Inst{5-0} = 0x07;
505 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
508 let Inst{31-26} = 0x0;
509 let Inst{25-21} = 0x0;
510 let Inst{20-16} = 0x0;
511 let Inst{15-11} = op;
512 let Inst{10-6} = 0x0;
516 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
518 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
520 let Inst{31-26} = 0x00;
521 let Inst{25-21} = 0x00;
522 let Inst{20-16} = rt;
523 let Inst{15-6} = funct;
524 let Inst{5-0} = 0x3c;
527 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
535 let Inst{25-21} = rd;
536 let Inst{20-16} = rt;
537 let Inst{15-11} = shamt;
538 let Inst{10} = rotate;
539 let Inst{9-0} = funct;
542 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
548 let Inst{31-26} = op;
549 let Inst{25-21} = rt;
550 let Inst{20-16} = addr{20-16};
551 let Inst{15-0} = addr{15-0};
554 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
555 bits<3> funct> : MMR6Arch<instr_asm> {
558 bits<5> base = addr{20-16};
559 bits<9> offset = addr{8-0};
563 let Inst{31-26} = op;
564 let Inst{25-21} = rt;
565 let Inst{20-16} = base;
566 let Inst{15-12} = fmt;
567 let Inst{11-9} = funct;
568 let Inst{8-0} = offset;
571 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
572 : MMR6Arch<instr_asm>, MipsR6Inst {
579 let Inst{31-26} = 0b010101;
580 let Inst{25-21} = ft;
581 let Inst{20-16} = fs;
582 let Inst{15-11} = fd;
585 let Inst{7-0} = funct;
588 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
589 : MMR6Arch<instr_asm>, MipsR6Inst {
596 let Inst{31-26} = 0b010101;
597 let Inst{25-21} = ft;
598 let Inst{20-16} = fs;
599 let Inst{15-11} = fd;
600 let Inst{10-9} = fmt;
601 let Inst{8-0} = funct;
604 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
605 : MMR6Arch<instr_asm>, MipsR6Inst {
611 let Inst{31-26} = 0b010101;
612 let Inst{25-21} = ft;
613 let Inst{20-16} = fs;
615 let Inst{14-13} = fmt;
616 let Inst{12-6} = funct;
617 let Inst{5-0} = 0b111011;
620 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
621 : MMR6Arch<instr_asm>, MipsR6Inst {
628 let Inst{31-26} = 0b010101;
629 let Inst{25-21} = ft;
630 let Inst{20-16} = fs;
631 let Inst{15-11} = fd;
632 let Inst{10-9} = fmt;
633 let Inst{8-0} = funct;
636 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
637 : MMR6Arch<instr_asm>, MipsR6Inst {
644 let Inst{31-26} = 0b010101;
645 let Inst{25-21} = ft;
646 let Inst{20-16} = fs;
647 let Inst{15-11} = fd;
648 let Inst{10-6} = Cond.Value;
649 let Inst{5-0} = format;
652 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
653 : MMR6Arch<instr_asm>, MipsR6Inst {
658 let Inst{31-26} = 0b010101;
659 let Inst{25-21} = ft;
660 let Inst{20-16} = fs;
663 let Inst{13-6} = funct;
664 let Inst{5-0} = 0b111011;
667 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
668 : MMR6Arch<instr_asm>, MipsR6Inst {
673 let Inst{31-26} = 0b010101;
674 let Inst{25-21} = ft;
675 let Inst{20-16} = fs;
677 let Inst{14-13} = fmt;
678 let Inst{12-6} = funct;
679 let Inst{5-0} = 0b111011;
682 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
683 : MMR6Arch<instr_asm>, MipsR6Inst {
689 let Inst{31-26} = 0b010101;
690 let Inst{25-21} = ft;
691 let Inst{20-16} = fs;
693 let Inst{14-13} = fmt;
694 let Inst{12-6} = funct;
695 let Inst{5-0} = 0b111011;
698 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
699 : MMR6Arch<instr_asm>, MipsR6Inst {
705 let Inst{31-26} = 0b010101;
706 let Inst{25-21} = ft;
707 let Inst{20-16} = fs;
710 let Inst{13-6} = funct;
711 let Inst{5-0} = 0b111011;
714 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
721 let Inst{15-10} = 0b000001;
728 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
734 let Inst{15-10} = 0b010001;
737 let Inst{3-0} = 0b0001;
740 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
746 let Inst{15-10} = 0x11;
749 let Inst{3-0} = 0b0000;
752 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
758 let Inst{15-10} = 0b010001;
764 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
768 let Inst{15-10} = 0b010001;
769 let Inst{9-6} = code_;
773 class POOL16A_SUBU16_FM_MMR6 {
780 let Inst{15-10} = 0b000001;
787 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
793 let Inst{31-26} = 0x00;
794 let Inst{25-21} = rt;
795 let Inst{20-16} = rs;
796 let Inst{15-6} = funct;
797 let Inst{5-0} = 0x3c;