1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
25 let Inst{31-26} = 0b000000;
28 let Inst{15-12} = 0b0000;
29 let Inst{11-6} = funct;
30 let Inst{5-0} = 0b111100;
33 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
39 let Inst{31-26} = opgroup;
40 let Inst{25-21} = hint;
41 let Inst{20-16} = addr{20-16};
42 let Inst{15-12} = funct;
43 let Inst{11-0} = addr{11-0};
46 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
58 let Inst{9-0} = funct;
61 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
71 let Inst{15-0} = imm16;
74 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
75 : MMR6Arch<instr_asm> {
81 let Inst{31-26} = 0b000000;
84 let Inst{15-6} = funct;
85 let Inst{5-0} = 0b111100;
88 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
94 let Inst{31-26} = 0b011110;
96 let Inst{20-19} = funct;
100 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
106 let Inst{31-26} = 0b011110;
107 let Inst{25-21} = rt;
108 let Inst{20-16} = funct;
109 let Inst{15-0} = imm;
112 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
119 let Inst{31-26} = 0b000000;
120 let Inst{25-21} = rt;
121 let Inst{20-16} = rs;
122 let Inst{15-11} = rd;
124 let Inst{9-0} = funct;
127 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
133 let Inst{31-26} = 0b000000;
134 let Inst{25-21} = rt;
135 let Inst{20-16} = rs;
136 let Inst{15-6} = funct;
137 let Inst{5-0} = 0b111100;
140 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
146 let Inst{31-26} = 0b000000;
147 let Inst{25-21} = rs;
148 let Inst{20-16} = 0b00000;
149 let Inst{15-11} = rt;
150 let Inst{10-6} = 0b00001;
151 let Inst{5-0} = funct;
154 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
162 let Inst{31-26} = 0b000000;
163 let Inst{25-21} = rs;
164 let Inst{20-16} = rt;
165 let Inst{15-11} = rd;
167 let Inst{8-6} = 0b000;
168 let Inst{5-0} = funct;
171 class AUI_FM_MMR6 : MipsR6Inst {
178 let Inst{31-26} = 0b000100;
179 let Inst{25-21} = rt;
180 let Inst{20-16} = rs;
181 let Inst{15-0} = imm;
184 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
192 let Inst{31-26} = 0b000000;
193 let Inst{25-21} = rt;
194 let Inst{20-16} = rs;
195 let Inst{15-11} = rd;
196 let Inst{10-9} = imm2;
197 let Inst{8-6} = 0b000;
198 let Inst{5-0} = funct;
201 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
207 let Inst{31-26} = funct;
208 let Inst{25-21} = rt;
209 let Inst{20-16} = 0b00000;
210 let Inst{15-0} = offset;
213 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
219 let Inst{31-26} = funct;
220 let Inst{25-21} = rt;
221 let Inst{20-16} = rt;
222 let Inst{15-0} = offset;
225 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
228 let Inst{31-26} = 0x00;
229 let Inst{25-16} = 0x00;
230 let Inst{15-6} = 0x3cd;
231 let Inst{5-0} = 0x3c;
234 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
237 let Inst{31-26} = 0x00;
238 let Inst{25-17} = 0x00;
239 let Inst{16-16} = 0x01;
240 let Inst{15-6} = 0x3cd;
241 let Inst{5-0} = 0x3c;
244 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
248 let Inst{31-26} = 0x0;
249 let Inst{25-16} = code_1;
250 let Inst{15-6} = code_2;
251 let Inst{5-0} = 0x07;
254 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
257 let Inst{31-26} = 0x0;
258 let Inst{25-21} = 0x0;
259 let Inst{20-16} = 0x0;
260 let Inst{15-11} = op;
261 let Inst{10-6} = 0x0;
265 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
267 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
269 let Inst{31-26} = 0x00;
270 let Inst{25-21} = 0x00;
271 let Inst{20-16} = rt;
272 let Inst{15-6} = funct;
273 let Inst{5-0} = 0x3c;