1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
50 let Inst{15-10} = 0x11;
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
60 let Inst{15-10} = 0x11;
65 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
71 let Inst{31-26} = 0b000000;
74 let Inst{15-12} = 0b0000;
75 let Inst{11-6} = funct;
76 let Inst{5-0} = 0b111100;
79 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
85 let Inst{31-26} = opgroup;
86 let Inst{25-21} = hint;
87 let Inst{20-16} = addr{20-16};
88 let Inst{15-12} = funct;
89 let Inst{11-0} = addr{11-0};
92 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
100 let Inst{25-21} = rt;
101 let Inst{20-16} = rs;
102 let Inst{15-11} = rd;
104 let Inst{9-0} = funct;
107 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
114 let Inst{31-26} = op;
115 let Inst{25-21} = rt;
116 let Inst{20-16} = rs;
117 let Inst{15-0} = imm16;
120 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
123 bits<5> base = addr{20-16};
124 bits<9> offset = addr{8-0};
128 let Inst{31-26} = op;
129 let Inst{25-21} = hint;
130 let Inst{20-16} = base;
131 let Inst{15-12} = 0b1010;
132 let Inst{11-9} = funct;
133 let Inst{8-0} = offset;
136 class LB32_FM_MMR6 : MipsR6Inst {
139 bits<5> base = addr{20-16};
140 bits<16> offset = addr{15-0};
144 let Inst{31-26} = 0b000111;
145 let Inst{25-21} = rt;
146 let Inst{20-16} = base;
147 let Inst{15-0} = offset;
150 class LBU32_FM_MMR6 : MipsR6Inst {
153 bits<5> base = addr{20-16};
154 bits<16> offset = addr{15-0};
158 let Inst{31-26} = 0b000101;
159 let Inst{25-21} = rt;
160 let Inst{20-16} = base;
161 let Inst{15-0} = offset;
164 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
170 let Inst{31-26} = 0b011000;
171 let Inst{25-21} = rt;
172 let Inst{20-16} = addr{20-16};
173 let Inst{15-12} = 0b0110;
174 let Inst{11-9} = funct;
175 let Inst{8-0} = addr{8-0};
178 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
179 : MMR6Arch<instr_asm> {
185 let Inst{31-26} = 0b000000;
186 let Inst{25-21} = rd;
187 let Inst{20-16} = rt;
188 let Inst{15-6} = funct;
189 let Inst{5-0} = 0b111100;
192 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
198 let Inst{31-26} = 0b011110;
199 let Inst{25-21} = rt;
200 let Inst{20-19} = funct;
201 let Inst{18-0} = imm;
204 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
210 let Inst{31-26} = 0b011110;
211 let Inst{25-21} = rt;
212 let Inst{20-16} = funct;
213 let Inst{15-0} = imm;
216 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
223 let Inst{31-26} = 0b000000;
224 let Inst{25-21} = rt;
225 let Inst{20-16} = rs;
226 let Inst{15-11} = rd;
228 let Inst{9-0} = funct;
231 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
237 let Inst{15-11} = op;
242 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
248 let Inst{25-21} = rt;
249 let Inst{20-16} = rd;
250 let Inst{15-6} = funct;
251 let Inst{5-0} = 0b111100;
254 class POOL32A_RDHWR_FM_MMR6 {
261 let Inst{25-21} = rt;
262 let Inst{20-16} = rs;
264 let Inst{13-11} = sel;
266 let Inst{9-0} = 0b0111000000;
269 class POOL32A_SYNC_FM_MMR6 {
276 let Inst{20-16} = stype;
277 let Inst{15-6} = 0b0110101101;
278 let Inst{5-0} = 0b111100;
281 class POOL32I_SYNCI_FM_MMR6 {
283 bits<5> base = addr{20-16};
284 bits<16> immediate = addr{15-0};
288 let Inst{31-26} = 0b010000;
289 let Inst{25-21} = 0b01100;
290 let Inst{20-16} = base;
291 let Inst{15-0} = immediate;
294 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
300 let Inst{31-26} = 0b000000;
301 let Inst{25-21} = rt;
302 let Inst{20-16} = rs;
303 let Inst{15-6} = funct;
304 let Inst{5-0} = 0b111100;
307 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
313 let Inst{31-26} = 0b000000;
314 let Inst{25-21} = rs;
315 let Inst{20-16} = 0b00000;
316 let Inst{15-11} = rt;
317 let Inst{10-6} = 0b00001;
318 let Inst{5-0} = funct;
321 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
329 let Inst{31-26} = 0b000000;
330 let Inst{25-21} = rs;
331 let Inst{20-16} = rt;
332 let Inst{15-11} = rd;
334 let Inst{8-6} = 0b000;
335 let Inst{5-0} = funct;
338 class AUI_FM_MMR6 : MipsR6Inst {
345 let Inst{31-26} = 0b000100;
346 let Inst{25-21} = rt;
347 let Inst{20-16} = rs;
348 let Inst{15-0} = imm;
351 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
359 let Inst{31-26} = 0b000000;
360 let Inst{25-21} = rt;
361 let Inst{20-16} = rs;
362 let Inst{15-11} = rd;
363 let Inst{10-9} = imm2;
364 let Inst{8-6} = 0b000;
365 let Inst{5-0} = funct;
368 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
371 bits<5> base = addr{20-16};
372 bits<16> offset = addr{15-0};
376 let Inst{31-26} = op;
377 let Inst{25-21} = rt;
378 let Inst{20-16} = base;
379 let Inst{15-0} = offset;
382 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
385 bits<5> base = addr{20-16};
386 bits<9> offset = addr{8-0};
390 let Inst{31-26} = 0b011000;
391 let Inst{25-21} = rt;
392 let Inst{20-16} = base;
393 let Inst{15-12} = 0b1010;
394 let Inst{11-9} = funct;
395 let Inst{8-0} = offset;
398 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
401 bits<5> base = addr{20-16};
402 bits<9> offset = addr{8-0};
406 let Inst{31-26} = 0b011000;
407 let Inst{25-21} = rt;
408 let Inst{20-16} = base;
409 let Inst{15-12} = 0b0110;
410 let Inst{11-9} = funct;
411 let Inst{8-0} = offset;
414 class LOAD_WORD_FM_MMR6 {
417 bits<5> base = addr{20-16};
418 bits<16> offset = addr{15-0};
422 let Inst{31-26} = 0b111111;
423 let Inst{25-21} = rt;
424 let Inst{20-16} = base;
425 let Inst{15-0} = offset;
428 class LOAD_UPPER_IMM_FM_MMR6 {
434 let Inst{31-26} = 0b000100;
435 let Inst{25-21} = rt;
437 let Inst{15-0} = imm16;
440 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
446 let Inst{31-26} = funct;
447 let Inst{25-21} = rt;
448 let Inst{20-16} = 0b00000;
449 let Inst{15-0} = offset;
452 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
458 let Inst{31-26} = funct;
459 let Inst{25-21} = rt;
460 let Inst{20-16} = rt;
461 let Inst{15-0} = offset;
464 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
467 let Inst{31-26} = 0x00;
468 let Inst{25-16} = 0x00;
469 let Inst{15-6} = 0x3cd;
470 let Inst{5-0} = 0x3c;
473 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
476 let Inst{31-26} = 0x00;
477 let Inst{25-17} = 0x00;
478 let Inst{16-16} = 0x01;
479 let Inst{15-6} = 0x3cd;
480 let Inst{5-0} = 0x3c;
483 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
487 let Inst{31-26} = 0x0;
488 let Inst{25-16} = code_1;
489 let Inst{15-6} = code_2;
490 let Inst{5-0} = 0x07;
493 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
496 let Inst{31-26} = 0x0;
497 let Inst{25-21} = 0x0;
498 let Inst{20-16} = 0x0;
499 let Inst{15-11} = op;
500 let Inst{10-6} = 0x0;
504 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
506 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
508 let Inst{31-26} = 0x00;
509 let Inst{25-21} = 0x00;
510 let Inst{20-16} = rt;
511 let Inst{15-6} = funct;
512 let Inst{5-0} = 0x3c;
515 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
523 let Inst{25-21} = rd;
524 let Inst{20-16} = rt;
525 let Inst{15-11} = shamt;
526 let Inst{10} = rotate;
527 let Inst{9-0} = funct;
530 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
536 let Inst{31-26} = op;
537 let Inst{25-21} = rt;
538 let Inst{20-16} = addr{20-16};
539 let Inst{15-0} = addr{15-0};
542 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
543 bits<3> funct> : MMR6Arch<instr_asm> {
546 bits<5> base = addr{20-16};
547 bits<9> offset = addr{8-0};
551 let Inst{31-26} = op;
552 let Inst{25-21} = rt;
553 let Inst{20-16} = base;
554 let Inst{15-12} = fmt;
555 let Inst{11-9} = funct;
556 let Inst{8-0} = offset;
559 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
560 : MMR6Arch<instr_asm>, MipsR6Inst {
567 let Inst{31-26} = 0b010101;
568 let Inst{25-21} = ft;
569 let Inst{20-16} = fs;
570 let Inst{15-11} = fd;
573 let Inst{7-0} = funct;
576 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
577 : MMR6Arch<instr_asm>, MipsR6Inst {
584 let Inst{31-26} = 0b010101;
585 let Inst{25-21} = ft;
586 let Inst{20-16} = fs;
587 let Inst{15-11} = fd;
588 let Inst{10-9} = fmt;
589 let Inst{8-0} = funct;
592 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
593 : MMR6Arch<instr_asm>, MipsR6Inst {
599 let Inst{31-26} = 0b010101;
600 let Inst{25-21} = ft;
601 let Inst{20-16} = fs;
603 let Inst{14-13} = fmt;
604 let Inst{12-6} = funct;
605 let Inst{5-0} = 0b111011;
608 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
609 : MMR6Arch<instr_asm>, MipsR6Inst {
616 let Inst{31-26} = 0b010101;
617 let Inst{25-21} = ft;
618 let Inst{20-16} = fs;
619 let Inst{15-11} = fd;
620 let Inst{10-9} = fmt;
621 let Inst{8-0} = funct;
624 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
625 : MMR6Arch<instr_asm>, MipsR6Inst {
632 let Inst{31-26} = 0b010101;
633 let Inst{25-21} = ft;
634 let Inst{20-16} = fs;
635 let Inst{15-11} = fd;
636 let Inst{10-6} = Cond.Value;
637 let Inst{5-0} = format;
640 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
641 : MMR6Arch<instr_asm>, MipsR6Inst {
646 let Inst{31-26} = 0b010101;
647 let Inst{25-21} = ft;
648 let Inst{20-16} = fs;
651 let Inst{13-6} = funct;
652 let Inst{5-0} = 0b111011;
655 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
656 : MMR6Arch<instr_asm>, MipsR6Inst {
661 let Inst{31-26} = 0b010101;
662 let Inst{25-21} = ft;
663 let Inst{20-16} = fs;
665 let Inst{14-13} = fmt;
666 let Inst{12-6} = funct;
667 let Inst{5-0} = 0b111011;
670 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
671 : MMR6Arch<instr_asm>, MipsR6Inst {
677 let Inst{31-26} = 0b010101;
678 let Inst{25-21} = ft;
679 let Inst{20-16} = fs;
681 let Inst{14-13} = fmt;
682 let Inst{12-6} = funct;
683 let Inst{5-0} = 0b111011;
686 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
687 : MMR6Arch<instr_asm>, MipsR6Inst {
693 let Inst{31-26} = 0b010101;
694 let Inst{25-21} = ft;
695 let Inst{20-16} = fs;
698 let Inst{13-6} = funct;
699 let Inst{5-0} = 0b111011;
702 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
709 let Inst{15-10} = 0b000001;
716 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
722 let Inst{15-10} = 0b010001;
725 let Inst{3-0} = 0b0001;
728 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
734 let Inst{15-10} = 0x11;
737 let Inst{3-0} = 0b0000;
740 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
746 let Inst{15-10} = 0b010001;
752 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
756 let Inst{15-10} = 0b010001;
757 let Inst{9-6} = code_;
761 class POOL16A_SUBU16_FM_MMR6 {
768 let Inst{15-10} = 0b000001;
775 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
781 let Inst{31-26} = 0x00;
782 let Inst{25-21} = rt;
783 let Inst{20-16} = rs;
784 let Inst{15-6} = funct;
785 let Inst{5-0} = 0x3c;