1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsMCNaCl.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
47 if (CPU.empty() || CPU == "generic") {
48 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
56 static MCInstrInfo *createMipsMCInstrInfo() {
57 MCInstrInfo *X = new MCInstrInfo();
58 InitMipsMCInstrInfo(X);
62 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
63 MCRegisterInfo *X = new MCRegisterInfo();
64 InitMipsMCRegisterInfo(X, Mips::RA);
68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
69 StringRef CPU, StringRef FS) {
70 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
71 return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
76 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
78 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
79 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
80 MAI->addInitialFrameState(Inst);
85 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
87 CodeGenOpt::Level OL) {
88 MCCodeGenInfo *X = new MCCodeGenInfo();
89 if (CM == CodeModel::JITDefault)
91 else if (RM == Reloc::Default)
93 X->initMCCodeGenInfo(RM, CM, OL);
97 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
98 unsigned SyntaxVariant,
100 const MCInstrInfo &MII,
101 const MCRegisterInfo &MRI) {
102 return new MipsInstPrinter(MAI, MII, MRI);
105 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
106 MCAsmBackend &MAB, raw_pwrite_stream &OS,
107 MCCodeEmitter *Emitter, bool RelaxAll) {
110 S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
112 S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
116 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
117 formatted_raw_ostream &OS,
118 MCInstPrinter *InstPrint,
120 return new MipsTargetAsmStreamer(S, OS);
123 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
124 return new MipsTargetStreamer(S);
127 static MCTargetStreamer *
128 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
129 return new MipsTargetELFStreamer(S, STI);
132 extern "C" void LLVMInitializeMipsTargetMC() {
133 for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
134 &TheMips64elTarget}) {
135 // Register the MC asm info.
136 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
138 // Register the MC codegen info.
139 TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
141 // Register the MC instruction info.
142 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
144 // Register the MC register info.
145 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
147 // Register the elf streamer.
148 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
150 // Register the asm target streamer.
151 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
153 TargetRegistry::RegisterNullTargetStreamer(*T,
154 createMipsNullTargetStreamer);
156 // Register the MC subtarget info.
157 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
159 // Register the MCInstPrinter.
160 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
162 TargetRegistry::RegisterObjectTargetStreamer(
163 *T, createMipsObjectTargetStreamer);
166 // Register the MC Code Emitter
167 for (Target *T : {&TheMipsTarget, &TheMips64Target})
168 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
170 for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
171 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
173 // Register the asm backend.
174 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
175 createMipsAsmBackendEB32);
176 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
177 createMipsAsmBackendEL32);
178 TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
179 createMipsAsmBackendEB64);
180 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
181 createMipsAsmBackendEL64);