1 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #ifndef MIPS_MC_CODE_EMITTER_H
16 #define MIPS_MC_CODE_EMITTER_H
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/Support/DataTypes.h"
30 class MCSubtargetInfo;
33 class MipsMCCodeEmitter : public MCCodeEmitter {
34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
36 const MCInstrInfo &MCII;
40 bool isMicroMips(const MCSubtargetInfo &STI) const;
43 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
44 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
46 ~MipsMCCodeEmitter() {}
48 void EmitByte(unsigned char C, raw_ostream &OS) const;
50 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
51 raw_ostream &OS) const;
53 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
54 SmallVectorImpl<MCFixup> &Fixups,
55 const MCSubtargetInfo &STI) const;
57 // getBinaryCodeForInstr - TableGen'erated function for getting the
58 // binary encoding for an instruction.
59 uint64_t getBinaryCodeForInstr(const MCInst &MI,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
63 // getBranchJumpOpValue - Return binary encoding of the jump
64 // target operand. If the machine operand requires relocation,
65 // record the relocation and return zero.
66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
70 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
71 // target operand. If the machine operand requires relocation,
72 // record the relocation and return zero.
73 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups,
75 const MCSubtargetInfo &STI) const;
77 // getBranchTargetOpValue - Return binary encoding of the branch
78 // target operand. If the machine operand requires relocation,
79 // record the relocation and return zero.
80 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
81 SmallVectorImpl<MCFixup> &Fixups,
82 const MCSubtargetInfo &STI) const;
84 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
85 // target operand. If the machine operand requires relocation,
86 // record the relocation and return zero.
87 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
91 // getMachineOpValue - Return binary encoding of operand. If the machin
92 // operand requires relocation, record the relocation and return zero.
93 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
97 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
98 SmallVectorImpl<MCFixup> &Fixups,
99 const MCSubtargetInfo &STI) const;
101 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
102 SmallVectorImpl<MCFixup> &Fixups,
103 const MCSubtargetInfo &STI) const;
104 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
108 SmallVectorImpl<MCFixup> &Fixups,
109 const MCSubtargetInfo &STI) const;
110 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
114 // getLSAImmEncoding - Return binary encoding of LSA immediate.
115 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
119 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
120 const MCSubtargetInfo &STI) const;
122 }; // class MipsMCCodeEmitter