1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "mccodeemitter"
32 #define GET_INSTRMAP_INFO
33 #include "MipsGenInstrInfo.inc"
34 #undef GET_INSTRMAP_INFO
37 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38 const MCRegisterInfo &MRI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
46 return new MipsMCCodeEmitter(MCII, Ctx, true);
48 } // End of namespace llvm.
50 // If the D<shift> instruction has a shift amount that is greater
51 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
52 static void LowerLargeShift(MCInst& Inst) {
54 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
55 assert(Inst.getOperand(2).isImm());
57 int64_t Shift = Inst.getOperand(2).getImm();
63 Inst.getOperand(2).setImm(Shift);
65 switch (Inst.getOpcode()) {
67 // Calling function is not synchronized
68 llvm_unreachable("Unexpected shift instruction");
70 Inst.setOpcode(Mips::DSLL32);
73 Inst.setOpcode(Mips::DSRL32);
76 Inst.setOpcode(Mips::DSRA32);
79 Inst.setOpcode(Mips::DROTR32);
84 // Pick a DEXT or DINS instruction variant based on the pos and size operands
85 static void LowerDextDins(MCInst& InstIn) {
86 int Opcode = InstIn.getOpcode();
88 if (Opcode == Mips::DEXT)
89 assert(InstIn.getNumOperands() == 4 &&
90 "Invalid no. of machine operands for DEXT!");
91 else // Only DEXT and DINS are possible
92 assert(InstIn.getNumOperands() == 5 &&
93 "Invalid no. of machine operands for DINS!");
95 assert(InstIn.getOperand(2).isImm());
96 int64_t pos = InstIn.getOperand(2).getImm();
97 assert(InstIn.getOperand(3).isImm());
98 int64_t size = InstIn.getOperand(3).getImm();
101 if (pos < 32) // DEXT/DINS, do nothing
104 InstIn.getOperand(2).setImm(pos - 32);
105 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
109 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
110 InstIn.getOperand(3).setImm(size - 32);
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
120 return STI.getFeatureBits()[Mips::FeatureMips32r6];
123 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
127 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
128 const MCSubtargetInfo &STI,
129 raw_ostream &OS) const {
130 // Output the instruction encoding in little endian byte order.
131 // Little-endian byte ordering:
132 // mips32r2: 4 | 3 | 2 | 1
133 // microMIPS: 2 | 1 | 4 | 3
134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
135 EmitInstruction(Val >> 16, 2, STI, OS);
136 EmitInstruction(Val, 2, STI, OS);
138 for (unsigned i = 0; i < Size; ++i) {
139 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
140 EmitByte((Val >> Shift) & 0xff, OS);
145 /// encodeInstruction - Emit the instruction.
146 /// Size the instruction with Desc.getSize().
147 void MipsMCCodeEmitter::
148 encodeInstruction(const MCInst &MI, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const
153 // Non-pseudo instructions that get changed for direct object
154 // only based on operand values.
155 // If this list of instructions get much longer we will move
156 // the check to a function call. Until then, this is more efficient.
158 switch (MI.getOpcode()) {
159 // If shift amount is >= 32 it the inst needs to be lowered further
164 LowerLargeShift(TmpInst);
166 // Double extract instruction is chosen by pos and size operands
169 LowerDextDins(TmpInst);
172 unsigned long N = Fixups.size();
173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
175 // Check for unimplemented opcodes.
176 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
177 // so we have to special check for them.
178 unsigned Opcode = TmpInst.getOpcode();
179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
180 (Opcode != Mips::SLL_MM) && !Binary)
181 llvm_unreachable("unimplemented opcode in encodeInstruction()");
184 if (isMicroMips(STI)) {
185 if (isMips32r6(STI)) {
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
188 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
191 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
193 if (NewOpcode != -1) {
194 if (Fixups.size() > N)
198 TmpInst.setOpcode (NewOpcode);
199 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
203 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
205 // Get byte count of instruction
206 unsigned Size = Desc.getSize();
208 llvm_unreachable("Desc.getSize() returns 0");
210 EmitInstruction(Binary, Size, STI, OS);
213 /// getBranchTargetOpValue - Return binary encoding of the branch
214 /// target operand. If the machine operand requires relocation,
215 /// record the relocation and return zero.
216 unsigned MipsMCCodeEmitter::
217 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
218 SmallVectorImpl<MCFixup> &Fixups,
219 const MCSubtargetInfo &STI) const {
221 const MCOperand &MO = MI.getOperand(OpNo);
223 // If the destination is an immediate, divide by 4.
224 if (MO.isImm()) return MO.getImm() >> 2;
226 assert(MO.isExpr() &&
227 "getBranchTargetOpValue expects only expressions or immediates");
229 const MCExpr *Expr = MO.getExpr();
230 Fixups.push_back(MCFixup::create(0, Expr,
231 MCFixupKind(Mips::fixup_Mips_PC16)));
235 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
236 /// target operand. If the machine operand requires relocation,
237 /// record the relocation and return zero.
238 unsigned MipsMCCodeEmitter::
239 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
240 SmallVectorImpl<MCFixup> &Fixups,
241 const MCSubtargetInfo &STI) const {
243 const MCOperand &MO = MI.getOperand(OpNo);
245 // If the destination is an immediate, divide by 2.
246 if (MO.isImm()) return MO.getImm() >> 1;
248 assert(MO.isExpr() &&
249 "getBranchTargetOpValueMM expects only expressions or immediates");
251 const MCExpr *Expr = MO.getExpr();
252 Fixups.push_back(MCFixup::create(0, Expr,
253 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
257 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
258 /// 10-bit branch target operand. If the machine operand requires relocation,
259 /// record the relocation and return zero.
260 unsigned MipsMCCodeEmitter::
261 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
262 SmallVectorImpl<MCFixup> &Fixups,
263 const MCSubtargetInfo &STI) const {
265 const MCOperand &MO = MI.getOperand(OpNo);
267 // If the destination is an immediate, divide by 2.
268 if (MO.isImm()) return MO.getImm() >> 1;
270 assert(MO.isExpr() &&
271 "getBranchTargetOpValuePC10 expects only expressions or immediates");
273 const MCExpr *Expr = MO.getExpr();
274 Fixups.push_back(MCFixup::create(0, Expr,
275 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
279 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
280 /// target operand. If the machine operand requires relocation,
281 /// record the relocation and return zero.
282 unsigned MipsMCCodeEmitter::
283 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
284 SmallVectorImpl<MCFixup> &Fixups,
285 const MCSubtargetInfo &STI) const {
287 const MCOperand &MO = MI.getOperand(OpNo);
289 // If the destination is an immediate, divide by 2.
290 if (MO.isImm()) return MO.getImm() >> 1;
292 assert(MO.isExpr() &&
293 "getBranchTargetOpValueMM expects only expressions or immediates");
295 const MCExpr *Expr = MO.getExpr();
296 Fixups.push_back(MCFixup::create(0, Expr,
298 fixup_MICROMIPS_PC16_S1)));
302 /// getBranchTarget21OpValue - Return binary encoding of the branch
303 /// target operand. If the machine operand requires relocation,
304 /// record the relocation and return zero.
305 unsigned MipsMCCodeEmitter::
306 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
307 SmallVectorImpl<MCFixup> &Fixups,
308 const MCSubtargetInfo &STI) const {
310 const MCOperand &MO = MI.getOperand(OpNo);
312 // If the destination is an immediate, divide by 4.
313 if (MO.isImm()) return MO.getImm() >> 2;
315 assert(MO.isExpr() &&
316 "getBranchTarget21OpValue expects only expressions or immediates");
318 const MCExpr *Expr = MO.getExpr();
319 Fixups.push_back(MCFixup::create(0, Expr,
320 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
324 /// getBranchTarget26OpValue - Return binary encoding of the branch
325 /// target operand. If the machine operand requires relocation,
326 /// record the relocation and return zero.
327 unsigned MipsMCCodeEmitter::
328 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
329 SmallVectorImpl<MCFixup> &Fixups,
330 const MCSubtargetInfo &STI) const {
332 const MCOperand &MO = MI.getOperand(OpNo);
334 // If the destination is an immediate, divide by 4.
335 if (MO.isImm()) return MO.getImm() >> 2;
337 assert(MO.isExpr() &&
338 "getBranchTarget26OpValue expects only expressions or immediates");
340 const MCExpr *Expr = MO.getExpr();
341 Fixups.push_back(MCFixup::create(0, Expr,
342 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
346 /// getJumpOffset16OpValue - Return binary encoding of the jump
347 /// target operand. If the machine operand requires relocation,
348 /// record the relocation and return zero.
349 unsigned MipsMCCodeEmitter::
350 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
351 SmallVectorImpl<MCFixup> &Fixups,
352 const MCSubtargetInfo &STI) const {
354 const MCOperand &MO = MI.getOperand(OpNo);
356 if (MO.isImm()) return MO.getImm();
358 assert(MO.isExpr() &&
359 "getJumpOffset16OpValue expects only expressions or an immediate");
365 /// getJumpTargetOpValue - Return binary encoding of the jump
366 /// target operand. If the machine operand requires relocation,
367 /// record the relocation and return zero.
368 unsigned MipsMCCodeEmitter::
369 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
370 SmallVectorImpl<MCFixup> &Fixups,
371 const MCSubtargetInfo &STI) const {
373 const MCOperand &MO = MI.getOperand(OpNo);
374 // If the destination is an immediate, divide by 4.
375 if (MO.isImm()) return MO.getImm()>>2;
377 assert(MO.isExpr() &&
378 "getJumpTargetOpValue expects only expressions or an immediate");
380 const MCExpr *Expr = MO.getExpr();
381 Fixups.push_back(MCFixup::create(0, Expr,
382 MCFixupKind(Mips::fixup_Mips_26)));
386 unsigned MipsMCCodeEmitter::
387 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
388 SmallVectorImpl<MCFixup> &Fixups,
389 const MCSubtargetInfo &STI) const {
391 const MCOperand &MO = MI.getOperand(OpNo);
392 // If the destination is an immediate, divide by 2.
393 if (MO.isImm()) return MO.getImm() >> 1;
395 assert(MO.isExpr() &&
396 "getJumpTargetOpValueMM expects only expressions or an immediate");
398 const MCExpr *Expr = MO.getExpr();
399 Fixups.push_back(MCFixup::create(0, Expr,
400 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
404 unsigned MipsMCCodeEmitter::
405 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
406 SmallVectorImpl<MCFixup> &Fixups,
407 const MCSubtargetInfo &STI) const {
409 const MCOperand &MO = MI.getOperand(OpNo);
411 // The immediate is encoded as 'immediate << 2'.
412 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
413 assert((Res & 3) == 0);
417 assert(MO.isExpr() &&
418 "getUImm5Lsl2Encoding expects only expressions or an immediate");
423 unsigned MipsMCCodeEmitter::
424 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
425 SmallVectorImpl<MCFixup> &Fixups,
426 const MCSubtargetInfo &STI) const {
428 const MCOperand &MO = MI.getOperand(OpNo);
430 int Value = MO.getImm();
437 unsigned MipsMCCodeEmitter::
438 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
439 SmallVectorImpl<MCFixup> &Fixups,
440 const MCSubtargetInfo &STI) const {
442 const MCOperand &MO = MI.getOperand(OpNo);
444 unsigned Value = MO.getImm();
451 unsigned MipsMCCodeEmitter::
452 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
453 SmallVectorImpl<MCFixup> &Fixups,
454 const MCSubtargetInfo &STI) const {
456 const MCOperand &MO = MI.getOperand(OpNo);
458 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
459 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
465 unsigned MipsMCCodeEmitter::
466 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
467 const MCSubtargetInfo &STI) const {
470 if (Expr->EvaluateAsAbsolute(Res))
473 MCExpr::ExprKind Kind = Expr->getKind();
474 if (Kind == MCExpr::Constant) {
475 return cast<MCConstantExpr>(Expr)->getValue();
478 if (Kind == MCExpr::Binary) {
479 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
480 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
484 if (Kind == MCExpr::Target) {
485 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
487 Mips::Fixups FixupKind = Mips::Fixups(0);
488 switch (MipsExpr->getKind()) {
489 default: llvm_unreachable("Unsupported fixup kind for target expression!");
490 case MipsMCExpr::VK_Mips_HIGHEST:
491 FixupKind = Mips::fixup_Mips_HIGHEST;
493 case MipsMCExpr::VK_Mips_HIGHER:
494 FixupKind = Mips::fixup_Mips_HIGHER;
496 case MipsMCExpr::VK_Mips_HI:
497 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
498 : Mips::fixup_Mips_HI16;
500 case MipsMCExpr::VK_Mips_LO:
501 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
502 : Mips::fixup_Mips_LO16;
505 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
509 if (Kind == MCExpr::SymbolRef) {
510 Mips::Fixups FixupKind = Mips::Fixups(0);
512 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
513 default: llvm_unreachable("Unknown fixup kind!");
515 case MCSymbolRefExpr::VK_None:
516 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
518 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
519 FixupKind = Mips::fixup_Mips_GPOFF_HI;
521 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
522 FixupKind = Mips::fixup_Mips_GPOFF_LO;
524 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
525 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
526 : Mips::fixup_Mips_GOT_PAGE;
528 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
529 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
530 : Mips::fixup_Mips_GOT_OFST;
532 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
533 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
534 : Mips::fixup_Mips_GOT_DISP;
536 case MCSymbolRefExpr::VK_Mips_GPREL:
537 FixupKind = Mips::fixup_Mips_GPREL16;
539 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
540 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
541 : Mips::fixup_Mips_CALL16;
543 case MCSymbolRefExpr::VK_Mips_GOT16:
544 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
545 : Mips::fixup_Mips_GOT_Global;
547 case MCSymbolRefExpr::VK_Mips_GOT:
548 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
549 : Mips::fixup_Mips_GOT_Local;
551 case MCSymbolRefExpr::VK_Mips_ABS_HI:
552 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
553 : Mips::fixup_Mips_HI16;
555 case MCSymbolRefExpr::VK_Mips_ABS_LO:
556 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
557 : Mips::fixup_Mips_LO16;
559 case MCSymbolRefExpr::VK_Mips_TLSGD:
560 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
561 : Mips::fixup_Mips_TLSGD;
563 case MCSymbolRefExpr::VK_Mips_TLSLDM:
564 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
565 : Mips::fixup_Mips_TLSLDM;
567 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
568 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
569 : Mips::fixup_Mips_DTPREL_HI;
571 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
572 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
573 : Mips::fixup_Mips_DTPREL_LO;
575 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
576 FixupKind = Mips::fixup_Mips_GOTTPREL;
578 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
579 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
580 : Mips::fixup_Mips_TPREL_HI;
582 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
583 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
584 : Mips::fixup_Mips_TPREL_LO;
586 case MCSymbolRefExpr::VK_Mips_HIGHER:
587 FixupKind = Mips::fixup_Mips_HIGHER;
589 case MCSymbolRefExpr::VK_Mips_HIGHEST:
590 FixupKind = Mips::fixup_Mips_HIGHEST;
592 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
593 FixupKind = Mips::fixup_Mips_GOT_HI16;
595 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
596 FixupKind = Mips::fixup_Mips_GOT_LO16;
598 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
599 FixupKind = Mips::fixup_Mips_CALL_HI16;
601 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
602 FixupKind = Mips::fixup_Mips_CALL_LO16;
604 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
605 FixupKind = Mips::fixup_MIPS_PCHI16;
607 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
608 FixupKind = Mips::fixup_MIPS_PCLO16;
612 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
618 /// getMachineOpValue - Return binary encoding of operand. If the machine
619 /// operand requires relocation, record the relocation and return zero.
620 unsigned MipsMCCodeEmitter::
621 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
622 SmallVectorImpl<MCFixup> &Fixups,
623 const MCSubtargetInfo &STI) const {
625 unsigned Reg = MO.getReg();
626 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
628 } else if (MO.isImm()) {
629 return static_cast<unsigned>(MO.getImm());
630 } else if (MO.isFPImm()) {
631 return static_cast<unsigned>(APFloat(MO.getFPImm())
632 .bitcastToAPInt().getHiBits(32).getLimitedValue());
634 // MO must be an Expr.
636 return getExprOpValue(MO.getExpr(),Fixups, STI);
639 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
642 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
643 SmallVectorImpl<MCFixup> &Fixups,
644 const MCSubtargetInfo &STI) const {
645 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
646 assert(MI.getOperand(OpNo).isReg());
647 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
648 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
650 // The immediate field of an LD/ST instruction is scaled which means it must
651 // be divided (when encoding) by the size (in bytes) of the instructions'
657 switch(MI.getOpcode())
660 assert (0 && "Unexpected instruction");
664 // We don't need to scale the offset in this case
680 return (OffBits & 0xFFFF) | RegBits;
683 /// getMemEncoding - Return binary encoding of memory related operand.
684 /// If the offset operand requires relocation, record the relocation.
686 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
687 SmallVectorImpl<MCFixup> &Fixups,
688 const MCSubtargetInfo &STI) const {
689 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
690 assert(MI.getOperand(OpNo).isReg());
691 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
692 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
694 return (OffBits & 0xFFFF) | RegBits;
697 unsigned MipsMCCodeEmitter::
698 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
699 SmallVectorImpl<MCFixup> &Fixups,
700 const MCSubtargetInfo &STI) const {
701 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
702 assert(MI.getOperand(OpNo).isReg());
703 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
705 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
708 return (OffBits & 0xF) | RegBits;
711 unsigned MipsMCCodeEmitter::
712 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
713 SmallVectorImpl<MCFixup> &Fixups,
714 const MCSubtargetInfo &STI) const {
715 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
716 assert(MI.getOperand(OpNo).isReg());
717 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
719 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
722 return (OffBits & 0xF) | RegBits;
725 unsigned MipsMCCodeEmitter::
726 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
727 SmallVectorImpl<MCFixup> &Fixups,
728 const MCSubtargetInfo &STI) const {
729 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
730 assert(MI.getOperand(OpNo).isReg());
731 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
733 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
736 return (OffBits & 0xF) | RegBits;
739 unsigned MipsMCCodeEmitter::
740 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
741 SmallVectorImpl<MCFixup> &Fixups,
742 const MCSubtargetInfo &STI) const {
743 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
744 assert(MI.getOperand(OpNo).isReg() &&
745 MI.getOperand(OpNo).getReg() == Mips::SP &&
746 "Unexpected base register!");
747 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
750 return OffBits & 0x1F;
753 unsigned MipsMCCodeEmitter::
754 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
755 SmallVectorImpl<MCFixup> &Fixups,
756 const MCSubtargetInfo &STI) const {
757 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
758 assert(MI.getOperand(OpNo).isReg() &&
759 MI.getOperand(OpNo).getReg() == Mips::GP &&
760 "Unexpected base register!");
762 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
765 return OffBits & 0x7F;
768 unsigned MipsMCCodeEmitter::
769 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
770 SmallVectorImpl<MCFixup> &Fixups,
771 const MCSubtargetInfo &STI) const {
772 // opNum can be invalid if instruction had reglist as operand.
773 // MemOperand is always last operand of instruction (base + offset).
774 switch (MI.getOpcode()) {
779 OpNo = MI.getNumOperands() - 2;
783 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
784 assert(MI.getOperand(OpNo).isReg());
785 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
786 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
788 return (OffBits & 0x0FFF) | RegBits;
791 unsigned MipsMCCodeEmitter::
792 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
793 SmallVectorImpl<MCFixup> &Fixups,
794 const MCSubtargetInfo &STI) const {
795 // opNum can be invalid if instruction had reglist as operand
796 // MemOperand is always last operand of instruction (base + offset)
797 switch (MI.getOpcode()) {
802 OpNo = MI.getNumOperands() - 2;
806 // Offset is encoded in bits 4-0.
807 assert(MI.getOperand(OpNo).isReg());
808 // Base register is always SP - thus it is not encoded.
809 assert(MI.getOperand(OpNo+1).isImm());
810 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
812 return ((OffBits >> 2) & 0x0F);
816 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
817 SmallVectorImpl<MCFixup> &Fixups,
818 const MCSubtargetInfo &STI) const {
819 assert(MI.getOperand(OpNo).isImm());
820 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
821 return SizeEncoding - 1;
824 // FIXME: should be called getMSBEncoding
827 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
828 SmallVectorImpl<MCFixup> &Fixups,
829 const MCSubtargetInfo &STI) const {
830 assert(MI.getOperand(OpNo-1).isImm());
831 assert(MI.getOperand(OpNo).isImm());
832 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
833 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
835 return Position + Size - 1;
839 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
840 SmallVectorImpl<MCFixup> &Fixups,
841 const MCSubtargetInfo &STI) const {
842 assert(MI.getOperand(OpNo).isImm());
843 // The immediate is encoded as 'immediate - 1'.
844 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
848 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
849 SmallVectorImpl<MCFixup> &Fixups,
850 const MCSubtargetInfo &STI) const {
851 const MCOperand &MO = MI.getOperand(OpNo);
853 // The immediate is encoded as 'immediate << 2'.
854 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
855 assert((Res & 3) == 0);
859 assert(MO.isExpr() &&
860 "getSimm19Lsl2Encoding expects only expressions or an immediate");
862 const MCExpr *Expr = MO.getExpr();
863 Fixups.push_back(MCFixup::create(0, Expr,
864 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
869 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
870 SmallVectorImpl<MCFixup> &Fixups,
871 const MCSubtargetInfo &STI) const {
872 const MCOperand &MO = MI.getOperand(OpNo);
874 // The immediate is encoded as 'immediate << 3'.
875 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
876 assert((Res & 7) == 0);
880 assert(MO.isExpr() &&
881 "getSimm18Lsl2Encoding expects only expressions or an immediate");
883 const MCExpr *Expr = MO.getExpr();
884 Fixups.push_back(MCFixup::create(0, Expr,
885 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
890 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
891 SmallVectorImpl<MCFixup> &Fixups,
892 const MCSubtargetInfo &STI) const {
893 assert(MI.getOperand(OpNo).isImm());
894 const MCOperand &MO = MI.getOperand(OpNo);
895 return MO.getImm() % 8;
899 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
900 SmallVectorImpl<MCFixup> &Fixups,
901 const MCSubtargetInfo &STI) const {
902 assert(MI.getOperand(OpNo).isImm());
903 const MCOperand &MO = MI.getOperand(OpNo);
904 unsigned Value = MO.getImm();
906 case 128: return 0x0;
919 case 255: return 0xd;
920 case 32768: return 0xe;
921 case 65535: return 0xf;
923 llvm_unreachable("Unexpected value");
927 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
928 SmallVectorImpl<MCFixup> &Fixups,
929 const MCSubtargetInfo &STI) const {
932 // Register list operand is always first operand of instruction and it is
933 // placed before memory operand (register + imm).
935 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
936 unsigned Reg = MI.getOperand(I).getReg();
937 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
947 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
948 SmallVectorImpl<MCFixup> &Fixups,
949 const MCSubtargetInfo &STI) const {
950 return (MI.getNumOperands() - 4);
954 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
955 SmallVectorImpl<MCFixup> &Fixups,
956 const MCSubtargetInfo &STI) const {
957 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
961 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
962 SmallVectorImpl<MCFixup> &Fixups,
963 const MCSubtargetInfo &STI) const {
966 if (MI.getOperand(0).getReg() == Mips::A1 &&
967 MI.getOperand(1).getReg() == Mips::A2)
969 else if (MI.getOperand(0).getReg() == Mips::A1 &&
970 MI.getOperand(1).getReg() == Mips::A3)
972 else if (MI.getOperand(0).getReg() == Mips::A2 &&
973 MI.getOperand(1).getReg() == Mips::A3)
975 else if (MI.getOperand(0).getReg() == Mips::A0 &&
976 MI.getOperand(1).getReg() == Mips::S5)
978 else if (MI.getOperand(0).getReg() == Mips::A0 &&
979 MI.getOperand(1).getReg() == Mips::S6)
981 else if (MI.getOperand(0).getReg() == Mips::A0 &&
982 MI.getOperand(1).getReg() == Mips::A1)
984 else if (MI.getOperand(0).getReg() == Mips::A0 &&
985 MI.getOperand(1).getReg() == Mips::A2)
987 else if (MI.getOperand(0).getReg() == Mips::A0 &&
988 MI.getOperand(1).getReg() == Mips::A3)
995 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
996 SmallVectorImpl<MCFixup> &Fixups,
997 const MCSubtargetInfo &STI) const {
998 const MCOperand &MO = MI.getOperand(OpNo);
999 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1000 // The immediate is encoded as 'immediate >> 2'.
1001 unsigned Res = static_cast<unsigned>(MO.getImm());
1002 assert((Res & 3) == 0);
1006 #include "MipsGenMCCodeEmitter.inc"