1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mccodeemitter"
17 #include "MipsMCCodeEmitter.h"
18 #include "MCTargetDesc/MipsFixupKinds.h"
19 #include "MCTargetDesc/MipsMCExpr.h"
20 #include "MCTargetDesc/MipsMCTargetDesc.h"
21 #include "llvm/ADT/APFloat.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCFixup.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/raw_ostream.h"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
177 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
179 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181 if (NewOpcode != -1) {
182 if (Fixups.size() > N)
185 TmpInst.setOpcode (NewOpcode);
186 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
190 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
192 // Get byte count of instruction
193 unsigned Size = Desc.getSize();
195 llvm_unreachable("Desc.getSize() returns 0");
197 EmitInstruction(Binary, Size, STI, OS);
200 /// getBranchTargetOpValue - Return binary encoding of the branch
201 /// target operand. If the machine operand requires relocation,
202 /// record the relocation and return zero.
203 unsigned MipsMCCodeEmitter::
204 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
205 SmallVectorImpl<MCFixup> &Fixups,
206 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
210 // If the destination is an immediate, divide by 4.
211 if (MO.isImm()) return MO.getImm() >> 2;
213 assert(MO.isExpr() &&
214 "getBranchTargetOpValue expects only expressions or immediates");
216 const MCExpr *Expr = MO.getExpr();
217 Fixups.push_back(MCFixup::Create(0, Expr,
218 MCFixupKind(Mips::fixup_Mips_PC16)));
222 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
223 /// target operand. If the machine operand requires relocation,
224 /// record the relocation and return zero.
225 unsigned MipsMCCodeEmitter::
226 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const {
230 const MCOperand &MO = MI.getOperand(OpNo);
232 // If the destination is an immediate, divide by 2.
233 if (MO.isImm()) return MO.getImm() >> 1;
235 assert(MO.isExpr() &&
236 "getBranchTargetOpValueMM expects only expressions or immediates");
238 const MCExpr *Expr = MO.getExpr();
239 Fixups.push_back(MCFixup::Create(0, Expr,
241 fixup_MICROMIPS_PC16_S1)));
245 /// getJumpTargetOpValue - Return binary encoding of the jump
246 /// target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const {
253 const MCOperand &MO = MI.getOperand(OpNo);
254 // If the destination is an immediate, divide by 4.
255 if (MO.isImm()) return MO.getImm()>>2;
257 assert(MO.isExpr() &&
258 "getJumpTargetOpValue expects only expressions or an immediate");
260 const MCExpr *Expr = MO.getExpr();
261 Fixups.push_back(MCFixup::Create(0, Expr,
262 MCFixupKind(Mips::fixup_Mips_26)));
266 unsigned MipsMCCodeEmitter::
267 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
268 SmallVectorImpl<MCFixup> &Fixups,
269 const MCSubtargetInfo &STI) const {
271 const MCOperand &MO = MI.getOperand(OpNo);
272 // If the destination is an immediate, divide by 2.
273 if (MO.isImm()) return MO.getImm() >> 1;
275 assert(MO.isExpr() &&
276 "getJumpTargetOpValueMM expects only expressions or an immediate");
278 const MCExpr *Expr = MO.getExpr();
279 Fixups.push_back(MCFixup::Create(0, Expr,
280 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
284 unsigned MipsMCCodeEmitter::
285 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
286 const MCSubtargetInfo &STI) const {
289 if (Expr->EvaluateAsAbsolute(Res))
292 MCExpr::ExprKind Kind = Expr->getKind();
293 if (Kind == MCExpr::Constant) {
294 return cast<MCConstantExpr>(Expr)->getValue();
297 if (Kind == MCExpr::Binary) {
298 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
299 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
303 if (Kind == MCExpr::Target) {
304 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
306 Mips::Fixups FixupKind = Mips::Fixups(0);
307 switch (MipsExpr->getKind()) {
308 default: llvm_unreachable("Unsupported fixup kind for target expression!");
309 case MipsMCExpr::VK_Mips_ABS_HI:
310 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
311 : Mips::fixup_Mips_HI16;
313 case MipsMCExpr::VK_Mips_ABS_LO:
314 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
315 : Mips::fixup_Mips_LO16;
318 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
322 if (Kind == MCExpr::SymbolRef) {
323 Mips::Fixups FixupKind = Mips::Fixups(0);
325 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
326 default: llvm_unreachable("Unknown fixup kind!");
328 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
329 FixupKind = Mips::fixup_Mips_GPOFF_HI;
331 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
332 FixupKind = Mips::fixup_Mips_GPOFF_LO;
334 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
335 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
336 : Mips::fixup_Mips_GOT_PAGE;
338 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
339 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
340 : Mips::fixup_Mips_GOT_OFST;
342 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
343 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
344 : Mips::fixup_Mips_GOT_DISP;
346 case MCSymbolRefExpr::VK_Mips_GPREL:
347 FixupKind = Mips::fixup_Mips_GPREL16;
349 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
350 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
351 : Mips::fixup_Mips_CALL16;
353 case MCSymbolRefExpr::VK_Mips_GOT16:
354 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
355 : Mips::fixup_Mips_GOT_Global;
357 case MCSymbolRefExpr::VK_Mips_GOT:
358 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
359 : Mips::fixup_Mips_GOT_Local;
361 case MCSymbolRefExpr::VK_Mips_ABS_HI:
362 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
363 : Mips::fixup_Mips_HI16;
365 case MCSymbolRefExpr::VK_Mips_ABS_LO:
366 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
367 : Mips::fixup_Mips_LO16;
369 case MCSymbolRefExpr::VK_Mips_TLSGD:
370 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
371 : Mips::fixup_Mips_TLSGD;
373 case MCSymbolRefExpr::VK_Mips_TLSLDM:
374 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
375 : Mips::fixup_Mips_TLSLDM;
377 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
378 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
379 : Mips::fixup_Mips_DTPREL_HI;
381 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
382 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
383 : Mips::fixup_Mips_DTPREL_LO;
385 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
386 FixupKind = Mips::fixup_Mips_GOTTPREL;
388 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
389 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
390 : Mips::fixup_Mips_TPREL_HI;
392 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
393 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
394 : Mips::fixup_Mips_TPREL_LO;
396 case MCSymbolRefExpr::VK_Mips_HIGHER:
397 FixupKind = Mips::fixup_Mips_HIGHER;
399 case MCSymbolRefExpr::VK_Mips_HIGHEST:
400 FixupKind = Mips::fixup_Mips_HIGHEST;
402 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
403 FixupKind = Mips::fixup_Mips_GOT_HI16;
405 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
406 FixupKind = Mips::fixup_Mips_GOT_LO16;
408 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
409 FixupKind = Mips::fixup_Mips_CALL_HI16;
411 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
412 FixupKind = Mips::fixup_Mips_CALL_LO16;
416 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
422 /// getMachineOpValue - Return binary encoding of operand. If the machine
423 /// operand requires relocation, record the relocation and return zero.
424 unsigned MipsMCCodeEmitter::
425 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
426 SmallVectorImpl<MCFixup> &Fixups,
427 const MCSubtargetInfo &STI) const {
429 unsigned Reg = MO.getReg();
430 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
432 } else if (MO.isImm()) {
433 return static_cast<unsigned>(MO.getImm());
434 } else if (MO.isFPImm()) {
435 return static_cast<unsigned>(APFloat(MO.getFPImm())
436 .bitcastToAPInt().getHiBits(32).getLimitedValue());
438 // MO must be an Expr.
440 return getExprOpValue(MO.getExpr(),Fixups, STI);
443 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
446 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
447 SmallVectorImpl<MCFixup> &Fixups,
448 const MCSubtargetInfo &STI) const {
449 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
450 assert(MI.getOperand(OpNo).isReg());
451 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
452 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
454 // The immediate field of an LD/ST instruction is scaled which means it must
455 // be divided (when encoding) by the size (in bytes) of the instructions'
461 switch(MI.getOpcode())
464 assert (0 && "Unexpected instruction");
468 // We don't need to scale the offset in this case
484 return (OffBits & 0xFFFF) | RegBits;
487 /// getMemEncoding - Return binary encoding of memory related operand.
488 /// If the offset operand requires relocation, record the relocation.
490 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
491 SmallVectorImpl<MCFixup> &Fixups,
492 const MCSubtargetInfo &STI) const {
493 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
494 assert(MI.getOperand(OpNo).isReg());
495 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
496 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
498 return (OffBits & 0xFFFF) | RegBits;
501 unsigned MipsMCCodeEmitter::
502 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
503 SmallVectorImpl<MCFixup> &Fixups,
504 const MCSubtargetInfo &STI) const {
505 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
506 assert(MI.getOperand(OpNo).isReg());
507 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
508 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
510 return (OffBits & 0x0FFF) | RegBits;
514 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
515 SmallVectorImpl<MCFixup> &Fixups,
516 const MCSubtargetInfo &STI) const {
517 assert(MI.getOperand(OpNo).isImm());
518 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
519 return SizeEncoding - 1;
522 // FIXME: should be called getMSBEncoding
525 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
526 SmallVectorImpl<MCFixup> &Fixups,
527 const MCSubtargetInfo &STI) const {
528 assert(MI.getOperand(OpNo-1).isImm());
529 assert(MI.getOperand(OpNo).isImm());
530 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
531 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
533 return Position + Size - 1;
537 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
538 SmallVectorImpl<MCFixup> &Fixups,
539 const MCSubtargetInfo &STI) const {
540 assert(MI.getOperand(OpNo).isImm());
541 // The immediate is encoded as 'immediate - 1'.
542 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
545 #include "MipsGenMCCodeEmitter.inc"