1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
177 (Opcode != Mips::SLL_MM) && !Binary)
178 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
180 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
181 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
182 if (NewOpcode != -1) {
183 if (Fixups.size() > N)
186 TmpInst.setOpcode (NewOpcode);
187 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
191 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
193 // Get byte count of instruction
194 unsigned Size = Desc.getSize();
196 llvm_unreachable("Desc.getSize() returns 0");
198 EmitInstruction(Binary, Size, STI, OS);
201 /// getBranchTargetOpValue - Return binary encoding of the branch
202 /// target operand. If the machine operand requires relocation,
203 /// record the relocation and return zero.
204 unsigned MipsMCCodeEmitter::
205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
209 const MCOperand &MO = MI.getOperand(OpNo);
211 // If the destination is an immediate, divide by 4.
212 if (MO.isImm()) return MO.getImm() >> 2;
214 assert(MO.isExpr() &&
215 "getBranchTargetOpValue expects only expressions or immediates");
217 const MCExpr *Expr = MO.getExpr();
218 Fixups.push_back(MCFixup::Create(0, Expr,
219 MCFixupKind(Mips::fixup_Mips_PC16)));
223 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
224 /// target operand. If the machine operand requires relocation,
225 /// record the relocation and return zero.
226 unsigned MipsMCCodeEmitter::
227 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
228 SmallVectorImpl<MCFixup> &Fixups,
229 const MCSubtargetInfo &STI) const {
231 const MCOperand &MO = MI.getOperand(OpNo);
233 // If the destination is an immediate, divide by 2.
234 if (MO.isImm()) return MO.getImm() >> 1;
236 assert(MO.isExpr() &&
237 "getBranchTargetOpValueMM expects only expressions or immediates");
239 const MCExpr *Expr = MO.getExpr();
240 Fixups.push_back(MCFixup::Create(0, Expr,
241 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
245 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
246 /// target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const {
253 const MCOperand &MO = MI.getOperand(OpNo);
255 // If the destination is an immediate, divide by 2.
256 if (MO.isImm()) return MO.getImm() >> 1;
258 assert(MO.isExpr() &&
259 "getBranchTargetOpValueMM expects only expressions or immediates");
261 const MCExpr *Expr = MO.getExpr();
262 Fixups.push_back(MCFixup::Create(0, Expr,
264 fixup_MICROMIPS_PC16_S1)));
268 /// getBranchTarget21OpValue - Return binary encoding of the branch
269 /// target operand. If the machine operand requires relocation,
270 /// record the relocation and return zero.
271 unsigned MipsMCCodeEmitter::
272 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
273 SmallVectorImpl<MCFixup> &Fixups,
274 const MCSubtargetInfo &STI) const {
276 const MCOperand &MO = MI.getOperand(OpNo);
278 // If the destination is an immediate, divide by 4.
279 if (MO.isImm()) return MO.getImm() >> 2;
281 assert(MO.isExpr() &&
282 "getBranchTarget21OpValue expects only expressions or immediates");
284 const MCExpr *Expr = MO.getExpr();
285 Fixups.push_back(MCFixup::Create(0, Expr,
286 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
290 /// getBranchTarget26OpValue - Return binary encoding of the branch
291 /// target operand. If the machine operand requires relocation,
292 /// record the relocation and return zero.
293 unsigned MipsMCCodeEmitter::
294 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
295 SmallVectorImpl<MCFixup> &Fixups,
296 const MCSubtargetInfo &STI) const {
298 const MCOperand &MO = MI.getOperand(OpNo);
300 // If the destination is an immediate, divide by 4.
301 if (MO.isImm()) return MO.getImm() >> 2;
303 assert(MO.isExpr() &&
304 "getBranchTarget26OpValue expects only expressions or immediates");
306 const MCExpr *Expr = MO.getExpr();
307 Fixups.push_back(MCFixup::Create(0, Expr,
308 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
312 /// getJumpOffset16OpValue - Return binary encoding of the jump
313 /// target operand. If the machine operand requires relocation,
314 /// record the relocation and return zero.
315 unsigned MipsMCCodeEmitter::
316 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
317 SmallVectorImpl<MCFixup> &Fixups,
318 const MCSubtargetInfo &STI) const {
320 const MCOperand &MO = MI.getOperand(OpNo);
322 if (MO.isImm()) return MO.getImm();
324 assert(MO.isExpr() &&
325 "getJumpOffset16OpValue expects only expressions or an immediate");
331 /// getJumpTargetOpValue - Return binary encoding of the jump
332 /// target operand. If the machine operand requires relocation,
333 /// record the relocation and return zero.
334 unsigned MipsMCCodeEmitter::
335 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
336 SmallVectorImpl<MCFixup> &Fixups,
337 const MCSubtargetInfo &STI) const {
339 const MCOperand &MO = MI.getOperand(OpNo);
340 // If the destination is an immediate, divide by 4.
341 if (MO.isImm()) return MO.getImm()>>2;
343 assert(MO.isExpr() &&
344 "getJumpTargetOpValue expects only expressions or an immediate");
346 const MCExpr *Expr = MO.getExpr();
347 Fixups.push_back(MCFixup::Create(0, Expr,
348 MCFixupKind(Mips::fixup_Mips_26)));
352 unsigned MipsMCCodeEmitter::
353 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const {
357 const MCOperand &MO = MI.getOperand(OpNo);
358 // If the destination is an immediate, divide by 2.
359 if (MO.isImm()) return MO.getImm() >> 1;
361 assert(MO.isExpr() &&
362 "getJumpTargetOpValueMM expects only expressions or an immediate");
364 const MCExpr *Expr = MO.getExpr();
365 Fixups.push_back(MCFixup::Create(0, Expr,
366 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
370 unsigned MipsMCCodeEmitter::
371 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
372 SmallVectorImpl<MCFixup> &Fixups,
373 const MCSubtargetInfo &STI) const {
375 const MCOperand &MO = MI.getOperand(OpNo);
377 // The immediate is encoded as 'immediate << 2'.
378 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
379 assert((Res & 3) == 0);
383 assert(MO.isExpr() &&
384 "getUImm5Lsl2Encoding expects only expressions or an immediate");
389 unsigned MipsMCCodeEmitter::
390 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const {
394 const MCOperand &MO = MI.getOperand(OpNo);
396 int Value = MO.getImm();
403 unsigned MipsMCCodeEmitter::
404 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
405 SmallVectorImpl<MCFixup> &Fixups,
406 const MCSubtargetInfo &STI) const {
408 const MCOperand &MO = MI.getOperand(OpNo);
410 unsigned Value = MO.getImm();
417 unsigned MipsMCCodeEmitter::
418 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI) const {
422 const MCOperand &MO = MI.getOperand(OpNo);
424 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
425 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
431 unsigned MipsMCCodeEmitter::
432 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
433 const MCSubtargetInfo &STI) const {
436 if (Expr->EvaluateAsAbsolute(Res))
439 MCExpr::ExprKind Kind = Expr->getKind();
440 if (Kind == MCExpr::Constant) {
441 return cast<MCConstantExpr>(Expr)->getValue();
444 if (Kind == MCExpr::Binary) {
445 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
446 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
450 if (Kind == MCExpr::Target) {
451 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
453 Mips::Fixups FixupKind = Mips::Fixups(0);
454 switch (MipsExpr->getKind()) {
455 default: llvm_unreachable("Unsupported fixup kind for target expression!");
456 case MipsMCExpr::VK_Mips_HIGHEST:
457 FixupKind = Mips::fixup_Mips_HIGHEST;
459 case MipsMCExpr::VK_Mips_HIGHER:
460 FixupKind = Mips::fixup_Mips_HIGHER;
462 case MipsMCExpr::VK_Mips_HI:
463 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
464 : Mips::fixup_Mips_HI16;
466 case MipsMCExpr::VK_Mips_LO:
467 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
468 : Mips::fixup_Mips_LO16;
471 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
475 if (Kind == MCExpr::SymbolRef) {
476 Mips::Fixups FixupKind = Mips::Fixups(0);
478 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
479 default: llvm_unreachable("Unknown fixup kind!");
481 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
482 FixupKind = Mips::fixup_Mips_GPOFF_HI;
484 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
485 FixupKind = Mips::fixup_Mips_GPOFF_LO;
487 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
488 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
489 : Mips::fixup_Mips_GOT_PAGE;
491 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
492 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
493 : Mips::fixup_Mips_GOT_OFST;
495 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
496 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
497 : Mips::fixup_Mips_GOT_DISP;
499 case MCSymbolRefExpr::VK_Mips_GPREL:
500 FixupKind = Mips::fixup_Mips_GPREL16;
502 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
503 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
504 : Mips::fixup_Mips_CALL16;
506 case MCSymbolRefExpr::VK_Mips_GOT16:
507 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
508 : Mips::fixup_Mips_GOT_Global;
510 case MCSymbolRefExpr::VK_Mips_GOT:
511 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
512 : Mips::fixup_Mips_GOT_Local;
514 case MCSymbolRefExpr::VK_Mips_ABS_HI:
515 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
516 : Mips::fixup_Mips_HI16;
518 case MCSymbolRefExpr::VK_Mips_ABS_LO:
519 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
520 : Mips::fixup_Mips_LO16;
522 case MCSymbolRefExpr::VK_Mips_TLSGD:
523 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
524 : Mips::fixup_Mips_TLSGD;
526 case MCSymbolRefExpr::VK_Mips_TLSLDM:
527 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
528 : Mips::fixup_Mips_TLSLDM;
530 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
531 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
532 : Mips::fixup_Mips_DTPREL_HI;
534 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
535 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
536 : Mips::fixup_Mips_DTPREL_LO;
538 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
539 FixupKind = Mips::fixup_Mips_GOTTPREL;
541 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
542 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
543 : Mips::fixup_Mips_TPREL_HI;
545 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
546 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
547 : Mips::fixup_Mips_TPREL_LO;
549 case MCSymbolRefExpr::VK_Mips_HIGHER:
550 FixupKind = Mips::fixup_Mips_HIGHER;
552 case MCSymbolRefExpr::VK_Mips_HIGHEST:
553 FixupKind = Mips::fixup_Mips_HIGHEST;
555 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
556 FixupKind = Mips::fixup_Mips_GOT_HI16;
558 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
559 FixupKind = Mips::fixup_Mips_GOT_LO16;
561 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
562 FixupKind = Mips::fixup_Mips_CALL_HI16;
564 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
565 FixupKind = Mips::fixup_Mips_CALL_LO16;
567 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
568 FixupKind = Mips::fixup_MIPS_PCHI16;
570 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
571 FixupKind = Mips::fixup_MIPS_PCLO16;
575 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
581 /// getMachineOpValue - Return binary encoding of operand. If the machine
582 /// operand requires relocation, record the relocation and return zero.
583 unsigned MipsMCCodeEmitter::
584 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
585 SmallVectorImpl<MCFixup> &Fixups,
586 const MCSubtargetInfo &STI) const {
588 unsigned Reg = MO.getReg();
589 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
591 } else if (MO.isImm()) {
592 return static_cast<unsigned>(MO.getImm());
593 } else if (MO.isFPImm()) {
594 return static_cast<unsigned>(APFloat(MO.getFPImm())
595 .bitcastToAPInt().getHiBits(32).getLimitedValue());
597 // MO must be an Expr.
599 return getExprOpValue(MO.getExpr(),Fixups, STI);
602 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
605 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
606 SmallVectorImpl<MCFixup> &Fixups,
607 const MCSubtargetInfo &STI) const {
608 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
609 assert(MI.getOperand(OpNo).isReg());
610 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
611 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
613 // The immediate field of an LD/ST instruction is scaled which means it must
614 // be divided (when encoding) by the size (in bytes) of the instructions'
620 switch(MI.getOpcode())
623 assert (0 && "Unexpected instruction");
627 // We don't need to scale the offset in this case
643 return (OffBits & 0xFFFF) | RegBits;
646 /// getMemEncoding - Return binary encoding of memory related operand.
647 /// If the offset operand requires relocation, record the relocation.
649 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
650 SmallVectorImpl<MCFixup> &Fixups,
651 const MCSubtargetInfo &STI) const {
652 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
653 assert(MI.getOperand(OpNo).isReg());
654 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
655 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
657 return (OffBits & 0xFFFF) | RegBits;
660 unsigned MipsMCCodeEmitter::
661 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
662 SmallVectorImpl<MCFixup> &Fixups,
663 const MCSubtargetInfo &STI) const {
664 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
665 assert(MI.getOperand(OpNo).isReg());
666 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
668 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
671 return (OffBits & 0xF) | RegBits;
674 unsigned MipsMCCodeEmitter::
675 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
676 SmallVectorImpl<MCFixup> &Fixups,
677 const MCSubtargetInfo &STI) const {
678 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
679 assert(MI.getOperand(OpNo).isReg());
680 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
682 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
685 return (OffBits & 0xF) | RegBits;
688 unsigned MipsMCCodeEmitter::
689 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
690 SmallVectorImpl<MCFixup> &Fixups,
691 const MCSubtargetInfo &STI) const {
692 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
693 assert(MI.getOperand(OpNo).isReg());
694 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
696 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
699 return (OffBits & 0xF) | RegBits;
702 unsigned MipsMCCodeEmitter::
703 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
704 SmallVectorImpl<MCFixup> &Fixups,
705 const MCSubtargetInfo &STI) const {
706 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
707 assert(MI.getOperand(OpNo).isReg() &&
708 MI.getOperand(OpNo).getReg() == Mips::SP &&
709 "Unexpected base register!");
710 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
713 return OffBits & 0x1F;
716 unsigned MipsMCCodeEmitter::
717 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
718 SmallVectorImpl<MCFixup> &Fixups,
719 const MCSubtargetInfo &STI) const {
720 // opNum can be invalid if instruction had reglist as operand.
721 // MemOperand is always last operand of instruction (base + offset).
722 switch (MI.getOpcode()) {
727 OpNo = MI.getNumOperands() - 2;
731 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
732 assert(MI.getOperand(OpNo).isReg());
733 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
734 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
736 return (OffBits & 0x0FFF) | RegBits;
739 unsigned MipsMCCodeEmitter::
740 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
741 SmallVectorImpl<MCFixup> &Fixups,
742 const MCSubtargetInfo &STI) const {
743 // opNum can be invalid if instruction had reglist as operand
744 // MemOperand is always last operand of instruction (base + offset)
745 switch (MI.getOpcode()) {
750 OpNo = MI.getNumOperands() - 2;
754 // Offset is encoded in bits 4-0.
755 assert(MI.getOperand(OpNo).isReg());
756 // Base register is always SP - thus it is not encoded.
757 assert(MI.getOperand(OpNo+1).isImm());
758 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
760 return ((OffBits >> 2) & 0x0F);
764 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
765 SmallVectorImpl<MCFixup> &Fixups,
766 const MCSubtargetInfo &STI) const {
767 assert(MI.getOperand(OpNo).isImm());
768 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
769 return SizeEncoding - 1;
772 // FIXME: should be called getMSBEncoding
775 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
776 SmallVectorImpl<MCFixup> &Fixups,
777 const MCSubtargetInfo &STI) const {
778 assert(MI.getOperand(OpNo-1).isImm());
779 assert(MI.getOperand(OpNo).isImm());
780 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
781 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
783 return Position + Size - 1;
787 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
788 SmallVectorImpl<MCFixup> &Fixups,
789 const MCSubtargetInfo &STI) const {
790 assert(MI.getOperand(OpNo).isImm());
791 // The immediate is encoded as 'immediate - 1'.
792 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
796 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
797 SmallVectorImpl<MCFixup> &Fixups,
798 const MCSubtargetInfo &STI) const {
799 const MCOperand &MO = MI.getOperand(OpNo);
801 // The immediate is encoded as 'immediate << 2'.
802 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
803 assert((Res & 3) == 0);
807 assert(MO.isExpr() &&
808 "getSimm19Lsl2Encoding expects only expressions or an immediate");
810 const MCExpr *Expr = MO.getExpr();
811 Fixups.push_back(MCFixup::Create(0, Expr,
812 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
817 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
818 SmallVectorImpl<MCFixup> &Fixups,
819 const MCSubtargetInfo &STI) const {
820 const MCOperand &MO = MI.getOperand(OpNo);
822 // The immediate is encoded as 'immediate << 3'.
823 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
824 assert((Res & 7) == 0);
828 assert(MO.isExpr() &&
829 "getSimm18Lsl2Encoding expects only expressions or an immediate");
831 const MCExpr *Expr = MO.getExpr();
832 Fixups.push_back(MCFixup::Create(0, Expr,
833 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
838 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
839 SmallVectorImpl<MCFixup> &Fixups,
840 const MCSubtargetInfo &STI) const {
841 assert(MI.getOperand(OpNo).isImm());
842 const MCOperand &MO = MI.getOperand(OpNo);
843 return MO.getImm() % 8;
847 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
848 SmallVectorImpl<MCFixup> &Fixups,
849 const MCSubtargetInfo &STI) const {
850 assert(MI.getOperand(OpNo).isImm());
851 const MCOperand &MO = MI.getOperand(OpNo);
852 unsigned Value = MO.getImm();
854 case 128: return 0x0;
867 case 255: return 0xd;
868 case 32768: return 0xe;
869 case 65535: return 0xf;
871 llvm_unreachable("Unexpected value");
875 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
876 SmallVectorImpl<MCFixup> &Fixups,
877 const MCSubtargetInfo &STI) const {
880 // Register list operand is always first operand of instruction and it is
881 // placed before memory operand (register + imm).
883 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
884 unsigned Reg = MI.getOperand(I).getReg();
885 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
895 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
896 SmallVectorImpl<MCFixup> &Fixups,
897 const MCSubtargetInfo &STI) const {
898 return (MI.getNumOperands() - 4);
902 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
903 SmallVectorImpl<MCFixup> &Fixups,
904 const MCSubtargetInfo &STI) const {
905 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
909 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
910 SmallVectorImpl<MCFixup> &Fixups,
911 const MCSubtargetInfo &STI) const {
912 const MCOperand &MO = MI.getOperand(OpNo);
913 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
914 // The immediate is encoded as 'immediate >> 2'.
915 unsigned Res = static_cast<unsigned>(MO.getImm());
916 assert((Res & 3) == 0);
920 #include "MipsGenMCCodeEmitter.inc"