1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "mccodeemitter"
32 #define GET_INSTRMAP_INFO
33 #include "MipsGenInstrInfo.inc"
34 #undef GET_INSTRMAP_INFO
37 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38 const MCRegisterInfo &MRI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
46 return new MipsMCCodeEmitter(MCII, Ctx, true);
48 } // End of namespace llvm.
50 // If the D<shift> instruction has a shift amount that is greater
51 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
52 static void LowerLargeShift(MCInst& Inst) {
54 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
55 assert(Inst.getOperand(2).isImm());
57 int64_t Shift = Inst.getOperand(2).getImm();
63 Inst.getOperand(2).setImm(Shift);
65 switch (Inst.getOpcode()) {
67 // Calling function is not synchronized
68 llvm_unreachable("Unexpected shift instruction");
70 Inst.setOpcode(Mips::DSLL32);
73 Inst.setOpcode(Mips::DSRL32);
76 Inst.setOpcode(Mips::DSRA32);
79 Inst.setOpcode(Mips::DROTR32);
84 // Pick a DEXT or DINS instruction variant based on the pos and size operands
85 static void LowerDextDins(MCInst& InstIn) {
86 int Opcode = InstIn.getOpcode();
88 if (Opcode == Mips::DEXT)
89 assert(InstIn.getNumOperands() == 4 &&
90 "Invalid no. of machine operands for DEXT!");
91 else // Only DEXT and DINS are possible
92 assert(InstIn.getNumOperands() == 5 &&
93 "Invalid no. of machine operands for DINS!");
95 assert(InstIn.getOperand(2).isImm());
96 int64_t pos = InstIn.getOperand(2).getImm();
97 assert(InstIn.getOperand(3).isImm());
98 int64_t size = InstIn.getOperand(3).getImm();
101 if (pos < 32) // DEXT/DINS, do nothing
104 InstIn.getOperand(2).setImm(pos - 32);
105 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
109 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
110 InstIn.getOperand(3).setImm(size - 32);
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
120 return STI.getFeatureBits()[Mips::FeatureMips32r6];
123 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
127 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
128 const MCSubtargetInfo &STI,
129 raw_ostream &OS) const {
130 // Output the instruction encoding in little endian byte order.
131 // Little-endian byte ordering:
132 // mips32r2: 4 | 3 | 2 | 1
133 // microMIPS: 2 | 1 | 4 | 3
134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
135 EmitInstruction(Val >> 16, 2, STI, OS);
136 EmitInstruction(Val, 2, STI, OS);
138 for (unsigned i = 0; i < Size; ++i) {
139 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
140 EmitByte((Val >> Shift) & 0xff, OS);
145 /// encodeInstruction - Emit the instruction.
146 /// Size the instruction with Desc.getSize().
147 void MipsMCCodeEmitter::
148 encodeInstruction(const MCInst &MI, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const
153 // Non-pseudo instructions that get changed for direct object
154 // only based on operand values.
155 // If this list of instructions get much longer we will move
156 // the check to a function call. Until then, this is more efficient.
158 switch (MI.getOpcode()) {
159 // If shift amount is >= 32 it the inst needs to be lowered further
164 LowerLargeShift(TmpInst);
166 // Double extract instruction is chosen by pos and size operands
169 LowerDextDins(TmpInst);
172 unsigned long N = Fixups.size();
173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
175 // Check for unimplemented opcodes.
176 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
177 // so we have to special check for them.
178 unsigned Opcode = TmpInst.getOpcode();
179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
180 (Opcode != Mips::SLL_MM) && !Binary)
181 llvm_unreachable("unimplemented opcode in encodeInstruction()");
184 if (isMicroMips(STI)) {
185 if (isMips32r6(STI)) {
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
188 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
191 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
193 // Check whether it is Dsp instruction.
195 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
197 if (NewOpcode != -1) {
198 if (Fixups.size() > N)
202 TmpInst.setOpcode (NewOpcode);
203 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
207 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
209 // Get byte count of instruction
210 unsigned Size = Desc.getSize();
212 llvm_unreachable("Desc.getSize() returns 0");
214 EmitInstruction(Binary, Size, STI, OS);
217 /// getBranchTargetOpValue - Return binary encoding of the branch
218 /// target operand. If the machine operand requires relocation,
219 /// record the relocation and return zero.
220 unsigned MipsMCCodeEmitter::
221 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
222 SmallVectorImpl<MCFixup> &Fixups,
223 const MCSubtargetInfo &STI) const {
225 const MCOperand &MO = MI.getOperand(OpNo);
227 // If the destination is an immediate, divide by 4.
228 if (MO.isImm()) return MO.getImm() >> 2;
230 assert(MO.isExpr() &&
231 "getBranchTargetOpValue expects only expressions or immediates");
233 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
234 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
235 Fixups.push_back(MCFixup::create(0, FixupExpression,
236 MCFixupKind(Mips::fixup_Mips_PC16)));
240 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
241 /// target operand. If the machine operand requires relocation,
242 /// record the relocation and return zero.
243 unsigned MipsMCCodeEmitter::
244 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
245 SmallVectorImpl<MCFixup> &Fixups,
246 const MCSubtargetInfo &STI) const {
248 const MCOperand &MO = MI.getOperand(OpNo);
250 // If the destination is an immediate, divide by 2.
251 if (MO.isImm()) return MO.getImm() >> 1;
253 assert(MO.isExpr() &&
254 "getBranchTargetOpValueMM expects only expressions or immediates");
256 const MCExpr *Expr = MO.getExpr();
257 Fixups.push_back(MCFixup::create(0, Expr,
258 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
262 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
263 /// 10-bit branch target operand. If the machine operand requires relocation,
264 /// record the relocation and return zero.
265 unsigned MipsMCCodeEmitter::
266 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
267 SmallVectorImpl<MCFixup> &Fixups,
268 const MCSubtargetInfo &STI) const {
270 const MCOperand &MO = MI.getOperand(OpNo);
272 // If the destination is an immediate, divide by 2.
273 if (MO.isImm()) return MO.getImm() >> 1;
275 assert(MO.isExpr() &&
276 "getBranchTargetOpValuePC10 expects only expressions or immediates");
278 const MCExpr *Expr = MO.getExpr();
279 Fixups.push_back(MCFixup::create(0, Expr,
280 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
284 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
285 /// target operand. If the machine operand requires relocation,
286 /// record the relocation and return zero.
287 unsigned MipsMCCodeEmitter::
288 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
289 SmallVectorImpl<MCFixup> &Fixups,
290 const MCSubtargetInfo &STI) const {
292 const MCOperand &MO = MI.getOperand(OpNo);
294 // If the destination is an immediate, divide by 2.
295 if (MO.isImm()) return MO.getImm() >> 1;
297 assert(MO.isExpr() &&
298 "getBranchTargetOpValueMM expects only expressions or immediates");
300 const MCExpr *Expr = MO.getExpr();
301 Fixups.push_back(MCFixup::create(0, Expr,
303 fixup_MICROMIPS_PC16_S1)));
307 /// getBranchTarget21OpValue - Return binary encoding of the branch
308 /// target operand. If the machine operand requires relocation,
309 /// record the relocation and return zero.
310 unsigned MipsMCCodeEmitter::
311 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
312 SmallVectorImpl<MCFixup> &Fixups,
313 const MCSubtargetInfo &STI) const {
315 const MCOperand &MO = MI.getOperand(OpNo);
317 // If the destination is an immediate, divide by 4.
318 if (MO.isImm()) return MO.getImm() >> 2;
320 assert(MO.isExpr() &&
321 "getBranchTarget21OpValue expects only expressions or immediates");
323 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
324 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
325 Fixups.push_back(MCFixup::create(0, FixupExpression,
326 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
330 /// getBranchTarget26OpValue - Return binary encoding of the branch
331 /// target operand. If the machine operand requires relocation,
332 /// record the relocation and return zero.
333 unsigned MipsMCCodeEmitter::
334 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
335 SmallVectorImpl<MCFixup> &Fixups,
336 const MCSubtargetInfo &STI) const {
338 const MCOperand &MO = MI.getOperand(OpNo);
340 // If the destination is an immediate, divide by 4.
341 if (MO.isImm()) return MO.getImm() >> 2;
343 assert(MO.isExpr() &&
344 "getBranchTarget26OpValue expects only expressions or immediates");
346 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
347 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
348 Fixups.push_back(MCFixup::create(0, FixupExpression,
349 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
353 /// getJumpOffset16OpValue - Return binary encoding of the jump
354 /// target operand. If the machine operand requires relocation,
355 /// record the relocation and return zero.
356 unsigned MipsMCCodeEmitter::
357 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
358 SmallVectorImpl<MCFixup> &Fixups,
359 const MCSubtargetInfo &STI) const {
361 const MCOperand &MO = MI.getOperand(OpNo);
363 if (MO.isImm()) return MO.getImm();
365 assert(MO.isExpr() &&
366 "getJumpOffset16OpValue expects only expressions or an immediate");
372 /// getJumpTargetOpValue - Return binary encoding of the jump
373 /// target operand. If the machine operand requires relocation,
374 /// record the relocation and return zero.
375 unsigned MipsMCCodeEmitter::
376 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const {
380 const MCOperand &MO = MI.getOperand(OpNo);
381 // If the destination is an immediate, divide by 4.
382 if (MO.isImm()) return MO.getImm()>>2;
384 assert(MO.isExpr() &&
385 "getJumpTargetOpValue expects only expressions or an immediate");
387 const MCExpr *Expr = MO.getExpr();
388 Fixups.push_back(MCFixup::create(0, Expr,
389 MCFixupKind(Mips::fixup_Mips_26)));
393 unsigned MipsMCCodeEmitter::
394 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
395 SmallVectorImpl<MCFixup> &Fixups,
396 const MCSubtargetInfo &STI) const {
398 const MCOperand &MO = MI.getOperand(OpNo);
399 // If the destination is an immediate, divide by 2.
400 if (MO.isImm()) return MO.getImm() >> 1;
402 assert(MO.isExpr() &&
403 "getJumpTargetOpValueMM expects only expressions or an immediate");
405 const MCExpr *Expr = MO.getExpr();
406 Fixups.push_back(MCFixup::create(0, Expr,
407 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
411 unsigned MipsMCCodeEmitter::
412 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
413 SmallVectorImpl<MCFixup> &Fixups,
414 const MCSubtargetInfo &STI) const {
416 const MCOperand &MO = MI.getOperand(OpNo);
418 // The immediate is encoded as 'immediate << 2'.
419 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
420 assert((Res & 3) == 0);
424 assert(MO.isExpr() &&
425 "getUImm5Lsl2Encoding expects only expressions or an immediate");
430 unsigned MipsMCCodeEmitter::
431 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
432 SmallVectorImpl<MCFixup> &Fixups,
433 const MCSubtargetInfo &STI) const {
435 const MCOperand &MO = MI.getOperand(OpNo);
437 int Value = MO.getImm();
444 unsigned MipsMCCodeEmitter::
445 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
446 SmallVectorImpl<MCFixup> &Fixups,
447 const MCSubtargetInfo &STI) const {
449 const MCOperand &MO = MI.getOperand(OpNo);
451 unsigned Value = MO.getImm();
458 unsigned MipsMCCodeEmitter::
459 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
460 SmallVectorImpl<MCFixup> &Fixups,
461 const MCSubtargetInfo &STI) const {
463 const MCOperand &MO = MI.getOperand(OpNo);
465 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
466 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
472 unsigned MipsMCCodeEmitter::
473 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
474 const MCSubtargetInfo &STI) const {
477 if (Expr->evaluateAsAbsolute(Res))
480 MCExpr::ExprKind Kind = Expr->getKind();
481 if (Kind == MCExpr::Constant) {
482 return cast<MCConstantExpr>(Expr)->getValue();
485 if (Kind == MCExpr::Binary) {
486 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
487 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
491 if (Kind == MCExpr::Target) {
492 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
494 Mips::Fixups FixupKind = Mips::Fixups(0);
495 switch (MipsExpr->getKind()) {
496 default: llvm_unreachable("Unsupported fixup kind for target expression!");
497 case MipsMCExpr::VK_Mips_HIGHEST:
498 FixupKind = Mips::fixup_Mips_HIGHEST;
500 case MipsMCExpr::VK_Mips_HIGHER:
501 FixupKind = Mips::fixup_Mips_HIGHER;
503 case MipsMCExpr::VK_Mips_HI:
504 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
505 : Mips::fixup_Mips_HI16;
507 case MipsMCExpr::VK_Mips_LO:
508 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
509 : Mips::fixup_Mips_LO16;
512 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
516 if (Kind == MCExpr::SymbolRef) {
517 Mips::Fixups FixupKind = Mips::Fixups(0);
519 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
520 default: llvm_unreachable("Unknown fixup kind!");
522 case MCSymbolRefExpr::VK_None:
523 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
525 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
526 FixupKind = Mips::fixup_Mips_GPOFF_HI;
528 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
529 FixupKind = Mips::fixup_Mips_GPOFF_LO;
531 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
532 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
533 : Mips::fixup_Mips_GOT_PAGE;
535 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
536 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
537 : Mips::fixup_Mips_GOT_OFST;
539 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
540 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
541 : Mips::fixup_Mips_GOT_DISP;
543 case MCSymbolRefExpr::VK_Mips_GPREL:
544 FixupKind = Mips::fixup_Mips_GPREL16;
546 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
547 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
548 : Mips::fixup_Mips_CALL16;
550 case MCSymbolRefExpr::VK_Mips_GOT16:
551 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
552 : Mips::fixup_Mips_GOT_Global;
554 case MCSymbolRefExpr::VK_Mips_GOT:
555 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
556 : Mips::fixup_Mips_GOT_Local;
558 case MCSymbolRefExpr::VK_Mips_ABS_HI:
559 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
560 : Mips::fixup_Mips_HI16;
562 case MCSymbolRefExpr::VK_Mips_ABS_LO:
563 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
564 : Mips::fixup_Mips_LO16;
566 case MCSymbolRefExpr::VK_Mips_TLSGD:
567 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
568 : Mips::fixup_Mips_TLSGD;
570 case MCSymbolRefExpr::VK_Mips_TLSLDM:
571 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
572 : Mips::fixup_Mips_TLSLDM;
574 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
575 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
576 : Mips::fixup_Mips_DTPREL_HI;
578 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
579 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
580 : Mips::fixup_Mips_DTPREL_LO;
582 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
583 FixupKind = Mips::fixup_Mips_GOTTPREL;
585 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
586 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
587 : Mips::fixup_Mips_TPREL_HI;
589 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
590 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
591 : Mips::fixup_Mips_TPREL_LO;
593 case MCSymbolRefExpr::VK_Mips_HIGHER:
594 FixupKind = Mips::fixup_Mips_HIGHER;
596 case MCSymbolRefExpr::VK_Mips_HIGHEST:
597 FixupKind = Mips::fixup_Mips_HIGHEST;
599 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
600 FixupKind = Mips::fixup_Mips_GOT_HI16;
602 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
603 FixupKind = Mips::fixup_Mips_GOT_LO16;
605 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
606 FixupKind = Mips::fixup_Mips_CALL_HI16;
608 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
609 FixupKind = Mips::fixup_Mips_CALL_LO16;
611 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
612 FixupKind = Mips::fixup_MIPS_PCHI16;
614 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
615 FixupKind = Mips::fixup_MIPS_PCLO16;
619 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
625 /// getMachineOpValue - Return binary encoding of operand. If the machine
626 /// operand requires relocation, record the relocation and return zero.
627 unsigned MipsMCCodeEmitter::
628 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
629 SmallVectorImpl<MCFixup> &Fixups,
630 const MCSubtargetInfo &STI) const {
632 unsigned Reg = MO.getReg();
633 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
635 } else if (MO.isImm()) {
636 return static_cast<unsigned>(MO.getImm());
637 } else if (MO.isFPImm()) {
638 return static_cast<unsigned>(APFloat(MO.getFPImm())
639 .bitcastToAPInt().getHiBits(32).getLimitedValue());
641 // MO must be an Expr.
643 return getExprOpValue(MO.getExpr(),Fixups, STI);
646 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
649 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
650 SmallVectorImpl<MCFixup> &Fixups,
651 const MCSubtargetInfo &STI) const {
652 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
653 assert(MI.getOperand(OpNo).isReg());
654 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
655 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
657 // The immediate field of an LD/ST instruction is scaled which means it must
658 // be divided (when encoding) by the size (in bytes) of the instructions'
664 switch(MI.getOpcode())
667 assert (0 && "Unexpected instruction");
671 // We don't need to scale the offset in this case
687 return (OffBits & 0xFFFF) | RegBits;
690 /// getMemEncoding - Return binary encoding of memory related operand.
691 /// If the offset operand requires relocation, record the relocation.
693 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
694 SmallVectorImpl<MCFixup> &Fixups,
695 const MCSubtargetInfo &STI) const {
696 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
697 assert(MI.getOperand(OpNo).isReg());
698 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
699 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
701 return (OffBits & 0xFFFF) | RegBits;
704 unsigned MipsMCCodeEmitter::
705 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
706 SmallVectorImpl<MCFixup> &Fixups,
707 const MCSubtargetInfo &STI) const {
708 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
709 assert(MI.getOperand(OpNo).isReg());
710 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
712 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
715 return (OffBits & 0xF) | RegBits;
718 unsigned MipsMCCodeEmitter::
719 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
720 SmallVectorImpl<MCFixup> &Fixups,
721 const MCSubtargetInfo &STI) const {
722 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
723 assert(MI.getOperand(OpNo).isReg());
724 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
726 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
729 return (OffBits & 0xF) | RegBits;
732 unsigned MipsMCCodeEmitter::
733 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
734 SmallVectorImpl<MCFixup> &Fixups,
735 const MCSubtargetInfo &STI) const {
736 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
737 assert(MI.getOperand(OpNo).isReg());
738 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
740 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
743 return (OffBits & 0xF) | RegBits;
746 unsigned MipsMCCodeEmitter::
747 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
748 SmallVectorImpl<MCFixup> &Fixups,
749 const MCSubtargetInfo &STI) const {
750 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
751 assert(MI.getOperand(OpNo).isReg() &&
752 (MI.getOperand(OpNo).getReg() == Mips::SP ||
753 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
754 "Unexpected base register!");
755 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
758 return OffBits & 0x1F;
761 unsigned MipsMCCodeEmitter::
762 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
763 SmallVectorImpl<MCFixup> &Fixups,
764 const MCSubtargetInfo &STI) const {
765 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
766 assert(MI.getOperand(OpNo).isReg() &&
767 MI.getOperand(OpNo).getReg() == Mips::GP &&
768 "Unexpected base register!");
770 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
773 return OffBits & 0x7F;
776 unsigned MipsMCCodeEmitter::
777 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
778 SmallVectorImpl<MCFixup> &Fixups,
779 const MCSubtargetInfo &STI) const {
780 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
781 assert(MI.getOperand(OpNo).isReg());
782 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
784 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
786 return (OffBits & 0x1FF) | RegBits;
789 unsigned MipsMCCodeEmitter::
790 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
791 SmallVectorImpl<MCFixup> &Fixups,
792 const MCSubtargetInfo &STI) const {
793 // opNum can be invalid if instruction had reglist as operand.
794 // MemOperand is always last operand of instruction (base + offset).
795 switch (MI.getOpcode()) {
800 OpNo = MI.getNumOperands() - 2;
804 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
805 assert(MI.getOperand(OpNo).isReg());
806 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
807 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
809 return (OffBits & 0x0FFF) | RegBits;
812 unsigned MipsMCCodeEmitter::
813 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
814 SmallVectorImpl<MCFixup> &Fixups,
815 const MCSubtargetInfo &STI) const {
816 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
817 assert(MI.getOperand(OpNo).isReg());
818 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
820 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
822 return (OffBits & 0xFFFF) | RegBits;
825 unsigned MipsMCCodeEmitter::
826 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
827 SmallVectorImpl<MCFixup> &Fixups,
828 const MCSubtargetInfo &STI) const {
829 // opNum can be invalid if instruction had reglist as operand
830 // MemOperand is always last operand of instruction (base + offset)
831 switch (MI.getOpcode()) {
836 OpNo = MI.getNumOperands() - 2;
840 // Offset is encoded in bits 4-0.
841 assert(MI.getOperand(OpNo).isReg());
842 // Base register is always SP - thus it is not encoded.
843 assert(MI.getOperand(OpNo+1).isImm());
844 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
846 return ((OffBits >> 2) & 0x0F);
850 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
851 SmallVectorImpl<MCFixup> &Fixups,
852 const MCSubtargetInfo &STI) const {
853 assert(MI.getOperand(OpNo).isImm());
854 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
855 return SizeEncoding - 1;
858 // FIXME: should be called getMSBEncoding
861 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
862 SmallVectorImpl<MCFixup> &Fixups,
863 const MCSubtargetInfo &STI) const {
864 assert(MI.getOperand(OpNo-1).isImm());
865 assert(MI.getOperand(OpNo).isImm());
866 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
867 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
869 return Position + Size - 1;
873 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
874 SmallVectorImpl<MCFixup> &Fixups,
875 const MCSubtargetInfo &STI) const {
876 assert(MI.getOperand(OpNo).isImm());
877 // The immediate is encoded as 'immediate - 1'.
878 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
882 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
883 SmallVectorImpl<MCFixup> &Fixups,
884 const MCSubtargetInfo &STI) const {
885 const MCOperand &MO = MI.getOperand(OpNo);
887 // The immediate is encoded as 'immediate << 2'.
888 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
889 assert((Res & 3) == 0);
893 assert(MO.isExpr() &&
894 "getSimm19Lsl2Encoding expects only expressions or an immediate");
896 const MCExpr *Expr = MO.getExpr();
897 Fixups.push_back(MCFixup::create(0, Expr,
898 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
903 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
904 SmallVectorImpl<MCFixup> &Fixups,
905 const MCSubtargetInfo &STI) const {
906 const MCOperand &MO = MI.getOperand(OpNo);
908 // The immediate is encoded as 'immediate << 3'.
909 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
910 assert((Res & 7) == 0);
914 assert(MO.isExpr() &&
915 "getSimm18Lsl2Encoding expects only expressions or an immediate");
917 const MCExpr *Expr = MO.getExpr();
918 Fixups.push_back(MCFixup::create(0, Expr,
919 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
924 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
925 SmallVectorImpl<MCFixup> &Fixups,
926 const MCSubtargetInfo &STI) const {
927 assert(MI.getOperand(OpNo).isImm());
928 const MCOperand &MO = MI.getOperand(OpNo);
929 return MO.getImm() % 8;
933 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
934 SmallVectorImpl<MCFixup> &Fixups,
935 const MCSubtargetInfo &STI) const {
936 assert(MI.getOperand(OpNo).isImm());
937 const MCOperand &MO = MI.getOperand(OpNo);
938 unsigned Value = MO.getImm();
940 case 128: return 0x0;
953 case 255: return 0xd;
954 case 32768: return 0xe;
955 case 65535: return 0xf;
957 llvm_unreachable("Unexpected value");
961 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
962 SmallVectorImpl<MCFixup> &Fixups,
963 const MCSubtargetInfo &STI) const {
966 // Register list operand is always first operand of instruction and it is
967 // placed before memory operand (register + imm).
969 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
970 unsigned Reg = MI.getOperand(I).getReg();
971 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
981 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
982 SmallVectorImpl<MCFixup> &Fixups,
983 const MCSubtargetInfo &STI) const {
984 return (MI.getNumOperands() - 4);
988 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
989 SmallVectorImpl<MCFixup> &Fixups,
990 const MCSubtargetInfo &STI) const {
991 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
995 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
996 SmallVectorImpl<MCFixup> &Fixups,
997 const MCSubtargetInfo &STI) const {
1000 if (MI.getOperand(0).getReg() == Mips::A1 &&
1001 MI.getOperand(1).getReg() == Mips::A2)
1003 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1004 MI.getOperand(1).getReg() == Mips::A3)
1006 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1007 MI.getOperand(1).getReg() == Mips::A3)
1009 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1010 MI.getOperand(1).getReg() == Mips::S5)
1012 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1013 MI.getOperand(1).getReg() == Mips::S6)
1015 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1016 MI.getOperand(1).getReg() == Mips::A1)
1018 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1019 MI.getOperand(1).getReg() == Mips::A2)
1021 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1022 MI.getOperand(1).getReg() == Mips::A3)
1029 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1030 SmallVectorImpl<MCFixup> &Fixups,
1031 const MCSubtargetInfo &STI) const {
1032 const MCOperand &MO = MI.getOperand(OpNo);
1033 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1034 // The immediate is encoded as 'immediate >> 2'.
1035 unsigned Res = static_cast<unsigned>(MO.getImm());
1036 assert((Res & 3) == 0);
1040 #include "MipsGenMCCodeEmitter.inc"