1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
39 return new MipsMCCodeEmitter(MCII, Ctx, false);
42 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
43 const MCRegisterInfo &MRI,
45 return new MipsMCCodeEmitter(MCII, Ctx, true);
47 } // End of namespace llvm.
49 // If the D<shift> instruction has a shift amount that is greater
50 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
51 static void LowerLargeShift(MCInst& Inst) {
53 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
54 assert(Inst.getOperand(2).isImm());
56 int64_t Shift = Inst.getOperand(2).getImm();
62 Inst.getOperand(2).setImm(Shift);
64 switch (Inst.getOpcode()) {
66 // Calling function is not synchronized
67 llvm_unreachable("Unexpected shift instruction");
69 Inst.setOpcode(Mips::DSLL32);
72 Inst.setOpcode(Mips::DSRL32);
75 Inst.setOpcode(Mips::DSRA32);
78 Inst.setOpcode(Mips::DROTR32);
83 // Pick a DEXT or DINS instruction variant based on the pos and size operands
84 static void LowerDextDins(MCInst& InstIn) {
85 int Opcode = InstIn.getOpcode();
87 if (Opcode == Mips::DEXT)
88 assert(InstIn.getNumOperands() == 4 &&
89 "Invalid no. of machine operands for DEXT!");
90 else // Only DEXT and DINS are possible
91 assert(InstIn.getNumOperands() == 5 &&
92 "Invalid no. of machine operands for DINS!");
94 assert(InstIn.getOperand(2).isImm());
95 int64_t pos = InstIn.getOperand(2).getImm();
96 assert(InstIn.getOperand(3).isImm());
97 int64_t size = InstIn.getOperand(3).getImm();
100 if (pos < 32) // DEXT/DINS, do nothing
103 InstIn.getOperand(2).setImm(pos - 32);
104 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
108 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
109 InstIn.getOperand(3).setImm(size - 32);
110 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
114 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
115 return STI.getFeatureBits() & Mips::FeatureMicroMips;
118 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
119 return STI.getFeatureBits() & Mips::FeatureMips32r6;
122 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
126 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
127 const MCSubtargetInfo &STI,
128 raw_ostream &OS) const {
129 // Output the instruction encoding in little endian byte order.
130 // Little-endian byte ordering:
131 // mips32r2: 4 | 3 | 2 | 1
132 // microMIPS: 2 | 1 | 4 | 3
133 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
134 EmitInstruction(Val >> 16, 2, STI, OS);
135 EmitInstruction(Val, 2, STI, OS);
137 for (unsigned i = 0; i < Size; ++i) {
138 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
139 EmitByte((Val >> Shift) & 0xff, OS);
144 /// encodeInstruction - Emit the instruction.
145 /// Size the instruction with Desc.getSize().
146 void MipsMCCodeEmitter::
147 encodeInstruction(const MCInst &MI, raw_ostream &OS,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const
152 // Non-pseudo instructions that get changed for direct object
153 // only based on operand values.
154 // If this list of instructions get much longer we will move
155 // the check to a function call. Until then, this is more efficient.
157 switch (MI.getOpcode()) {
158 // If shift amount is >= 32 it the inst needs to be lowered further
163 LowerLargeShift(TmpInst);
165 // Double extract instruction is chosen by pos and size operands
168 LowerDextDins(TmpInst);
171 unsigned long N = Fixups.size();
172 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
174 // Check for unimplemented opcodes.
175 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
176 // so we have to special check for them.
177 unsigned Opcode = TmpInst.getOpcode();
178 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
179 (Opcode != Mips::SLL_MM) && !Binary)
180 llvm_unreachable("unimplemented opcode in encodeInstruction()");
183 if (isMicroMips(STI)) {
184 if (isMips32r6(STI)) {
185 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
187 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
190 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
192 if (NewOpcode != -1) {
193 if (Fixups.size() > N)
197 TmpInst.setOpcode (NewOpcode);
198 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
202 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
204 // Get byte count of instruction
205 unsigned Size = Desc.getSize();
207 llvm_unreachable("Desc.getSize() returns 0");
209 EmitInstruction(Binary, Size, STI, OS);
212 /// getBranchTargetOpValue - Return binary encoding of the branch
213 /// target operand. If the machine operand requires relocation,
214 /// record the relocation and return zero.
215 unsigned MipsMCCodeEmitter::
216 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
217 SmallVectorImpl<MCFixup> &Fixups,
218 const MCSubtargetInfo &STI) const {
220 const MCOperand &MO = MI.getOperand(OpNo);
222 // If the destination is an immediate, divide by 4.
223 if (MO.isImm()) return MO.getImm() >> 2;
225 assert(MO.isExpr() &&
226 "getBranchTargetOpValue expects only expressions or immediates");
228 const MCExpr *Expr = MO.getExpr();
229 Fixups.push_back(MCFixup::create(0, Expr,
230 MCFixupKind(Mips::fixup_Mips_PC16)));
234 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
235 /// target operand. If the machine operand requires relocation,
236 /// record the relocation and return zero.
237 unsigned MipsMCCodeEmitter::
238 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const {
242 const MCOperand &MO = MI.getOperand(OpNo);
244 // If the destination is an immediate, divide by 2.
245 if (MO.isImm()) return MO.getImm() >> 1;
247 assert(MO.isExpr() &&
248 "getBranchTargetOpValueMM expects only expressions or immediates");
250 const MCExpr *Expr = MO.getExpr();
251 Fixups.push_back(MCFixup::create(0, Expr,
252 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
256 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
257 /// 10-bit branch target operand. If the machine operand requires relocation,
258 /// record the relocation and return zero.
259 unsigned MipsMCCodeEmitter::
260 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
261 SmallVectorImpl<MCFixup> &Fixups,
262 const MCSubtargetInfo &STI) const {
264 const MCOperand &MO = MI.getOperand(OpNo);
266 // If the destination is an immediate, divide by 2.
267 if (MO.isImm()) return MO.getImm() >> 1;
269 assert(MO.isExpr() &&
270 "getBranchTargetOpValuePC10 expects only expressions or immediates");
272 const MCExpr *Expr = MO.getExpr();
273 Fixups.push_back(MCFixup::create(0, Expr,
274 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
278 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
279 /// target operand. If the machine operand requires relocation,
280 /// record the relocation and return zero.
281 unsigned MipsMCCodeEmitter::
282 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
283 SmallVectorImpl<MCFixup> &Fixups,
284 const MCSubtargetInfo &STI) const {
286 const MCOperand &MO = MI.getOperand(OpNo);
288 // If the destination is an immediate, divide by 2.
289 if (MO.isImm()) return MO.getImm() >> 1;
291 assert(MO.isExpr() &&
292 "getBranchTargetOpValueMM expects only expressions or immediates");
294 const MCExpr *Expr = MO.getExpr();
295 Fixups.push_back(MCFixup::create(0, Expr,
297 fixup_MICROMIPS_PC16_S1)));
301 /// getBranchTarget21OpValue - Return binary encoding of the branch
302 /// target operand. If the machine operand requires relocation,
303 /// record the relocation and return zero.
304 unsigned MipsMCCodeEmitter::
305 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
306 SmallVectorImpl<MCFixup> &Fixups,
307 const MCSubtargetInfo &STI) const {
309 const MCOperand &MO = MI.getOperand(OpNo);
311 // If the destination is an immediate, divide by 4.
312 if (MO.isImm()) return MO.getImm() >> 2;
314 assert(MO.isExpr() &&
315 "getBranchTarget21OpValue expects only expressions or immediates");
317 const MCExpr *Expr = MO.getExpr();
318 Fixups.push_back(MCFixup::create(0, Expr,
319 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
323 /// getBranchTarget26OpValue - Return binary encoding of the branch
324 /// target operand. If the machine operand requires relocation,
325 /// record the relocation and return zero.
326 unsigned MipsMCCodeEmitter::
327 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
328 SmallVectorImpl<MCFixup> &Fixups,
329 const MCSubtargetInfo &STI) const {
331 const MCOperand &MO = MI.getOperand(OpNo);
333 // If the destination is an immediate, divide by 4.
334 if (MO.isImm()) return MO.getImm() >> 2;
336 assert(MO.isExpr() &&
337 "getBranchTarget26OpValue expects only expressions or immediates");
339 const MCExpr *Expr = MO.getExpr();
340 Fixups.push_back(MCFixup::create(0, Expr,
341 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
345 /// getJumpOffset16OpValue - Return binary encoding of the jump
346 /// target operand. If the machine operand requires relocation,
347 /// record the relocation and return zero.
348 unsigned MipsMCCodeEmitter::
349 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
350 SmallVectorImpl<MCFixup> &Fixups,
351 const MCSubtargetInfo &STI) const {
353 const MCOperand &MO = MI.getOperand(OpNo);
355 if (MO.isImm()) return MO.getImm();
357 assert(MO.isExpr() &&
358 "getJumpOffset16OpValue expects only expressions or an immediate");
364 /// getJumpTargetOpValue - Return binary encoding of the jump
365 /// target operand. If the machine operand requires relocation,
366 /// record the relocation and return zero.
367 unsigned MipsMCCodeEmitter::
368 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
369 SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const {
372 const MCOperand &MO = MI.getOperand(OpNo);
373 // If the destination is an immediate, divide by 4.
374 if (MO.isImm()) return MO.getImm()>>2;
376 assert(MO.isExpr() &&
377 "getJumpTargetOpValue expects only expressions or an immediate");
379 const MCExpr *Expr = MO.getExpr();
380 Fixups.push_back(MCFixup::create(0, Expr,
381 MCFixupKind(Mips::fixup_Mips_26)));
385 unsigned MipsMCCodeEmitter::
386 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
387 SmallVectorImpl<MCFixup> &Fixups,
388 const MCSubtargetInfo &STI) const {
390 const MCOperand &MO = MI.getOperand(OpNo);
391 // If the destination is an immediate, divide by 2.
392 if (MO.isImm()) return MO.getImm() >> 1;
394 assert(MO.isExpr() &&
395 "getJumpTargetOpValueMM expects only expressions or an immediate");
397 const MCExpr *Expr = MO.getExpr();
398 Fixups.push_back(MCFixup::create(0, Expr,
399 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
403 unsigned MipsMCCodeEmitter::
404 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
405 SmallVectorImpl<MCFixup> &Fixups,
406 const MCSubtargetInfo &STI) const {
408 const MCOperand &MO = MI.getOperand(OpNo);
410 // The immediate is encoded as 'immediate << 2'.
411 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
412 assert((Res & 3) == 0);
416 assert(MO.isExpr() &&
417 "getUImm5Lsl2Encoding expects only expressions or an immediate");
422 unsigned MipsMCCodeEmitter::
423 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
424 SmallVectorImpl<MCFixup> &Fixups,
425 const MCSubtargetInfo &STI) const {
427 const MCOperand &MO = MI.getOperand(OpNo);
429 int Value = MO.getImm();
436 unsigned MipsMCCodeEmitter::
437 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
438 SmallVectorImpl<MCFixup> &Fixups,
439 const MCSubtargetInfo &STI) const {
441 const MCOperand &MO = MI.getOperand(OpNo);
443 unsigned Value = MO.getImm();
450 unsigned MipsMCCodeEmitter::
451 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
452 SmallVectorImpl<MCFixup> &Fixups,
453 const MCSubtargetInfo &STI) const {
455 const MCOperand &MO = MI.getOperand(OpNo);
457 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
458 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
464 unsigned MipsMCCodeEmitter::
465 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
466 const MCSubtargetInfo &STI) const {
469 if (Expr->EvaluateAsAbsolute(Res))
472 MCExpr::ExprKind Kind = Expr->getKind();
473 if (Kind == MCExpr::Constant) {
474 return cast<MCConstantExpr>(Expr)->getValue();
477 if (Kind == MCExpr::Binary) {
478 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
479 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
483 if (Kind == MCExpr::Target) {
484 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
486 Mips::Fixups FixupKind = Mips::Fixups(0);
487 switch (MipsExpr->getKind()) {
488 default: llvm_unreachable("Unsupported fixup kind for target expression!");
489 case MipsMCExpr::VK_Mips_HIGHEST:
490 FixupKind = Mips::fixup_Mips_HIGHEST;
492 case MipsMCExpr::VK_Mips_HIGHER:
493 FixupKind = Mips::fixup_Mips_HIGHER;
495 case MipsMCExpr::VK_Mips_HI:
496 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
497 : Mips::fixup_Mips_HI16;
499 case MipsMCExpr::VK_Mips_LO:
500 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
501 : Mips::fixup_Mips_LO16;
504 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
508 if (Kind == MCExpr::SymbolRef) {
509 Mips::Fixups FixupKind = Mips::Fixups(0);
511 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
512 default: llvm_unreachable("Unknown fixup kind!");
514 case MCSymbolRefExpr::VK_None:
515 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
517 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
518 FixupKind = Mips::fixup_Mips_GPOFF_HI;
520 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
521 FixupKind = Mips::fixup_Mips_GPOFF_LO;
523 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
524 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
525 : Mips::fixup_Mips_GOT_PAGE;
527 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
528 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
529 : Mips::fixup_Mips_GOT_OFST;
531 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
532 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
533 : Mips::fixup_Mips_GOT_DISP;
535 case MCSymbolRefExpr::VK_Mips_GPREL:
536 FixupKind = Mips::fixup_Mips_GPREL16;
538 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
539 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
540 : Mips::fixup_Mips_CALL16;
542 case MCSymbolRefExpr::VK_Mips_GOT16:
543 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
544 : Mips::fixup_Mips_GOT_Global;
546 case MCSymbolRefExpr::VK_Mips_GOT:
547 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
548 : Mips::fixup_Mips_GOT_Local;
550 case MCSymbolRefExpr::VK_Mips_ABS_HI:
551 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
552 : Mips::fixup_Mips_HI16;
554 case MCSymbolRefExpr::VK_Mips_ABS_LO:
555 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
556 : Mips::fixup_Mips_LO16;
558 case MCSymbolRefExpr::VK_Mips_TLSGD:
559 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
560 : Mips::fixup_Mips_TLSGD;
562 case MCSymbolRefExpr::VK_Mips_TLSLDM:
563 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
564 : Mips::fixup_Mips_TLSLDM;
566 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
567 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
568 : Mips::fixup_Mips_DTPREL_HI;
570 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
571 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
572 : Mips::fixup_Mips_DTPREL_LO;
574 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
575 FixupKind = Mips::fixup_Mips_GOTTPREL;
577 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
578 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
579 : Mips::fixup_Mips_TPREL_HI;
581 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
582 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
583 : Mips::fixup_Mips_TPREL_LO;
585 case MCSymbolRefExpr::VK_Mips_HIGHER:
586 FixupKind = Mips::fixup_Mips_HIGHER;
588 case MCSymbolRefExpr::VK_Mips_HIGHEST:
589 FixupKind = Mips::fixup_Mips_HIGHEST;
591 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
592 FixupKind = Mips::fixup_Mips_GOT_HI16;
594 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
595 FixupKind = Mips::fixup_Mips_GOT_LO16;
597 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
598 FixupKind = Mips::fixup_Mips_CALL_HI16;
600 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
601 FixupKind = Mips::fixup_Mips_CALL_LO16;
603 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
604 FixupKind = Mips::fixup_MIPS_PCHI16;
606 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
607 FixupKind = Mips::fixup_MIPS_PCLO16;
611 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
617 /// getMachineOpValue - Return binary encoding of operand. If the machine
618 /// operand requires relocation, record the relocation and return zero.
619 unsigned MipsMCCodeEmitter::
620 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
621 SmallVectorImpl<MCFixup> &Fixups,
622 const MCSubtargetInfo &STI) const {
624 unsigned Reg = MO.getReg();
625 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
627 } else if (MO.isImm()) {
628 return static_cast<unsigned>(MO.getImm());
629 } else if (MO.isFPImm()) {
630 return static_cast<unsigned>(APFloat(MO.getFPImm())
631 .bitcastToAPInt().getHiBits(32).getLimitedValue());
633 // MO must be an Expr.
635 return getExprOpValue(MO.getExpr(),Fixups, STI);
638 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
641 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
642 SmallVectorImpl<MCFixup> &Fixups,
643 const MCSubtargetInfo &STI) const {
644 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
645 assert(MI.getOperand(OpNo).isReg());
646 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
647 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
649 // The immediate field of an LD/ST instruction is scaled which means it must
650 // be divided (when encoding) by the size (in bytes) of the instructions'
656 switch(MI.getOpcode())
659 assert (0 && "Unexpected instruction");
663 // We don't need to scale the offset in this case
679 return (OffBits & 0xFFFF) | RegBits;
682 /// getMemEncoding - Return binary encoding of memory related operand.
683 /// If the offset operand requires relocation, record the relocation.
685 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
686 SmallVectorImpl<MCFixup> &Fixups,
687 const MCSubtargetInfo &STI) const {
688 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
689 assert(MI.getOperand(OpNo).isReg());
690 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
691 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
693 return (OffBits & 0xFFFF) | RegBits;
696 unsigned MipsMCCodeEmitter::
697 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
698 SmallVectorImpl<MCFixup> &Fixups,
699 const MCSubtargetInfo &STI) const {
700 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
701 assert(MI.getOperand(OpNo).isReg());
702 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
704 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
707 return (OffBits & 0xF) | RegBits;
710 unsigned MipsMCCodeEmitter::
711 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
712 SmallVectorImpl<MCFixup> &Fixups,
713 const MCSubtargetInfo &STI) const {
714 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
715 assert(MI.getOperand(OpNo).isReg());
716 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
718 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
721 return (OffBits & 0xF) | RegBits;
724 unsigned MipsMCCodeEmitter::
725 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
726 SmallVectorImpl<MCFixup> &Fixups,
727 const MCSubtargetInfo &STI) const {
728 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
729 assert(MI.getOperand(OpNo).isReg());
730 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
732 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
735 return (OffBits & 0xF) | RegBits;
738 unsigned MipsMCCodeEmitter::
739 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
740 SmallVectorImpl<MCFixup> &Fixups,
741 const MCSubtargetInfo &STI) const {
742 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
743 assert(MI.getOperand(OpNo).isReg() &&
744 MI.getOperand(OpNo).getReg() == Mips::SP &&
745 "Unexpected base register!");
746 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
749 return OffBits & 0x1F;
752 unsigned MipsMCCodeEmitter::
753 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
754 SmallVectorImpl<MCFixup> &Fixups,
755 const MCSubtargetInfo &STI) const {
756 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
757 assert(MI.getOperand(OpNo).isReg() &&
758 MI.getOperand(OpNo).getReg() == Mips::GP &&
759 "Unexpected base register!");
761 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
764 return OffBits & 0x7F;
767 unsigned MipsMCCodeEmitter::
768 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
769 SmallVectorImpl<MCFixup> &Fixups,
770 const MCSubtargetInfo &STI) const {
771 // opNum can be invalid if instruction had reglist as operand.
772 // MemOperand is always last operand of instruction (base + offset).
773 switch (MI.getOpcode()) {
778 OpNo = MI.getNumOperands() - 2;
782 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
783 assert(MI.getOperand(OpNo).isReg());
784 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
785 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
787 return (OffBits & 0x0FFF) | RegBits;
790 unsigned MipsMCCodeEmitter::
791 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
792 SmallVectorImpl<MCFixup> &Fixups,
793 const MCSubtargetInfo &STI) const {
794 // opNum can be invalid if instruction had reglist as operand
795 // MemOperand is always last operand of instruction (base + offset)
796 switch (MI.getOpcode()) {
801 OpNo = MI.getNumOperands() - 2;
805 // Offset is encoded in bits 4-0.
806 assert(MI.getOperand(OpNo).isReg());
807 // Base register is always SP - thus it is not encoded.
808 assert(MI.getOperand(OpNo+1).isImm());
809 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
811 return ((OffBits >> 2) & 0x0F);
815 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
816 SmallVectorImpl<MCFixup> &Fixups,
817 const MCSubtargetInfo &STI) const {
818 assert(MI.getOperand(OpNo).isImm());
819 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
820 return SizeEncoding - 1;
823 // FIXME: should be called getMSBEncoding
826 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
827 SmallVectorImpl<MCFixup> &Fixups,
828 const MCSubtargetInfo &STI) const {
829 assert(MI.getOperand(OpNo-1).isImm());
830 assert(MI.getOperand(OpNo).isImm());
831 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
832 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
834 return Position + Size - 1;
838 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
839 SmallVectorImpl<MCFixup> &Fixups,
840 const MCSubtargetInfo &STI) const {
841 assert(MI.getOperand(OpNo).isImm());
842 // The immediate is encoded as 'immediate - 1'.
843 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
847 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
848 SmallVectorImpl<MCFixup> &Fixups,
849 const MCSubtargetInfo &STI) const {
850 const MCOperand &MO = MI.getOperand(OpNo);
852 // The immediate is encoded as 'immediate << 2'.
853 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
854 assert((Res & 3) == 0);
858 assert(MO.isExpr() &&
859 "getSimm19Lsl2Encoding expects only expressions or an immediate");
861 const MCExpr *Expr = MO.getExpr();
862 Fixups.push_back(MCFixup::create(0, Expr,
863 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
868 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
869 SmallVectorImpl<MCFixup> &Fixups,
870 const MCSubtargetInfo &STI) const {
871 const MCOperand &MO = MI.getOperand(OpNo);
873 // The immediate is encoded as 'immediate << 3'.
874 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
875 assert((Res & 7) == 0);
879 assert(MO.isExpr() &&
880 "getSimm18Lsl2Encoding expects only expressions or an immediate");
882 const MCExpr *Expr = MO.getExpr();
883 Fixups.push_back(MCFixup::create(0, Expr,
884 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
889 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
890 SmallVectorImpl<MCFixup> &Fixups,
891 const MCSubtargetInfo &STI) const {
892 assert(MI.getOperand(OpNo).isImm());
893 const MCOperand &MO = MI.getOperand(OpNo);
894 return MO.getImm() % 8;
898 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
899 SmallVectorImpl<MCFixup> &Fixups,
900 const MCSubtargetInfo &STI) const {
901 assert(MI.getOperand(OpNo).isImm());
902 const MCOperand &MO = MI.getOperand(OpNo);
903 unsigned Value = MO.getImm();
905 case 128: return 0x0;
918 case 255: return 0xd;
919 case 32768: return 0xe;
920 case 65535: return 0xf;
922 llvm_unreachable("Unexpected value");
926 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
927 SmallVectorImpl<MCFixup> &Fixups,
928 const MCSubtargetInfo &STI) const {
931 // Register list operand is always first operand of instruction and it is
932 // placed before memory operand (register + imm).
934 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
935 unsigned Reg = MI.getOperand(I).getReg();
936 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
946 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
947 SmallVectorImpl<MCFixup> &Fixups,
948 const MCSubtargetInfo &STI) const {
949 return (MI.getNumOperands() - 4);
953 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
954 SmallVectorImpl<MCFixup> &Fixups,
955 const MCSubtargetInfo &STI) const {
956 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
960 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
961 SmallVectorImpl<MCFixup> &Fixups,
962 const MCSubtargetInfo &STI) const {
965 if (MI.getOperand(0).getReg() == Mips::A1 &&
966 MI.getOperand(1).getReg() == Mips::A2)
968 else if (MI.getOperand(0).getReg() == Mips::A1 &&
969 MI.getOperand(1).getReg() == Mips::A3)
971 else if (MI.getOperand(0).getReg() == Mips::A2 &&
972 MI.getOperand(1).getReg() == Mips::A3)
974 else if (MI.getOperand(0).getReg() == Mips::A0 &&
975 MI.getOperand(1).getReg() == Mips::S5)
977 else if (MI.getOperand(0).getReg() == Mips::A0 &&
978 MI.getOperand(1).getReg() == Mips::S6)
980 else if (MI.getOperand(0).getReg() == Mips::A0 &&
981 MI.getOperand(1).getReg() == Mips::A1)
983 else if (MI.getOperand(0).getReg() == Mips::A0 &&
984 MI.getOperand(1).getReg() == Mips::A2)
986 else if (MI.getOperand(0).getReg() == Mips::A0 &&
987 MI.getOperand(1).getReg() == Mips::A3)
994 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
995 SmallVectorImpl<MCFixup> &Fixups,
996 const MCSubtargetInfo &STI) const {
997 const MCOperand &MO = MI.getOperand(OpNo);
998 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
999 // The immediate is encoded as 'immediate >> 2'.
1000 unsigned Res = static_cast<unsigned>(MO.getImm());
1001 assert((Res & 3) == 0);
1005 #include "MipsGenMCCodeEmitter.inc"