1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRMAP_INFO
30 #include "MipsGenInstrInfo.inc"
35 class MipsMCCodeEmitter : public MCCodeEmitter {
36 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
45 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
46 const MCSubtargetInfo &sti, bool IsLittle) :
47 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {
48 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
51 ~MipsMCCodeEmitter() {}
53 void EmitByte(unsigned char C, raw_ostream &OS) const {
57 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
58 // Output the instruction encoding in little endian byte order.
59 // Little-endian byte ordering:
60 // mips32r2: 4 | 3 | 2 | 1
61 // microMIPS: 2 | 1 | 4 | 3
62 if (IsLittleEndian && Size == 4 && IsMicroMips) {
63 EmitInstruction(Val>>16, 2, OS);
64 EmitInstruction(Val, 2, OS);
66 for (unsigned i = 0; i < Size; ++i) {
67 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
68 EmitByte((Val >> Shift) & 0xff, OS);
73 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getBinaryCodeForInstr - TableGen'erated function for getting the
77 // binary encoding for an instruction.
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 // getBranchJumpOpValue - Return binary encoding of the jump
82 // target operand. If the machine operand requires relocation,
83 // record the relocation and return zero.
84 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 // getBranchTargetOpValue - Return binary encoding of the branch
88 // target operand. If the machine operand requires relocation,
89 // record the relocation and return zero.
90 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl<MCFixup> &Fixups) const;
93 // getMachineOpValue - Return binary encoding of operand. If the machin
94 // operand requires relocation, record the relocation and return zero.
95 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
96 SmallVectorImpl<MCFixup> &Fixups) const;
98 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
99 SmallVectorImpl<MCFixup> &Fixups) const;
100 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl<MCFixup> &Fixups) const;
102 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
103 SmallVectorImpl<MCFixup> &Fixups) const;
104 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
105 SmallVectorImpl<MCFixup> &Fixups) const;
108 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
110 }; // class MipsMCCodeEmitter
113 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
114 const MCRegisterInfo &MRI,
115 const MCSubtargetInfo &STI,
118 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
121 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
122 const MCRegisterInfo &MRI,
123 const MCSubtargetInfo &STI,
126 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
130 // If the D<shift> instruction has a shift amount that is greater
131 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
132 static void LowerLargeShift(MCInst& Inst) {
134 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
135 assert(Inst.getOperand(2).isImm());
137 int64_t Shift = Inst.getOperand(2).getImm();
139 return; // Do nothing
143 Inst.getOperand(2).setImm(Shift);
145 switch (Inst.getOpcode()) {
147 // Calling function is not synchronized
148 llvm_unreachable("Unexpected shift instruction");
150 Inst.setOpcode(Mips::DSLL32);
153 Inst.setOpcode(Mips::DSRL32);
156 Inst.setOpcode(Mips::DSRA32);
159 Inst.setOpcode(Mips::DROTR32);
164 // Pick a DEXT or DINS instruction variant based on the pos and size operands
165 static void LowerDextDins(MCInst& InstIn) {
166 int Opcode = InstIn.getOpcode();
168 if (Opcode == Mips::DEXT)
169 assert(InstIn.getNumOperands() == 4 &&
170 "Invalid no. of machine operands for DEXT!");
171 else // Only DEXT and DINS are possible
172 assert(InstIn.getNumOperands() == 5 &&
173 "Invalid no. of machine operands for DINS!");
175 assert(InstIn.getOperand(2).isImm());
176 int64_t pos = InstIn.getOperand(2).getImm();
177 assert(InstIn.getOperand(3).isImm());
178 int64_t size = InstIn.getOperand(3).getImm();
181 if (pos < 32) // DEXT/DINS, do nothing
184 InstIn.getOperand(2).setImm(pos - 32);
185 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
189 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
190 InstIn.getOperand(3).setImm(size - 32);
191 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
195 /// EncodeInstruction - Emit the instruction.
196 /// Size the instruction with Desc.getSize().
197 void MipsMCCodeEmitter::
198 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
199 SmallVectorImpl<MCFixup> &Fixups) const
202 // Non-pseudo instructions that get changed for direct object
203 // only based on operand values.
204 // If this list of instructions get much longer we will move
205 // the check to a function call. Until then, this is more efficient.
207 switch (MI.getOpcode()) {
208 // If shift amount is >= 32 it the inst needs to be lowered further
213 LowerLargeShift(TmpInst);
215 // Double extract instruction is chosen by pos and size operands
218 LowerDextDins(TmpInst);
221 unsigned long N = Fixups.size();
222 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
224 // Check for unimplemented opcodes.
225 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
226 // so we have to special check for them.
227 unsigned Opcode = TmpInst.getOpcode();
228 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
229 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
231 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
232 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
233 if (NewOpcode != -1) {
234 if (Fixups.size() > N)
237 TmpInst.setOpcode (NewOpcode);
238 Binary = getBinaryCodeForInstr(TmpInst, Fixups);
242 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
244 // Get byte count of instruction
245 unsigned Size = Desc.getSize();
247 llvm_unreachable("Desc.getSize() returns 0");
249 EmitInstruction(Binary, Size, OS);
252 /// getBranchTargetOpValue - Return binary encoding of the branch
253 /// target operand. If the machine operand requires relocation,
254 /// record the relocation and return zero.
255 unsigned MipsMCCodeEmitter::
256 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
257 SmallVectorImpl<MCFixup> &Fixups) const {
259 const MCOperand &MO = MI.getOperand(OpNo);
261 // If the destination is an immediate, divide by 4.
262 if (MO.isImm()) return MO.getImm() >> 2;
264 assert(MO.isExpr() &&
265 "getBranchTargetOpValue expects only expressions or immediates");
267 const MCExpr *Expr = MO.getExpr();
268 Fixups.push_back(MCFixup::Create(0, Expr,
269 MCFixupKind(Mips::fixup_Mips_PC16)));
273 /// getJumpTargetOpValue - Return binary encoding of the jump
274 /// target operand. If the machine operand requires relocation,
275 /// record the relocation and return zero.
276 unsigned MipsMCCodeEmitter::
277 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
278 SmallVectorImpl<MCFixup> &Fixups) const {
280 const MCOperand &MO = MI.getOperand(OpNo);
281 // If the destination is an immediate, divide by 4.
282 if (MO.isImm()) return MO.getImm()>>2;
284 assert(MO.isExpr() &&
285 "getJumpTargetOpValue expects only expressions or an immediate");
287 const MCExpr *Expr = MO.getExpr();
288 Fixups.push_back(MCFixup::Create(0, Expr,
289 MCFixupKind(Mips::fixup_Mips_26)));
293 unsigned MipsMCCodeEmitter::
294 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
297 if (Expr->EvaluateAsAbsolute(Res))
300 MCExpr::ExprKind Kind = Expr->getKind();
301 if (Kind == MCExpr::Constant) {
302 return cast<MCConstantExpr>(Expr)->getValue();
305 if (Kind == MCExpr::Binary) {
306 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
307 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
310 if (Kind == MCExpr::SymbolRef) {
311 Mips::Fixups FixupKind = Mips::Fixups(0);
313 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
314 default: llvm_unreachable("Unknown fixup kind!");
316 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
317 FixupKind = Mips::fixup_Mips_GPOFF_HI;
319 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
320 FixupKind = Mips::fixup_Mips_GPOFF_LO;
322 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
323 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_PAGE
324 : Mips::fixup_Mips_GOT_PAGE;
326 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
327 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_OFST
328 : Mips::fixup_Mips_GOT_OFST;
330 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
331 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_DISP
332 : Mips::fixup_Mips_GOT_DISP;
334 case MCSymbolRefExpr::VK_Mips_GPREL:
335 FixupKind = Mips::fixup_Mips_GPREL16;
337 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
338 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_CALL16
339 : Mips::fixup_Mips_CALL16;
341 case MCSymbolRefExpr::VK_Mips_GOT16:
342 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
343 : Mips::fixup_Mips_GOT_Global;
345 case MCSymbolRefExpr::VK_Mips_GOT:
346 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
347 : Mips::fixup_Mips_GOT_Local;
349 case MCSymbolRefExpr::VK_Mips_ABS_HI:
350 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_HI16
351 : Mips::fixup_Mips_HI16;
353 case MCSymbolRefExpr::VK_Mips_ABS_LO:
354 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_LO16
355 : Mips::fixup_Mips_LO16;
357 case MCSymbolRefExpr::VK_Mips_TLSGD:
358 FixupKind = Mips::fixup_Mips_TLSGD;
360 case MCSymbolRefExpr::VK_Mips_TLSLDM:
361 FixupKind = Mips::fixup_Mips_TLSLDM;
363 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
364 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
365 : Mips::fixup_Mips_DTPREL_HI;
367 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
368 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
369 : Mips::fixup_Mips_DTPREL_LO;
371 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
372 FixupKind = Mips::fixup_Mips_GOTTPREL;
374 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
375 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
376 : Mips::fixup_Mips_TPREL_HI;
378 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
379 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
380 : Mips::fixup_Mips_TPREL_LO;
382 case MCSymbolRefExpr::VK_Mips_HIGHER:
383 FixupKind = Mips::fixup_Mips_HIGHER;
385 case MCSymbolRefExpr::VK_Mips_HIGHEST:
386 FixupKind = Mips::fixup_Mips_HIGHEST;
388 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
389 FixupKind = Mips::fixup_Mips_GOT_HI16;
391 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
392 FixupKind = Mips::fixup_Mips_GOT_LO16;
394 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
395 FixupKind = Mips::fixup_Mips_CALL_HI16;
397 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
398 FixupKind = Mips::fixup_Mips_CALL_LO16;
402 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
408 /// getMachineOpValue - Return binary encoding of operand. If the machine
409 /// operand requires relocation, record the relocation and return zero.
410 unsigned MipsMCCodeEmitter::
411 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
412 SmallVectorImpl<MCFixup> &Fixups) const {
414 unsigned Reg = MO.getReg();
415 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
417 } else if (MO.isImm()) {
418 return static_cast<unsigned>(MO.getImm());
419 } else if (MO.isFPImm()) {
420 return static_cast<unsigned>(APFloat(MO.getFPImm())
421 .bitcastToAPInt().getHiBits(32).getLimitedValue());
423 // MO must be an Expr.
425 return getExprOpValue(MO.getExpr(),Fixups);
428 /// getMemEncoding - Return binary encoding of memory related operand.
429 /// If the offset operand requires relocation, record the relocation.
431 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
432 SmallVectorImpl<MCFixup> &Fixups) const {
433 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
434 assert(MI.getOperand(OpNo).isReg());
435 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
436 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
438 return (OffBits & 0xFFFF) | RegBits;
441 unsigned MipsMCCodeEmitter::
442 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
443 SmallVectorImpl<MCFixup> &Fixups) const {
444 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
445 assert(MI.getOperand(OpNo).isReg());
446 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16;
447 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
449 return (OffBits & 0x0FFF) | RegBits;
453 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
454 SmallVectorImpl<MCFixup> &Fixups) const {
455 assert(MI.getOperand(OpNo).isImm());
456 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
457 return SizeEncoding - 1;
460 // FIXME: should be called getMSBEncoding
463 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
464 SmallVectorImpl<MCFixup> &Fixups) const {
465 assert(MI.getOperand(OpNo-1).isImm());
466 assert(MI.getOperand(OpNo).isImm());
467 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
468 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
470 return Position + Size - 1;
473 #include "MipsGenMCCodeEmitter.inc"