1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
177 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
179 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181 if (NewOpcode != -1) {
182 if (Fixups.size() > N)
185 TmpInst.setOpcode (NewOpcode);
186 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
190 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
192 // Get byte count of instruction
193 unsigned Size = Desc.getSize();
195 llvm_unreachable("Desc.getSize() returns 0");
197 EmitInstruction(Binary, Size, STI, OS);
200 /// getBranchTargetOpValue - Return binary encoding of the branch
201 /// target operand. If the machine operand requires relocation,
202 /// record the relocation and return zero.
203 unsigned MipsMCCodeEmitter::
204 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
205 SmallVectorImpl<MCFixup> &Fixups,
206 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
210 // If the destination is an immediate, divide by 4.
211 if (MO.isImm()) return MO.getImm() >> 2;
213 assert(MO.isExpr() &&
214 "getBranchTargetOpValue expects only expressions or immediates");
216 const MCExpr *Expr = MO.getExpr();
217 Fixups.push_back(MCFixup::Create(0, Expr,
218 MCFixupKind(Mips::fixup_Mips_PC16)));
222 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
223 /// target operand. If the machine operand requires relocation,
224 /// record the relocation and return zero.
225 unsigned MipsMCCodeEmitter::
226 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const {
230 const MCOperand &MO = MI.getOperand(OpNo);
232 // If the destination is an immediate, divide by 2.
233 if (MO.isImm()) return MO.getImm() >> 1;
235 assert(MO.isExpr() &&
236 "getBranchTargetOpValueMM expects only expressions or immediates");
238 const MCExpr *Expr = MO.getExpr();
239 Fixups.push_back(MCFixup::Create(0, Expr,
241 fixup_MICROMIPS_PC16_S1)));
245 /// getBranchTarget21OpValue - Return binary encoding of the branch
246 /// target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const {
253 const MCOperand &MO = MI.getOperand(OpNo);
255 // If the destination is an immediate, divide by 4.
256 if (MO.isImm()) return MO.getImm() >> 2;
258 assert(MO.isExpr() &&
259 "getBranchTarget21OpValue expects only expressions or immediates");
261 const MCExpr *Expr = MO.getExpr();
262 Fixups.push_back(MCFixup::Create(0, Expr,
263 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
267 /// getBranchTarget26OpValue - Return binary encoding of the branch
268 /// target operand. If the machine operand requires relocation,
269 /// record the relocation and return zero.
270 unsigned MipsMCCodeEmitter::
271 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
275 const MCOperand &MO = MI.getOperand(OpNo);
277 // If the destination is an immediate, divide by 4.
278 if (MO.isImm()) return MO.getImm() >> 2;
280 assert(MO.isExpr() &&
281 "getBranchTarget26OpValue expects only expressions or immediates");
283 const MCExpr *Expr = MO.getExpr();
284 Fixups.push_back(MCFixup::Create(0, Expr,
285 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
289 /// getJumpOffset16OpValue - Return binary encoding of the jump
290 /// target operand. If the machine operand requires relocation,
291 /// record the relocation and return zero.
292 unsigned MipsMCCodeEmitter::
293 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
294 SmallVectorImpl<MCFixup> &Fixups,
295 const MCSubtargetInfo &STI) const {
297 const MCOperand &MO = MI.getOperand(OpNo);
299 if (MO.isImm()) return MO.getImm();
301 assert(MO.isExpr() &&
302 "getJumpOffset16OpValue expects only expressions or an immediate");
308 /// getJumpTargetOpValue - Return binary encoding of the jump
309 /// target operand. If the machine operand requires relocation,
310 /// record the relocation and return zero.
311 unsigned MipsMCCodeEmitter::
312 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
313 SmallVectorImpl<MCFixup> &Fixups,
314 const MCSubtargetInfo &STI) const {
316 const MCOperand &MO = MI.getOperand(OpNo);
317 // If the destination is an immediate, divide by 4.
318 if (MO.isImm()) return MO.getImm()>>2;
320 assert(MO.isExpr() &&
321 "getJumpTargetOpValue expects only expressions or an immediate");
323 const MCExpr *Expr = MO.getExpr();
324 Fixups.push_back(MCFixup::Create(0, Expr,
325 MCFixupKind(Mips::fixup_Mips_26)));
329 unsigned MipsMCCodeEmitter::
330 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const {
334 const MCOperand &MO = MI.getOperand(OpNo);
335 // If the destination is an immediate, divide by 2.
336 if (MO.isImm()) return MO.getImm() >> 1;
338 assert(MO.isExpr() &&
339 "getJumpTargetOpValueMM expects only expressions or an immediate");
341 const MCExpr *Expr = MO.getExpr();
342 Fixups.push_back(MCFixup::Create(0, Expr,
343 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
347 unsigned MipsMCCodeEmitter::
348 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
349 SmallVectorImpl<MCFixup> &Fixups,
350 const MCSubtargetInfo &STI) const {
352 const MCOperand &MO = MI.getOperand(OpNo);
354 // The immediate is encoded as 'immediate << 2'.
355 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
356 assert((Res & 3) == 0);
360 assert(MO.isExpr() &&
361 "getUImm5Lsl2Encoding expects only expressions or an immediate");
366 unsigned MipsMCCodeEmitter::
367 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI) const {
371 const MCOperand &MO = MI.getOperand(OpNo);
373 int Value = MO.getImm();
380 unsigned MipsMCCodeEmitter::
381 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
382 SmallVectorImpl<MCFixup> &Fixups,
383 const MCSubtargetInfo &STI) const {
385 const MCOperand &MO = MI.getOperand(OpNo);
387 unsigned Value = MO.getImm();
394 unsigned MipsMCCodeEmitter::
395 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
396 SmallVectorImpl<MCFixup> &Fixups,
397 const MCSubtargetInfo &STI) const {
399 const MCOperand &MO = MI.getOperand(OpNo);
401 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
402 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
408 unsigned MipsMCCodeEmitter::
409 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
410 const MCSubtargetInfo &STI) const {
413 if (Expr->EvaluateAsAbsolute(Res))
416 MCExpr::ExprKind Kind = Expr->getKind();
417 if (Kind == MCExpr::Constant) {
418 return cast<MCConstantExpr>(Expr)->getValue();
421 if (Kind == MCExpr::Binary) {
422 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
423 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
427 if (Kind == MCExpr::Target) {
428 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
430 Mips::Fixups FixupKind = Mips::Fixups(0);
431 switch (MipsExpr->getKind()) {
432 default: llvm_unreachable("Unsupported fixup kind for target expression!");
433 case MipsMCExpr::VK_Mips_HIGHEST:
434 FixupKind = Mips::fixup_Mips_HIGHEST;
436 case MipsMCExpr::VK_Mips_HIGHER:
437 FixupKind = Mips::fixup_Mips_HIGHER;
439 case MipsMCExpr::VK_Mips_HI:
440 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
441 : Mips::fixup_Mips_HI16;
443 case MipsMCExpr::VK_Mips_LO:
444 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
445 : Mips::fixup_Mips_LO16;
448 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
452 if (Kind == MCExpr::SymbolRef) {
453 Mips::Fixups FixupKind = Mips::Fixups(0);
455 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
456 default: llvm_unreachable("Unknown fixup kind!");
458 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
459 FixupKind = Mips::fixup_Mips_GPOFF_HI;
461 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
462 FixupKind = Mips::fixup_Mips_GPOFF_LO;
464 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
465 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
466 : Mips::fixup_Mips_GOT_PAGE;
468 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
469 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
470 : Mips::fixup_Mips_GOT_OFST;
472 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
473 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
474 : Mips::fixup_Mips_GOT_DISP;
476 case MCSymbolRefExpr::VK_Mips_GPREL:
477 FixupKind = Mips::fixup_Mips_GPREL16;
479 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
480 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
481 : Mips::fixup_Mips_CALL16;
483 case MCSymbolRefExpr::VK_Mips_GOT16:
484 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
485 : Mips::fixup_Mips_GOT_Global;
487 case MCSymbolRefExpr::VK_Mips_GOT:
488 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
489 : Mips::fixup_Mips_GOT_Local;
491 case MCSymbolRefExpr::VK_Mips_ABS_HI:
492 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
493 : Mips::fixup_Mips_HI16;
495 case MCSymbolRefExpr::VK_Mips_ABS_LO:
496 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
497 : Mips::fixup_Mips_LO16;
499 case MCSymbolRefExpr::VK_Mips_TLSGD:
500 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
501 : Mips::fixup_Mips_TLSGD;
503 case MCSymbolRefExpr::VK_Mips_TLSLDM:
504 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
505 : Mips::fixup_Mips_TLSLDM;
507 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
508 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
509 : Mips::fixup_Mips_DTPREL_HI;
511 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
512 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
513 : Mips::fixup_Mips_DTPREL_LO;
515 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
516 FixupKind = Mips::fixup_Mips_GOTTPREL;
518 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
519 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
520 : Mips::fixup_Mips_TPREL_HI;
522 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
523 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
524 : Mips::fixup_Mips_TPREL_LO;
526 case MCSymbolRefExpr::VK_Mips_HIGHER:
527 FixupKind = Mips::fixup_Mips_HIGHER;
529 case MCSymbolRefExpr::VK_Mips_HIGHEST:
530 FixupKind = Mips::fixup_Mips_HIGHEST;
532 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
533 FixupKind = Mips::fixup_Mips_GOT_HI16;
535 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
536 FixupKind = Mips::fixup_Mips_GOT_LO16;
538 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
539 FixupKind = Mips::fixup_Mips_CALL_HI16;
541 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
542 FixupKind = Mips::fixup_Mips_CALL_LO16;
544 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
545 FixupKind = Mips::fixup_MIPS_PCHI16;
547 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
548 FixupKind = Mips::fixup_MIPS_PCLO16;
552 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
558 /// getMachineOpValue - Return binary encoding of operand. If the machine
559 /// operand requires relocation, record the relocation and return zero.
560 unsigned MipsMCCodeEmitter::
561 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
562 SmallVectorImpl<MCFixup> &Fixups,
563 const MCSubtargetInfo &STI) const {
565 unsigned Reg = MO.getReg();
566 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
568 } else if (MO.isImm()) {
569 return static_cast<unsigned>(MO.getImm());
570 } else if (MO.isFPImm()) {
571 return static_cast<unsigned>(APFloat(MO.getFPImm())
572 .bitcastToAPInt().getHiBits(32).getLimitedValue());
574 // MO must be an Expr.
576 return getExprOpValue(MO.getExpr(),Fixups, STI);
579 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
582 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
583 SmallVectorImpl<MCFixup> &Fixups,
584 const MCSubtargetInfo &STI) const {
585 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
586 assert(MI.getOperand(OpNo).isReg());
587 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
588 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
590 // The immediate field of an LD/ST instruction is scaled which means it must
591 // be divided (when encoding) by the size (in bytes) of the instructions'
597 switch(MI.getOpcode())
600 assert (0 && "Unexpected instruction");
604 // We don't need to scale the offset in this case
620 return (OffBits & 0xFFFF) | RegBits;
623 /// getMemEncoding - Return binary encoding of memory related operand.
624 /// If the offset operand requires relocation, record the relocation.
626 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
627 SmallVectorImpl<MCFixup> &Fixups,
628 const MCSubtargetInfo &STI) const {
629 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
630 assert(MI.getOperand(OpNo).isReg());
631 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
632 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
634 return (OffBits & 0xFFFF) | RegBits;
637 unsigned MipsMCCodeEmitter::
638 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
639 SmallVectorImpl<MCFixup> &Fixups,
640 const MCSubtargetInfo &STI) const {
641 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
642 assert(MI.getOperand(OpNo).isReg());
643 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
645 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
648 return (OffBits & 0xF) | RegBits;
651 unsigned MipsMCCodeEmitter::
652 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
653 SmallVectorImpl<MCFixup> &Fixups,
654 const MCSubtargetInfo &STI) const {
655 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
656 assert(MI.getOperand(OpNo).isReg());
657 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
659 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
662 return (OffBits & 0xF) | RegBits;
665 unsigned MipsMCCodeEmitter::
666 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
667 SmallVectorImpl<MCFixup> &Fixups,
668 const MCSubtargetInfo &STI) const {
669 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
670 assert(MI.getOperand(OpNo).isReg());
671 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
673 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
676 return (OffBits & 0xF) | RegBits;
679 unsigned MipsMCCodeEmitter::
680 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
681 SmallVectorImpl<MCFixup> &Fixups,
682 const MCSubtargetInfo &STI) const {
683 // opNum can be invalid if instruction had reglist as operand.
684 // MemOperand is always last operand of instruction (base + offset).
685 switch (MI.getOpcode()) {
690 OpNo = MI.getNumOperands() - 2;
694 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
695 assert(MI.getOperand(OpNo).isReg());
696 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
697 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
699 return (OffBits & 0x0FFF) | RegBits;
702 unsigned MipsMCCodeEmitter::
703 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
704 SmallVectorImpl<MCFixup> &Fixups,
705 const MCSubtargetInfo &STI) const {
706 // opNum can be invalid if instruction had reglist as operand
707 // MemOperand is always last operand of instruction (base + offset)
708 switch (MI.getOpcode()) {
713 OpNo = MI.getNumOperands() - 2;
717 // Offset is encoded in bits 4-0.
718 assert(MI.getOperand(OpNo).isReg());
719 // Base register is always SP - thus it is not encoded.
720 assert(MI.getOperand(OpNo+1).isImm());
721 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
723 return ((OffBits >> 2) & 0x0F);
727 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
728 SmallVectorImpl<MCFixup> &Fixups,
729 const MCSubtargetInfo &STI) const {
730 assert(MI.getOperand(OpNo).isImm());
731 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
732 return SizeEncoding - 1;
735 // FIXME: should be called getMSBEncoding
738 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
739 SmallVectorImpl<MCFixup> &Fixups,
740 const MCSubtargetInfo &STI) const {
741 assert(MI.getOperand(OpNo-1).isImm());
742 assert(MI.getOperand(OpNo).isImm());
743 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
744 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
746 return Position + Size - 1;
750 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
751 SmallVectorImpl<MCFixup> &Fixups,
752 const MCSubtargetInfo &STI) const {
753 assert(MI.getOperand(OpNo).isImm());
754 // The immediate is encoded as 'immediate - 1'.
755 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
759 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
760 SmallVectorImpl<MCFixup> &Fixups,
761 const MCSubtargetInfo &STI) const {
762 const MCOperand &MO = MI.getOperand(OpNo);
764 // The immediate is encoded as 'immediate << 2'.
765 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
766 assert((Res & 3) == 0);
770 assert(MO.isExpr() &&
771 "getSimm19Lsl2Encoding expects only expressions or an immediate");
773 const MCExpr *Expr = MO.getExpr();
774 Fixups.push_back(MCFixup::Create(0, Expr,
775 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
780 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
781 SmallVectorImpl<MCFixup> &Fixups,
782 const MCSubtargetInfo &STI) const {
783 const MCOperand &MO = MI.getOperand(OpNo);
785 // The immediate is encoded as 'immediate << 3'.
786 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
787 assert((Res & 7) == 0);
791 assert(MO.isExpr() &&
792 "getSimm18Lsl2Encoding expects only expressions or an immediate");
794 const MCExpr *Expr = MO.getExpr();
795 Fixups.push_back(MCFixup::Create(0, Expr,
796 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
801 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
802 SmallVectorImpl<MCFixup> &Fixups,
803 const MCSubtargetInfo &STI) const {
804 assert(MI.getOperand(OpNo).isImm());
805 const MCOperand &MO = MI.getOperand(OpNo);
806 return MO.getImm() % 8;
810 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
811 SmallVectorImpl<MCFixup> &Fixups,
812 const MCSubtargetInfo &STI) const {
813 assert(MI.getOperand(OpNo).isImm());
814 const MCOperand &MO = MI.getOperand(OpNo);
815 unsigned Value = MO.getImm();
817 case 128: return 0x0;
830 case 255: return 0xd;
831 case 32768: return 0xe;
832 case 65535: return 0xf;
834 llvm_unreachable("Unexpected value");
838 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
839 SmallVectorImpl<MCFixup> &Fixups,
840 const MCSubtargetInfo &STI) const {
843 // Register list operand is always first operand of instruction and it is
844 // placed before memory operand (register + imm).
846 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
847 unsigned Reg = MI.getOperand(I).getReg();
848 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
858 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
859 SmallVectorImpl<MCFixup> &Fixups,
860 const MCSubtargetInfo &STI) const {
861 return (MI.getNumOperands() - 4);
864 #include "MipsGenMCCodeEmitter.inc"