1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
177 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
179 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181 if (NewOpcode != -1) {
182 if (Fixups.size() > N)
185 TmpInst.setOpcode (NewOpcode);
186 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
190 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
192 // Get byte count of instruction
193 unsigned Size = Desc.getSize();
195 llvm_unreachable("Desc.getSize() returns 0");
197 EmitInstruction(Binary, Size, STI, OS);
200 /// getBranchTargetOpValue - Return binary encoding of the branch
201 /// target operand. If the machine operand requires relocation,
202 /// record the relocation and return zero.
203 unsigned MipsMCCodeEmitter::
204 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
205 SmallVectorImpl<MCFixup> &Fixups,
206 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
210 // If the destination is an immediate, divide by 4.
211 if (MO.isImm()) return MO.getImm() >> 2;
213 assert(MO.isExpr() &&
214 "getBranchTargetOpValue expects only expressions or immediates");
216 const MCExpr *Expr = MO.getExpr();
217 Fixups.push_back(MCFixup::Create(0, Expr,
218 MCFixupKind(Mips::fixup_Mips_PC16)));
222 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
223 /// target operand. If the machine operand requires relocation,
224 /// record the relocation and return zero.
225 unsigned MipsMCCodeEmitter::
226 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const {
230 const MCOperand &MO = MI.getOperand(OpNo);
232 // If the destination is an immediate, divide by 2.
233 if (MO.isImm()) return MO.getImm() >> 1;
235 assert(MO.isExpr() &&
236 "getBranchTargetOpValueMM expects only expressions or immediates");
238 const MCExpr *Expr = MO.getExpr();
239 Fixups.push_back(MCFixup::Create(0, Expr,
241 fixup_MICROMIPS_PC16_S1)));
245 /// getBranchTarget21OpValue - Return binary encoding of the branch
246 /// target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const {
253 const MCOperand &MO = MI.getOperand(OpNo);
255 // If the destination is an immediate, divide by 4.
256 if (MO.isImm()) return MO.getImm() >> 2;
258 assert(MO.isExpr() &&
259 "getBranchTarget21OpValue expects only expressions or immediates");
261 const MCExpr *Expr = MO.getExpr();
262 Fixups.push_back(MCFixup::Create(0, Expr,
263 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
267 /// getBranchTarget26OpValue - Return binary encoding of the branch
268 /// target operand. If the machine operand requires relocation,
269 /// record the relocation and return zero.
270 unsigned MipsMCCodeEmitter::
271 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
275 const MCOperand &MO = MI.getOperand(OpNo);
277 // If the destination is an immediate, divide by 4.
278 if (MO.isImm()) return MO.getImm() >> 2;
280 assert(MO.isExpr() &&
281 "getBranchTarget26OpValue expects only expressions or immediates");
283 const MCExpr *Expr = MO.getExpr();
284 Fixups.push_back(MCFixup::Create(0, Expr,
285 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
289 /// getJumpOffset16OpValue - Return binary encoding of the jump
290 /// target operand. If the machine operand requires relocation,
291 /// record the relocation and return zero.
292 unsigned MipsMCCodeEmitter::
293 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
294 SmallVectorImpl<MCFixup> &Fixups,
295 const MCSubtargetInfo &STI) const {
297 const MCOperand &MO = MI.getOperand(OpNo);
299 if (MO.isImm()) return MO.getImm();
301 assert(MO.isExpr() &&
302 "getJumpOffset16OpValue expects only expressions or an immediate");
308 /// getJumpTargetOpValue - Return binary encoding of the jump
309 /// target operand. If the machine operand requires relocation,
310 /// record the relocation and return zero.
311 unsigned MipsMCCodeEmitter::
312 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
313 SmallVectorImpl<MCFixup> &Fixups,
314 const MCSubtargetInfo &STI) const {
316 const MCOperand &MO = MI.getOperand(OpNo);
317 // If the destination is an immediate, divide by 4.
318 if (MO.isImm()) return MO.getImm()>>2;
320 assert(MO.isExpr() &&
321 "getJumpTargetOpValue expects only expressions or an immediate");
323 const MCExpr *Expr = MO.getExpr();
324 Fixups.push_back(MCFixup::Create(0, Expr,
325 MCFixupKind(Mips::fixup_Mips_26)));
329 unsigned MipsMCCodeEmitter::
330 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const {
334 const MCOperand &MO = MI.getOperand(OpNo);
335 // If the destination is an immediate, divide by 2.
336 if (MO.isImm()) return MO.getImm() >> 1;
338 assert(MO.isExpr() &&
339 "getJumpTargetOpValueMM expects only expressions or an immediate");
341 const MCExpr *Expr = MO.getExpr();
342 Fixups.push_back(MCFixup::Create(0, Expr,
343 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
347 unsigned MipsMCCodeEmitter::
348 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const {
352 if (Expr->EvaluateAsAbsolute(Res))
355 MCExpr::ExprKind Kind = Expr->getKind();
356 if (Kind == MCExpr::Constant) {
357 return cast<MCConstantExpr>(Expr)->getValue();
360 if (Kind == MCExpr::Binary) {
361 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
362 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
366 if (Kind == MCExpr::Target) {
367 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
369 Mips::Fixups FixupKind = Mips::Fixups(0);
370 switch (MipsExpr->getKind()) {
371 default: llvm_unreachable("Unsupported fixup kind for target expression!");
372 case MipsMCExpr::VK_Mips_HIGHEST:
373 FixupKind = Mips::fixup_Mips_HIGHEST;
375 case MipsMCExpr::VK_Mips_HIGHER:
376 FixupKind = Mips::fixup_Mips_HIGHER;
378 case MipsMCExpr::VK_Mips_HI:
379 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
380 : Mips::fixup_Mips_HI16;
382 case MipsMCExpr::VK_Mips_LO:
383 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
384 : Mips::fixup_Mips_LO16;
387 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
391 if (Kind == MCExpr::SymbolRef) {
392 Mips::Fixups FixupKind = Mips::Fixups(0);
394 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
395 default: llvm_unreachable("Unknown fixup kind!");
397 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
398 FixupKind = Mips::fixup_Mips_GPOFF_HI;
400 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
401 FixupKind = Mips::fixup_Mips_GPOFF_LO;
403 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
404 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
405 : Mips::fixup_Mips_GOT_PAGE;
407 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
408 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
409 : Mips::fixup_Mips_GOT_OFST;
411 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
412 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
413 : Mips::fixup_Mips_GOT_DISP;
415 case MCSymbolRefExpr::VK_Mips_GPREL:
416 FixupKind = Mips::fixup_Mips_GPREL16;
418 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
419 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
420 : Mips::fixup_Mips_CALL16;
422 case MCSymbolRefExpr::VK_Mips_GOT16:
423 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
424 : Mips::fixup_Mips_GOT_Global;
426 case MCSymbolRefExpr::VK_Mips_GOT:
427 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
428 : Mips::fixup_Mips_GOT_Local;
430 case MCSymbolRefExpr::VK_Mips_ABS_HI:
431 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
432 : Mips::fixup_Mips_HI16;
434 case MCSymbolRefExpr::VK_Mips_ABS_LO:
435 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
436 : Mips::fixup_Mips_LO16;
438 case MCSymbolRefExpr::VK_Mips_TLSGD:
439 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
440 : Mips::fixup_Mips_TLSGD;
442 case MCSymbolRefExpr::VK_Mips_TLSLDM:
443 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
444 : Mips::fixup_Mips_TLSLDM;
446 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
447 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
448 : Mips::fixup_Mips_DTPREL_HI;
450 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
451 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
452 : Mips::fixup_Mips_DTPREL_LO;
454 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
455 FixupKind = Mips::fixup_Mips_GOTTPREL;
457 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
458 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
459 : Mips::fixup_Mips_TPREL_HI;
461 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
462 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
463 : Mips::fixup_Mips_TPREL_LO;
465 case MCSymbolRefExpr::VK_Mips_HIGHER:
466 FixupKind = Mips::fixup_Mips_HIGHER;
468 case MCSymbolRefExpr::VK_Mips_HIGHEST:
469 FixupKind = Mips::fixup_Mips_HIGHEST;
471 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
472 FixupKind = Mips::fixup_Mips_GOT_HI16;
474 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
475 FixupKind = Mips::fixup_Mips_GOT_LO16;
477 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
478 FixupKind = Mips::fixup_Mips_CALL_HI16;
480 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
481 FixupKind = Mips::fixup_Mips_CALL_LO16;
485 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
491 /// getMachineOpValue - Return binary encoding of operand. If the machine
492 /// operand requires relocation, record the relocation and return zero.
493 unsigned MipsMCCodeEmitter::
494 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
495 SmallVectorImpl<MCFixup> &Fixups,
496 const MCSubtargetInfo &STI) const {
498 unsigned Reg = MO.getReg();
499 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
501 } else if (MO.isImm()) {
502 return static_cast<unsigned>(MO.getImm());
503 } else if (MO.isFPImm()) {
504 return static_cast<unsigned>(APFloat(MO.getFPImm())
505 .bitcastToAPInt().getHiBits(32).getLimitedValue());
507 // MO must be an Expr.
509 return getExprOpValue(MO.getExpr(),Fixups, STI);
512 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
515 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
516 SmallVectorImpl<MCFixup> &Fixups,
517 const MCSubtargetInfo &STI) const {
518 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
519 assert(MI.getOperand(OpNo).isReg());
520 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
521 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
523 // The immediate field of an LD/ST instruction is scaled which means it must
524 // be divided (when encoding) by the size (in bytes) of the instructions'
530 switch(MI.getOpcode())
533 assert (0 && "Unexpected instruction");
537 // We don't need to scale the offset in this case
553 return (OffBits & 0xFFFF) | RegBits;
556 /// getMemEncoding - Return binary encoding of memory related operand.
557 /// If the offset operand requires relocation, record the relocation.
559 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
560 SmallVectorImpl<MCFixup> &Fixups,
561 const MCSubtargetInfo &STI) const {
562 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
563 assert(MI.getOperand(OpNo).isReg());
564 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
565 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
567 return (OffBits & 0xFFFF) | RegBits;
570 unsigned MipsMCCodeEmitter::
571 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
572 SmallVectorImpl<MCFixup> &Fixups,
573 const MCSubtargetInfo &STI) const {
574 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
575 assert(MI.getOperand(OpNo).isReg());
576 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
577 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
579 return (OffBits & 0x0FFF) | RegBits;
583 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
584 SmallVectorImpl<MCFixup> &Fixups,
585 const MCSubtargetInfo &STI) const {
586 assert(MI.getOperand(OpNo).isImm());
587 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
588 return SizeEncoding - 1;
591 // FIXME: should be called getMSBEncoding
594 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
595 SmallVectorImpl<MCFixup> &Fixups,
596 const MCSubtargetInfo &STI) const {
597 assert(MI.getOperand(OpNo-1).isImm());
598 assert(MI.getOperand(OpNo).isImm());
599 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
600 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
602 return Position + Size - 1;
606 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
607 SmallVectorImpl<MCFixup> &Fixups,
608 const MCSubtargetInfo &STI) const {
609 assert(MI.getOperand(OpNo).isImm());
610 // The immediate is encoded as 'immediate - 1'.
611 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
615 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
616 SmallVectorImpl<MCFixup> &Fixups,
617 const MCSubtargetInfo &STI) const {
618 assert(MI.getOperand(OpNo).isImm());
619 // The immediate is encoded as 'immediate << 2'.
620 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
621 assert((Res & 3) == 0);
625 #include "MipsGenMCCodeEmitter.inc"