1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend class.
12 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsAsmBackend.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 // Prepare value for the target space for it
33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
34 MCContext *Ctx = NULL) {
36 unsigned Kind = Fixup.getKind();
38 // Add/subtract and shift
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16:
55 case Mips::fixup_MICROMIPS_LO16:
56 case Mips::fixup_MICROMIPS_GOT_PAGE:
57 case Mips::fixup_MICROMIPS_GOT_OFST:
58 case Mips::fixup_MICROMIPS_GOT_DISP:
60 case Mips::fixup_Mips_PC16:
61 // So far we are only using this type for branches.
62 // For branches we start 1 instruction after the branch
63 // so the displacement will be one instruction size less.
65 // The displacement is then divided by 4 to give us an 18 bit
66 // address range. Forcing a signed division because Value can be negative.
67 Value = (int64_t)Value / 4;
68 // We now check if Value can be encoded as a 16-bit signed immediate.
69 if (!isIntN(16, Value) && Ctx)
70 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
72 case Mips::fixup_Mips_26:
73 // So far we are only using this type for jumps.
74 // The displacement is then divided by 4 to give us an 28 bit
78 case Mips::fixup_Mips_HI16:
79 case Mips::fixup_Mips_GOT_Local:
80 case Mips::fixup_Mips_GOT_HI16:
81 case Mips::fixup_Mips_CALL_HI16:
82 case Mips::fixup_MICROMIPS_HI16:
83 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
84 Value = ((Value + 0x8000) >> 16) & 0xffff;
86 case Mips::fixup_Mips_HIGHER:
87 // Get the 3rd 16-bits.
88 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
90 case Mips::fixup_Mips_HIGHEST:
91 // Get the 4th 16-bits.
92 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
94 case Mips::fixup_MICROMIPS_26_S1:
97 case Mips::fixup_MICROMIPS_PC16_S1:
99 // Forcing a signed division because Value can be negative.
100 Value = (int64_t)Value / 2;
101 // We now check if Value can be encoded as a 16-bit signed immediate.
102 if (!isIntN(16, Value) && Ctx)
103 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
110 MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
111 return createMipsELFObjectWriter(OS,
112 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
115 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
116 /// data fragment, at the offset specified by the fixup and following the
117 /// fixup kind as appropriate.
118 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
119 unsigned DataSize, uint64_t Value) const {
120 MCFixupKind Kind = Fixup.getKind();
121 Value = adjustFixupValue(Fixup, Value);
124 return; // Doesn't change encoding.
126 // Where do we start in the object
127 unsigned Offset = Fixup.getOffset();
128 // Number of bytes we need to fixup
129 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
130 // Used to point to big endian bytes
133 switch ((unsigned)Kind) {
135 case Mips::fixup_Mips_16:
139 case Mips::fixup_Mips_64:
148 // Grab current value, if any, from bits.
151 for (unsigned i = 0; i != NumBytes; ++i) {
152 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
153 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
156 uint64_t Mask = ((uint64_t)(-1) >>
157 (64 - getFixupKindInfo(Kind).TargetSize));
158 CurVal |= Value & Mask;
160 // Write out the fixed up bytes back to the code/data bits.
161 for (unsigned i = 0; i != NumBytes; ++i) {
162 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
163 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
167 const MCFixupKindInfo &MipsAsmBackend::
168 getFixupKindInfo(MCFixupKind Kind) const {
169 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
170 // This table *must* be in same the order of fixup_* kinds in
173 // name offset bits flags
174 { "fixup_Mips_16", 0, 16, 0 },
175 { "fixup_Mips_32", 0, 32, 0 },
176 { "fixup_Mips_REL32", 0, 32, 0 },
177 { "fixup_Mips_26", 0, 26, 0 },
178 { "fixup_Mips_HI16", 0, 16, 0 },
179 { "fixup_Mips_LO16", 0, 16, 0 },
180 { "fixup_Mips_GPREL16", 0, 16, 0 },
181 { "fixup_Mips_LITERAL", 0, 16, 0 },
182 { "fixup_Mips_GOT_Global", 0, 16, 0 },
183 { "fixup_Mips_GOT_Local", 0, 16, 0 },
184 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
185 { "fixup_Mips_CALL16", 0, 16, 0 },
186 { "fixup_Mips_GPREL32", 0, 32, 0 },
187 { "fixup_Mips_SHIFT5", 6, 5, 0 },
188 { "fixup_Mips_SHIFT6", 6, 5, 0 },
189 { "fixup_Mips_64", 0, 64, 0 },
190 { "fixup_Mips_TLSGD", 0, 16, 0 },
191 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
192 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
193 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
194 { "fixup_Mips_TLSLDM", 0, 16, 0 },
195 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
196 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
197 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
198 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
199 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
200 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
201 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
202 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
203 { "fixup_Mips_HIGHER", 0, 16, 0 },
204 { "fixup_Mips_HIGHEST", 0, 16, 0 },
205 { "fixup_Mips_GOT_HI16", 0, 16, 0 },
206 { "fixup_Mips_GOT_LO16", 0, 16, 0 },
207 { "fixup_Mips_CALL_HI16", 0, 16, 0 },
208 { "fixup_Mips_CALL_LO16", 0, 16, 0 },
209 { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
210 { "fixup_MICROMIPS_HI16", 0, 16, 0 },
211 { "fixup_MICROMIPS_LO16", 0, 16, 0 },
212 { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
213 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
214 { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
215 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
216 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
217 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
218 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
219 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
220 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
221 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
222 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
223 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
226 if (Kind < FirstTargetFixupKind)
227 return MCAsmBackend::getFixupKindInfo(Kind);
229 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
231 return Infos[Kind - FirstTargetFixupKind];
234 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
235 /// to the given output. If the target cannot generate such a sequence,
236 /// it should return an error.
238 /// \return - True on success.
239 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
240 // Check for a less than instruction size number of bytes
241 // FIXME: 16 bit instructions are not handled yet here.
242 // We shouldn't be using a hard coded number for instruction size.
243 if (Count % 4) return false;
245 uint64_t NumNops = Count / 4;
246 for (uint64_t i = 0; i != NumNops; ++i)
251 /// processFixupValue - Target hook to process the literal value of a fixup
253 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
254 const MCAsmLayout &Layout,
255 const MCFixup &Fixup,
256 const MCFragment *DF,
260 // At this point we'll ignore the value returned by adjustFixupValue as
261 // we are only checking if the fixup can be applied correctly. We have
262 // access to MCContext from here which allows us to report a fatal error
263 // with *possibly* a source code location.
264 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
268 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
269 const MCRegisterInfo &MRI,
272 return new MipsAsmBackend(T, Triple(TT).getOS(),
273 /*IsLittle*/true, /*Is64Bit*/false);
276 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
277 const MCRegisterInfo &MRI,
280 return new MipsAsmBackend(T, Triple(TT).getOS(),
281 /*IsLittle*/false, /*Is64Bit*/false);
284 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
285 const MCRegisterInfo &MRI,
288 return new MipsAsmBackend(T, Triple(TT).getOS(),
289 /*IsLittle*/true, /*Is64Bit*/true);
292 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
293 const MCRegisterInfo &MRI,
296 return new MipsAsmBackend(T, Triple(TT).getOS(),
297 /*IsLittle*/false, /*Is64Bit*/true);