1 //===-- MipsASMBackend.cpp - ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
12 //===----------------------------------------------------------------------===//
15 #include "MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCDirectives.h"
21 #include "llvm/MC/MCELFObjectWriter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCMachObjectWriter.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSectionELF.h"
26 #include "llvm/MC/MCSectionMachO.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Object/MachOFormat.h"
29 #include "llvm/Support/ELF.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
34 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
36 // Add/subtract and shift
40 case Mips::fixup_Mips_PC16:
41 // So far we are only using this type for branches.
42 // For branches we start 1 instruction after the branch
43 // so the displacement will be one instruction size less.
45 // The displacement is then divided by 4 to give us an 18 bit
49 case Mips::fixup_Mips_26:
50 // So far we are only using this type for jumps.
51 // The displacement is then divided by 4 to give us an 28 bit
57 // Mask off value for placement as an operand
65 case Mips::fixup_Mips_26:
68 case Mips::fixup_Mips_LO16:
69 case Mips::fixup_Mips_PC16:
72 case Mips::fixup_Mips_HI16:
82 class MipsELFObjectWriter : public MCELFObjectTargetWriter {
84 MipsELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
85 bool HasRelocationAddend)
86 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine,
87 HasRelocationAddend) {}
90 class MipsAsmBackend : public MCAsmBackend {
92 MipsAsmBackend(const Target &T) : MCAsmBackend() {}
94 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
95 /// data fragment, at the offset specified by the fixup and following the
96 /// fixup kind as appropriate.
97 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
98 uint64_t Value) const {
99 unsigned Kind = (unsigned)Fixup.getKind();
100 Value = adjustFixupValue(Kind, Value);
103 return; // Doesn't change encoding.
105 unsigned Offset = Fixup.getOffset();
108 llvm_unreachable("Unknown fixup kind!");
109 case Mips::fixup_Mips_GOT16: // This will be fixed up at link time
113 case Mips::fixup_Mips_26:
114 case Mips::fixup_Mips_LO16:
115 case Mips::fixup_Mips_PC16:
116 case Mips::fixup_Mips_HI16:
117 // For each byte of the fragment that the fixup touches, mask i
118 // the fixup value. The Value has been "split up" into the appr
120 for (unsigned i = 0; i != 4; ++i) // FIXME - Need to support 2 and 8 bytes
121 Data[Offset + i] += uint8_t((Value >> (i * 8)) & 0xff);
126 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
128 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
129 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
130 // This table *must* be in the order that the fixup_* kinds a
133 // name offset bits flags
134 { "fixup_Mips_NONE", 0, 0, 0 },
135 { "fixup_Mips_16", 0, 16, 0 },
136 { "fixup_Mips_32", 0, 32, 0 },
137 { "fixup_Mips_REL32", 0, 32, 0 },
138 { "fixup_Mips_26", 0, 26, 0 },
139 { "fixup_Mips_HI16", 0, 16, 0 },
140 { "fixup_Mips_LO16", 0, 16, 0 },
141 { "fixup_Mips_GPREL16", 0, 16, 0 },
142 { "fixup_Mips_LITERAL", 0, 16, 0 },
143 { "fixup_Mips_GOT16", 0, 16, 0 },
144 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
145 { "fixup_Mips_CALL16", 0, 16, 0 },
146 { "fixup_Mips_GPREL32", 0, 32, 0 },
147 { "fixup_Mips_SHIFT5", 6, 5, 0 },
148 { "fixup_Mips_SHIFT6", 6, 5, 0 },
149 { "fixup_Mips_64", 0, 64, 0 },
150 { "fixup_Mips_TLSGD", 0, 16, 0 },
151 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
152 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
153 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
154 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
157 if (Kind < FirstTargetFixupKind)
158 return MCAsmBackend::getFixupKindInfo(Kind);
160 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
162 return Infos[Kind - FirstTargetFixupKind];
165 /// @name Target Relaxation Interfaces
168 /// MayNeedRelaxation - Check whether the given instruction may need
171 /// \param Inst - The instruction to test.
172 bool MayNeedRelaxation(const MCInst &Inst) const {
176 /// fixupNeedsRelaxation - Target specific predicate for whether a given
177 /// fixup requires the associated instruction to be relaxed.
178 bool fixupNeedsRelaxation(const MCFixup &Fixup,
180 const MCInstFragment *DF,
181 const MCAsmLayout &Layout) const {
183 assert(0 && "RelaxInstruction() unimplemented");
186 /// RelaxInstruction - Relax the instruction in the given fragment
187 /// to the next wider instruction.
189 /// \param Inst - The instruction to relax, which may be the same
191 /// \parm Res [output] - On return, the relaxed instruction.
192 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
197 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
198 /// to the given output. If the target cannot generate such a sequence,
199 /// it should return an error.
201 /// \return - True on success.
202 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
207 class MipsEB_AsmBackend : public MipsAsmBackend {
209 Triple::OSType OSType;
211 MipsEB_AsmBackend(const Target &T, Triple::OSType _OSType)
212 : MipsAsmBackend(T), OSType(_OSType) {}
214 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
215 return createELFObjectWriter(createELFObjectTargetWriter(),
216 OS, /*IsLittleEndian*/ false);
219 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
220 return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
224 class MipsEL_AsmBackend : public MipsAsmBackend {
226 Triple::OSType OSType;
228 MipsEL_AsmBackend(const Target &T, Triple::OSType _OSType)
229 : MipsAsmBackend(T), OSType(_OSType) {}
231 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
232 return createELFObjectWriter(createELFObjectTargetWriter(),
233 OS, /*IsLittleEndian*/ true);
236 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
237 return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
242 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, StringRef TT) {
243 Triple TheTriple(TT);
245 // just return little endian for now
247 return new MipsEL_AsmBackend(T, Triple(TT).getOS());