lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 234                                           unsigned Offset,
 235                                           uint64_t Address,
 236                                           const void *Decoder);
 237
 238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 241                                            unsigned Offset,
 242                                            uint64_t Address,
 243                                            const void *Decoder);
 244
 245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 246 // shifted left by 1 bit.
 247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 248                                          unsigned Offset,
 249                                          uint64_t Address,
 250                                          const void *Decoder);
 251
 252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 253 // shifted left by 1 bit.
 254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 255                                        unsigned Insn,
 256                                        uint64_t Address,
 257                                        const void *Decoder);
 258
 259 static DecodeStatus DecodeMem(MCInst &Inst,
 260                               unsigned Insn,
 261                               uint64_t Address,
 262                               const void *Decoder);
 263
 264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 265                               unsigned Insn,
 266                               uint64_t Address,
 267                               const void *Decoder);
 268
 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeSyncI(MCInst &Inst,
 275                                 unsigned Insn,
 276                                 uint64_t Address,
 277                                 const void *Decoder);
 278
 279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 280                                     uint64_t Address, const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 283                                     unsigned Insn,
 284                                     uint64_t Address,
 285                                     const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 288                                           unsigned Insn,
 289                                           uint64_t Address,
 290                                           const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 293                                      unsigned Insn,
 294                                      uint64_t Address,
 295                                      const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 298                                      unsigned Insn,
 299                                      uint64_t Address,
 300                                      const void *Decoder);
 301
 302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 303                                uint64_t Address,
 304                                const void *Decoder);
 305
 306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 307                                uint64_t Address,
 308                                const void *Decoder);
 309
 310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 311                                uint64_t Address,
 312                                const void *Decoder);
 313
 314 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 315                                uint64_t Address,
 316                                const void *Decoder);
 317
 318 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 319                                        unsigned Insn,
 320                                        uint64_t Address,
 321                                        const void *Decoder);
 322
 323 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 324                                        unsigned Value,
 325                                        uint64_t Address,
 326                                        const void *Decoder);
 327
 328 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 329                                     unsigned Value,
 330                                     uint64_t Address,
 331                                     const void *Decoder);
 332
 333 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 334                                   unsigned Value,
 335                                   uint64_t Address,
 336                                   const void *Decoder);
 337
 338 static DecodeStatus DecodeSimm4(MCInst &Inst,
 339                                 unsigned Value,
 340                                 uint64_t Address,
 341                                 const void *Decoder);
 342
 343 static DecodeStatus DecodeSimm16(MCInst &Inst,
 344                                  unsigned Insn,
 345                                  uint64_t Address,
 346                                  const void *Decoder);
 347
 348 // Decode the immediate field of an LSA instruction which
 349 // is off by one.
 350 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 351                                  unsigned Insn,
 352                                  uint64_t Address,
 353                                  const void *Decoder);
 354
 355 static DecodeStatus DecodeInsSize(MCInst &Inst,
 356                                   unsigned Insn,
 357                                   uint64_t Address,
 358                                   const void *Decoder);
 359
 360 static DecodeStatus DecodeExtSize(MCInst &Inst,
 361                                   unsigned Insn,
 362                                   uint64_t Address,
 363                                   const void *Decoder);
 364
 365 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 366                                      uint64_t Address, const void *Decoder);
 367
 368 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 369                                      uint64_t Address, const void *Decoder);
 370
 371 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 372                                   uint64_t Address, const void *Decoder);
 373
 374 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 375                                     uint64_t Address, const void *Decoder);
 376
 377 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 378                                    uint64_t Address, const void *Decoder);
 379
 380 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 381                                      uint64_t Address, const void *Decoder);
 382
 383 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 384 /// handle.
 385 template <typename InsnType>
 386 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 387                                    const void *Decoder);
 388
 389 template <typename InsnType>
 390 static DecodeStatus
 391 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 392                       const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                        const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                        const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                       const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                        const void *Decoder);
 418
 419 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 420                                          uint64_t Address,
 421                                          const void *Decoder);
 422
 423 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 424                                            uint64_t Address,
 425                                            const void *Decoder);
 426
 427 namespace llvm {
 428 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 429               TheMips64elTarget;
 430 }
 431
 432 static MCDisassembler *createMipsDisassembler(
 433                        const Target &T,
 434                        const MCSubtargetInfo &STI,
 435                        MCContext &Ctx) {
 436   return new MipsDisassembler(STI, Ctx, true);
 437 }
 438
 439 static MCDisassembler *createMipselDisassembler(
 440                        const Target &T,
 441                        const MCSubtargetInfo &STI,
 442                        MCContext &Ctx) {
 443   return new MipsDisassembler(STI, Ctx, false);
 444 }
 445
 446 static MCDisassembler *createMips64Disassembler(
 447                        const Target &T,
 448                        const MCSubtargetInfo &STI,
 449                        MCContext &Ctx) {
 450   return new Mips64Disassembler(STI, Ctx, true);
 451 }
 452
 453 static MCDisassembler *createMips64elDisassembler(
 454                        const Target &T,
 455                        const MCSubtargetInfo &STI,
 456                        MCContext &Ctx) {
 457   return new Mips64Disassembler(STI, Ctx, false);
 458 }
 459
 460 extern "C" void LLVMInitializeMipsDisassembler() {
 461   // Register the disassembler.
 462   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 463                                          createMipsDisassembler);
 464   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 465                                          createMipselDisassembler);
 466   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 467                                          createMips64Disassembler);
 468   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 469                                          createMips64elDisassembler);
 470 }
 471
 472 #include "MipsGenDisassemblerTables.inc"
 473
 474 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 475   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 476   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 477   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 478 }
 479
 480 template <typename InsnType>
 481 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 482                                    const void *Decoder) {
 483   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 484   // The size of the n field depends on the element size
 485   // The register class also depends on this.
 486   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 487   unsigned NSize = 0;
 488   DecodeFN RegDecoder = nullptr;
 489   if ((tmp & 0x18) == 0x00) { // INSVE_B
 490     NSize = 4;
 491     RegDecoder = DecodeMSA128BRegisterClass;
 492   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 493     NSize = 3;
 494     RegDecoder = DecodeMSA128HRegisterClass;
 495   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 496     NSize = 2;
 497     RegDecoder = DecodeMSA128WRegisterClass;
 498   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 499     NSize = 1;
 500     RegDecoder = DecodeMSA128DRegisterClass;
 501   } else
 502     llvm_unreachable("Invalid encoding");
 503
 504   assert(NSize != 0 && RegDecoder != nullptr);
 505
 506   // $wd
 507   tmp = fieldFromInstruction(insn, 6, 5);
 508   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 509     return MCDisassembler::Fail;
 510   // $wd_in
 511   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 512     return MCDisassembler::Fail;
 513   // $n
 514   tmp = fieldFromInstruction(insn, 16, NSize);
 515   MI.addOperand(MCOperand::CreateImm(tmp));
 516   // $ws
 517   tmp = fieldFromInstruction(insn, 11, 5);
 518   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 519     return MCDisassembler::Fail;
 520   // $n2
 521   MI.addOperand(MCOperand::CreateImm(0));
 522
 523   return MCDisassembler::Success;
 524 }
 525
 526 template <typename InsnType>
 527 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 528                                           uint64_t Address,
 529                                           const void *Decoder) {
 530   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 531   // (otherwise we would have matched the ADDI instruction from the earlier
 532   // ISA's instead).
 533   //
 534   // We have:
 535   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 536   //      BOVC if rs >= rt
 537   //      BEQZALC if rs == 0 && rt != 0
 538   //      BEQC if rs < rt && rs != 0
 539
 540   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 541   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 542   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 543   bool HasRs = false;
 544
 545   if (Rs >= Rt) {
 546     MI.setOpcode(Mips::BOVC);
 547     HasRs = true;
 548   } else if (Rs != 0 && Rs < Rt) {
 549     MI.setOpcode(Mips::BEQC);
 550     HasRs = true;
 551   } else
 552     MI.setOpcode(Mips::BEQZALC);
 553
 554   if (HasRs)
 555     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 556                                        Rs)));
 557
 558   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 559                                      Rt)));
 560   MI.addOperand(MCOperand::CreateImm(Imm));
 561
 562   return MCDisassembler::Success;
 563 }
 564
 565 template <typename InsnType>
 566 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 567                                            uint64_t Address,
 568                                            const void *Decoder) {
 569   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 570   // (otherwise we would have matched the ADDI instruction from the earlier
 571   // ISA's instead).
 572   //
 573   // We have:
 574   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 575   //      BNVC if rs >= rt
 576   //      BNEZALC if rs == 0 && rt != 0
 577   //      BNEC if rs < rt && rs != 0
 578
 579   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 580   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 581   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 582   bool HasRs = false;
 583
 584   if (Rs >= Rt) {
 585     MI.setOpcode(Mips::BNVC);
 586     HasRs = true;
 587   } else if (Rs != 0 && Rs < Rt) {
 588     MI.setOpcode(Mips::BNEC);
 589     HasRs = true;
 590   } else
 591     MI.setOpcode(Mips::BNEZALC);
 592
 593   if (HasRs)
 594     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 595                                        Rs)));
 596
 597   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 598                                      Rt)));
 599   MI.addOperand(MCOperand::CreateImm(Imm));
 600
 601   return MCDisassembler::Success;
 602 }
 603
 604 template <typename InsnType>
 605 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 606                                            uint64_t Address,
 607                                            const void *Decoder) {
 608   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 609   // (otherwise we would have matched the BLEZL instruction from the earlier
 610   // ISA's instead).
 611   //
 612   // We have:
 613   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 614   //      Invalid if rs == 0
 615   //      BLEZC   if rs == 0  && rt != 0
 616   //      BGEZC   if rs == rt && rt != 0
 617   //      BGEC    if rs != rt && rs != 0  && rt != 0
 618
 619   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 620   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 621   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 622   bool HasRs = false;
 623
 624   if (Rt == 0)
 625     return MCDisassembler::Fail;
 626   else if (Rs == 0)
 627     MI.setOpcode(Mips::BLEZC);
 628   else if (Rs == Rt)
 629     MI.setOpcode(Mips::BGEZC);
 630   else {
 631     HasRs = true;
 632     MI.setOpcode(Mips::BGEC);
 633   }
 634
 635   if (HasRs)
 636     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 637                                        Rs)));
 638
 639   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 640                                      Rt)));
 641
 642   MI.addOperand(MCOperand::CreateImm(Imm));
 643
 644   return MCDisassembler::Success;
 645 }
 646
 647 template <typename InsnType>
 648 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 649                                            uint64_t Address,
 650                                            const void *Decoder) {
 651   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 652   // (otherwise we would have matched the BGTZL instruction from the earlier
 653   // ISA's instead).
 654   //
 655   // We have:
 656   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 657   //      Invalid if rs == 0
 658   //      BGTZC   if rs == 0  && rt != 0
 659   //      BLTZC   if rs == rt && rt != 0
 660   //      BLTC    if rs != rt && rs != 0  && rt != 0
 661
 662   bool HasRs = false;
 663
 664   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 665   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 666   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 667
 668   if (Rt == 0)
 669     return MCDisassembler::Fail;
 670   else if (Rs == 0)
 671     MI.setOpcode(Mips::BGTZC);
 672   else if (Rs == Rt)
 673     MI.setOpcode(Mips::BLTZC);
 674   else {
 675     MI.setOpcode(Mips::BLTC);
 676     HasRs = true;
 677   }
 678
 679   if (HasRs)
 680     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 681                                               Rs)));
 682
 683   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 684                                      Rt)));
 685
 686   MI.addOperand(MCOperand::CreateImm(Imm));
 687
 688   return MCDisassembler::Success;
 689 }
 690
 691 template <typename InsnType>
 692 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 693                                           uint64_t Address,
 694                                           const void *Decoder) {
 695   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 696   // (otherwise we would have matched the BGTZ instruction from the earlier
 697   // ISA's instead).
 698   //
 699   // We have:
 700   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 701   //      BGTZ    if rt == 0
 702   //      BGTZALC if rs == 0 && rt != 0
 703   //      BLTZALC if rs != 0 && rs == rt
 704   //      BLTUC   if rs != 0 && rs != rt
 705
 706   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 707   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 708   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 709   bool HasRs = false;
 710   bool HasRt = false;
 711
 712   if (Rt == 0) {
 713     MI.setOpcode(Mips::BGTZ);
 714     HasRs = true;
 715   } else if (Rs == 0) {
 716     MI.setOpcode(Mips::BGTZALC);
 717     HasRt = true;
 718   } else if (Rs == Rt) {
 719     MI.setOpcode(Mips::BLTZALC);
 720     HasRs = true;
 721   } else {
 722     MI.setOpcode(Mips::BLTUC);
 723     HasRs = true;
 724     HasRt = true;
 725   }
 726
 727   if (HasRs)
 728     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 729                                        Rs)));
 730
 731   if (HasRt)
 732     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 733                                        Rt)));
 734
 735   MI.addOperand(MCOperand::CreateImm(Imm));
 736
 737   return MCDisassembler::Success;
 738 }
 739
 740 template <typename InsnType>
 741 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 742                                            uint64_t Address,
 743                                            const void *Decoder) {
 744   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 745   // (otherwise we would have matched the BLEZL instruction from the earlier
 746   // ISA's instead).
 747   //
 748   // We have:
 749   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 750   //      Invalid   if rs == 0
 751   //      BLEZALC   if rs == 0  && rt != 0
 752   //      BGEZALC   if rs == rt && rt != 0
 753   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 754
 755   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 756   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 757   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 758   bool HasRs = false;
 759
 760   if (Rt == 0)
 761     return MCDisassembler::Fail;
 762   else if (Rs == 0)
 763     MI.setOpcode(Mips::BLEZALC);
 764   else if (Rs == Rt)
 765     MI.setOpcode(Mips::BGEZALC);
 766   else {
 767     HasRs = true;
 768     MI.setOpcode(Mips::BGEUC);
 769   }
 770
 771   if (HasRs)
 772     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 773                                        Rs)));
 774   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 775                                      Rt)));
 776
 777   MI.addOperand(MCOperand::CreateImm(Imm));
 778
 779   return MCDisassembler::Success;
 780 }
 781
 782 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 783 /// according to the given endianess.
 784 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 785                                       uint64_t &Size, uint32_t &Insn,
 786                                       bool IsBigEndian) {
 787   // We want to read exactly 2 Bytes of data.
 788   if (Bytes.size() < 2) {
 789     Size = 0;
 790     return MCDisassembler::Fail;
 791   }
 792
 793   if (IsBigEndian) {
 794     Insn = (Bytes[0] << 8) | Bytes[1];
 795   } else {
 796     Insn = (Bytes[1] << 8) | Bytes[0];
 797   }
 798
 799   return MCDisassembler::Success;
 800 }
 801
 802 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 803 /// according to the given endianess
 804 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 805                                       uint64_t &Size, uint32_t &Insn,
 806                                       bool IsBigEndian, bool IsMicroMips) {
 807   // We want to read exactly 4 Bytes of data.
 808   if (Bytes.size() < 4) {
 809     Size = 0;
 810     return MCDisassembler::Fail;
 811   }
 812
 813   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 814   // always precede the low 16 bits in the instruction stream (that is, they
 815   // are placed at lower addresses in the instruction stream).
 816   //
 817   // microMIPS byte ordering:
 818   //   Big-endian:    0 | 1 | 2 | 3
 819   //   Little-endian: 1 | 0 | 3 | 2
 820
 821   if (IsBigEndian) {
 822     // Encoded as a big-endian 32-bit word in the stream.
 823     Insn =
 824         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 825   } else {
 826     if (IsMicroMips) {
 827       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 828              (Bytes[1] << 24);
 829     } else {
 830       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 831              (Bytes[3] << 24);
 832     }
 833   }
 834
 835   return MCDisassembler::Success;
 836 }
 837
 838 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 839                                               ArrayRef<uint8_t> Bytes,
 840                                               uint64_t Address,
 841                                               raw_ostream &VStream,
 842                                               raw_ostream &CStream) const {
 843   uint32_t Insn;
 844   DecodeStatus Result;
 845
 846   if (IsMicroMips) {
 847     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 848
 849     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 850     // Calling the auto-generated decoder function.
 851     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 852                                this, STI);
 853     if (Result != MCDisassembler::Fail) {
 854       Size = 2;
 855       return Result;
 856     }
 857
 858     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 859     if (Result == MCDisassembler::Fail)
 860       return MCDisassembler::Fail;
 861
 862     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 863     // Calling the auto-generated decoder function.
 864     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 865                                this, STI);
 866     if (Result != MCDisassembler::Fail) {
 867       Size = 4;
 868       return Result;
 869     }
 870     return MCDisassembler::Fail;
 871   }
 872
 873   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 874   if (Result == MCDisassembler::Fail)
 875     return MCDisassembler::Fail;
 876
 877   if (hasCOP3()) {
 878     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 879     Result =
 880         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 881     if (Result != MCDisassembler::Fail) {
 882       Size = 4;
 883       return Result;
 884     }
 885   }
 886
 887   if (hasMips32r6() && isGP64()) {
 888     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 889     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 890                                Address, this, STI);
 891     if (Result != MCDisassembler::Fail) {
 892       Size = 4;
 893       return Result;
 894     }
 895   }
 896
 897   if (hasMips32r6()) {
 898     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 899     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 900                                Address, this, STI);
 901     if (Result != MCDisassembler::Fail) {
 902       Size = 4;
 903       return Result;
 904     }
 905   }
 906
 907   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 908   // Calling the auto-generated decoder function.
 909   Result =
 910       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 911   if (Result != MCDisassembler::Fail) {
 912     Size = 4;
 913     return Result;
 914   }
 915
 916   return MCDisassembler::Fail;
 917 }
 918
 919 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 920                                                 ArrayRef<uint8_t> Bytes,
 921                                                 uint64_t Address,
 922                                                 raw_ostream &VStream,
 923                                                 raw_ostream &CStream) const {
 924   uint32_t Insn;
 925
 926   DecodeStatus Result =
 927       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 928   if (Result == MCDisassembler::Fail)
 929     return MCDisassembler::Fail;
 930
 931   // Calling the auto-generated decoder function.
 932   Result =
 933       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 934   if (Result != MCDisassembler::Fail) {
 935     Size = 4;
 936     return Result;
 937   }
 938   // If we fail to decode in Mips64 decoder space we can try in Mips32
 939   Result =
 940       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 941   if (Result != MCDisassembler::Fail) {
 942     Size = 4;
 943     return Result;
 944   }
 945
 946   return MCDisassembler::Fail;
 947 }
 948
 949 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 950                                                  unsigned RegNo,
 951                                                  uint64_t Address,
 952                                                  const void *Decoder) {
 953
 954   return MCDisassembler::Fail;
 955
 956 }
 957
 958 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 959                                              unsigned RegNo,
 960                                              uint64_t Address,
 961                                              const void *Decoder) {
 962
 963   if (RegNo > 31)
 964     return MCDisassembler::Fail;
 965
 966   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 967   Inst.addOperand(MCOperand::CreateReg(Reg));
 968   return MCDisassembler::Success;
 969 }
 970
 971 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 972                                                unsigned RegNo,
 973                                                uint64_t Address,
 974                                                const void *Decoder) {
 975   if (RegNo > 7)
 976     return MCDisassembler::Fail;
 977   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 978   Inst.addOperand(MCOperand::CreateReg(Reg));
 979   return MCDisassembler::Success;
 980 }
 981
 982 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 983                                                    unsigned RegNo,
 984                                                    uint64_t Address,
 985                                                    const void *Decoder) {
 986   if (RegNo > 7)
 987     return MCDisassembler::Fail;
 988   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 989   Inst.addOperand(MCOperand::CreateReg(Reg));
 990   return MCDisassembler::Success;
 991 }
 992
 993 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 994                                              unsigned RegNo,
 995                                              uint64_t Address,
 996                                              const void *Decoder) {
 997   if (RegNo > 31)
 998     return MCDisassembler::Fail;
 999   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1000   Inst.addOperand(MCOperand::CreateReg(Reg));
1001   return MCDisassembler::Success;
1002 }
1003
1004 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1005                                            unsigned RegNo,
1006                                            uint64_t Address,
1007                                            const void *Decoder) {
1008   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1009     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1010
1011   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1012 }
1013
1014 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1015                                             unsigned RegNo,
1016                                             uint64_t Address,
1017                                             const void *Decoder) {
1018   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1019 }
1020
1021 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1022                                              unsigned RegNo,
1023                                              uint64_t Address,
1024                                              const void *Decoder) {
1025   if (RegNo > 31)
1026     return MCDisassembler::Fail;
1027
1028   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1029   Inst.addOperand(MCOperand::CreateReg(Reg));
1030   return MCDisassembler::Success;
1031 }
1032
1033 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1034                                              unsigned RegNo,
1035                                              uint64_t Address,
1036                                              const void *Decoder) {
1037   if (RegNo > 31)
1038     return MCDisassembler::Fail;
1039
1040   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1041   Inst.addOperand(MCOperand::CreateReg(Reg));
1042   return MCDisassembler::Success;
1043 }
1044
1045 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1046                                            unsigned RegNo,
1047                                            uint64_t Address,
1048                                            const void *Decoder) {
1049   if (RegNo > 31)
1050     return MCDisassembler::Fail;
1051   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1052   Inst.addOperand(MCOperand::CreateReg(Reg));
1053   return MCDisassembler::Success;
1054 }
1055
1056 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1057                                            unsigned RegNo,
1058                                            uint64_t Address,
1059                                            const void *Decoder) {
1060   if (RegNo > 7)
1061     return MCDisassembler::Fail;
1062   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1063   Inst.addOperand(MCOperand::CreateReg(Reg));
1064   return MCDisassembler::Success;
1065 }
1066
1067 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1068                                              uint64_t Address,
1069                                              const void *Decoder) {
1070   if (RegNo > 31)
1071     return MCDisassembler::Fail;
1072
1073   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1074   Inst.addOperand(MCOperand::CreateReg(Reg));
1075   return MCDisassembler::Success;
1076 }
1077
1078 static DecodeStatus DecodeMem(MCInst &Inst,
1079                               unsigned Insn,
1080                               uint64_t Address,
1081                               const void *Decoder) {
1082   int Offset = SignExtend32<16>(Insn & 0xffff);
1083   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1084   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1085
1086   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1087   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1088
1089   if(Inst.getOpcode() == Mips::SC ||
1090      Inst.getOpcode() == Mips::SCD){
1091     Inst.addOperand(MCOperand::CreateReg(Reg));
1092   }
1093
1094   Inst.addOperand(MCOperand::CreateReg(Reg));
1095   Inst.addOperand(MCOperand::CreateReg(Base));
1096   Inst.addOperand(MCOperand::CreateImm(Offset));
1097
1098   return MCDisassembler::Success;
1099 }
1100
1101 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1102                               unsigned Insn,
1103                               uint64_t Address,
1104                               const void *Decoder) {
1105   int Offset = SignExtend32<16>(Insn & 0xffff);
1106   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1107   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1108
1109   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1110
1111   Inst.addOperand(MCOperand::CreateReg(Base));
1112   Inst.addOperand(MCOperand::CreateImm(Offset));
1113   Inst.addOperand(MCOperand::CreateImm(Hint));
1114
1115   return MCDisassembler::Success;
1116 }
1117
1118 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1119                                     unsigned Insn,
1120                                     uint64_t Address,
1121                                     const void *Decoder) {
1122   int Offset = SignExtend32<12>(Insn & 0xfff);
1123   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1124   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1125
1126   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1127
1128   Inst.addOperand(MCOperand::CreateReg(Base));
1129   Inst.addOperand(MCOperand::CreateImm(Offset));
1130   Inst.addOperand(MCOperand::CreateImm(Hint));
1131
1132   return MCDisassembler::Success;
1133 }
1134
1135 static DecodeStatus DecodeSyncI(MCInst &Inst,
1136                               unsigned Insn,
1137                               uint64_t Address,
1138                               const void *Decoder) {
1139   int Offset = SignExtend32<16>(Insn & 0xffff);
1140   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1141
1142   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1143
1144   Inst.addOperand(MCOperand::CreateReg(Base));
1145   Inst.addOperand(MCOperand::CreateImm(Offset));
1146
1147   return MCDisassembler::Success;
1148 }
1149
1150 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1151                                     uint64_t Address, const void *Decoder) {
1152   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1153   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1154   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1155
1156   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1157   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1158
1159   Inst.addOperand(MCOperand::CreateReg(Reg));
1160   Inst.addOperand(MCOperand::CreateReg(Base));
1161
1162   // The immediate field of an LD/ST instruction is scaled which means it must
1163   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1164   // data format.
1165   // .b - 1 byte
1166   // .h - 2 bytes
1167   // .w - 4 bytes
1168   // .d - 8 bytes
1169   switch(Inst.getOpcode())
1170   {
1171   default:
1172     assert (0 && "Unexpected instruction");
1173     return MCDisassembler::Fail;
1174     break;
1175   case Mips::LD_B:
1176   case Mips::ST_B:
1177     Inst.addOperand(MCOperand::CreateImm(Offset));
1178     break;
1179   case Mips::LD_H:
1180   case Mips::ST_H:
1181     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1182     break;
1183   case Mips::LD_W:
1184   case Mips::ST_W:
1185     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1186     break;
1187   case Mips::LD_D:
1188   case Mips::ST_D:
1189     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1190     break;
1191   }
1192
1193   return MCDisassembler::Success;
1194 }
1195
1196 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1197                                     unsigned Insn,
1198                                     uint64_t Address,
1199                                     const void *Decoder) {
1200   unsigned Offset = Insn & 0xf;
1201   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1202   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1203
1204   switch (Inst.getOpcode()) {
1205     case Mips::LBU16_MM:
1206     case Mips::LHU16_MM:
1207     case Mips::LW16_MM:
1208       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1209             == MCDisassembler::Fail)
1210         return MCDisassembler::Fail;
1211       break;
1212     case Mips::SB16_MM:
1213     case Mips::SH16_MM:
1214     case Mips::SW16_MM:
1215       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1216             == MCDisassembler::Fail)
1217         return MCDisassembler::Fail;
1218       break;
1219   }
1220
1221   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1222         == MCDisassembler::Fail)
1223     return MCDisassembler::Fail;
1224
1225   switch (Inst.getOpcode()) {
1226     case Mips::LBU16_MM:
1227       if (Offset == 0xf)
1228         Inst.addOperand(MCOperand::CreateImm(-1));
1229       else
1230         Inst.addOperand(MCOperand::CreateImm(Offset));
1231       break;
1232     case Mips::SB16_MM:
1233       Inst.addOperand(MCOperand::CreateImm(Offset));
1234       break;
1235     case Mips::LHU16_MM:
1236     case Mips::SH16_MM:
1237       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1238       break;
1239     case Mips::LW16_MM:
1240     case Mips::SW16_MM:
1241       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1242       break;
1243   }
1244
1245   return MCDisassembler::Success;
1246 }
1247
1248 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1249                                           unsigned Insn,
1250                                           uint64_t Address,
1251                                           const void *Decoder) {
1252   unsigned Offset = Insn & 0x1F;
1253   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1254
1255   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1256
1257   Inst.addOperand(MCOperand::CreateReg(Reg));
1258   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1259   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1260
1261   return MCDisassembler::Success;
1262 }
1263
1264 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1265                                      unsigned Insn,
1266                                      uint64_t Address,
1267                                      const void *Decoder) {
1268   int Offset = SignExtend32<12>(Insn & 0x0fff);
1269   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1270   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1271
1272   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1273   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1274
1275   switch (Inst.getOpcode()) {
1276   case Mips::SWM32_MM:
1277   case Mips::LWM32_MM:
1278     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1279         == MCDisassembler::Fail)
1280       return MCDisassembler::Fail;
1281     Inst.addOperand(MCOperand::CreateReg(Base));
1282     Inst.addOperand(MCOperand::CreateImm(Offset));
1283     break;
1284   case Mips::SC_MM:
1285     Inst.addOperand(MCOperand::CreateReg(Reg));
1286     // fallthrough
1287   default:
1288     Inst.addOperand(MCOperand::CreateReg(Reg));
1289     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1290       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1291
1292     Inst.addOperand(MCOperand::CreateReg(Base));
1293     Inst.addOperand(MCOperand::CreateImm(Offset));
1294   }
1295
1296   return MCDisassembler::Success;
1297 }
1298
1299 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1300                                      unsigned Insn,
1301                                      uint64_t Address,
1302                                      const void *Decoder) {
1303   int Offset = SignExtend32<16>(Insn & 0xffff);
1304   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1305   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1306
1307   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1308   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1309
1310   Inst.addOperand(MCOperand::CreateReg(Reg));
1311   Inst.addOperand(MCOperand::CreateReg(Base));
1312   Inst.addOperand(MCOperand::CreateImm(Offset));
1313
1314   return MCDisassembler::Success;
1315 }
1316
1317 static DecodeStatus DecodeFMem(MCInst &Inst,
1318                                unsigned Insn,
1319                                uint64_t Address,
1320                                const void *Decoder) {
1321   int Offset = SignExtend32<16>(Insn & 0xffff);
1322   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1323   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1324
1325   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1326   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1327
1328   Inst.addOperand(MCOperand::CreateReg(Reg));
1329   Inst.addOperand(MCOperand::CreateReg(Base));
1330   Inst.addOperand(MCOperand::CreateImm(Offset));
1331
1332   return MCDisassembler::Success;
1333 }
1334
1335 static DecodeStatus DecodeFMem2(MCInst &Inst,
1336                                unsigned Insn,
1337                                uint64_t Address,
1338                                const void *Decoder) {
1339   int Offset = SignExtend32<16>(Insn & 0xffff);
1340   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1341   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1342
1343   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1344   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1345
1346   Inst.addOperand(MCOperand::CreateReg(Reg));
1347   Inst.addOperand(MCOperand::CreateReg(Base));
1348   Inst.addOperand(MCOperand::CreateImm(Offset));
1349
1350   return MCDisassembler::Success;
1351 }
1352
1353 static DecodeStatus DecodeFMem3(MCInst &Inst,
1354                                unsigned Insn,
1355                                uint64_t Address,
1356                                const void *Decoder) {
1357   int Offset = SignExtend32<16>(Insn & 0xffff);
1358   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1359   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1360
1361   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1362   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1363
1364   Inst.addOperand(MCOperand::CreateReg(Reg));
1365   Inst.addOperand(MCOperand::CreateReg(Base));
1366   Inst.addOperand(MCOperand::CreateImm(Offset));
1367
1368   return MCDisassembler::Success;
1369 }
1370
1371 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1372                                     unsigned Insn,
1373                                     uint64_t Address,
1374                                     const void *Decoder) {
1375   int Offset = SignExtend32<11>(Insn & 0x07ff);
1376   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1377   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1378
1379   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1380   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1381
1382   Inst.addOperand(MCOperand::CreateReg(Reg));
1383   Inst.addOperand(MCOperand::CreateReg(Base));
1384   Inst.addOperand(MCOperand::CreateImm(Offset));
1385
1386   return MCDisassembler::Success;
1387 }
1388 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1389                                        unsigned Insn,
1390                                        uint64_t Address,
1391                                        const void *Decoder) {
1392   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1393   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1394   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1395
1396   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1397   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1398
1399   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1400     Inst.addOperand(MCOperand::CreateReg(Rt));
1401   }
1402
1403   Inst.addOperand(MCOperand::CreateReg(Rt));
1404   Inst.addOperand(MCOperand::CreateReg(Base));
1405   Inst.addOperand(MCOperand::CreateImm(Offset));
1406
1407   return MCDisassembler::Success;
1408 }
1409
1410 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1411                                               unsigned RegNo,
1412                                               uint64_t Address,
1413                                               const void *Decoder) {
1414   // Currently only hardware register 29 is supported.
1415   if (RegNo != 29)
1416     return  MCDisassembler::Fail;
1417   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1418   return MCDisassembler::Success;
1419 }
1420
1421 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1422                                               unsigned RegNo,
1423                                               uint64_t Address,
1424                                               const void *Decoder) {
1425   if (RegNo > 30 || RegNo %2)
1426     return MCDisassembler::Fail;
1427
1428   ;
1429   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1430   Inst.addOperand(MCOperand::CreateReg(Reg));
1431   return MCDisassembler::Success;
1432 }
1433
1434 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1435                                                 unsigned RegNo,
1436                                                 uint64_t Address,
1437                                                 const void *Decoder) {
1438   if (RegNo >= 4)
1439     return MCDisassembler::Fail;
1440
1441   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1442   Inst.addOperand(MCOperand::CreateReg(Reg));
1443   return MCDisassembler::Success;
1444 }
1445
1446 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1447                                                unsigned RegNo,
1448                                                uint64_t Address,
1449                                                const void *Decoder) {
1450   if (RegNo >= 4)
1451     return MCDisassembler::Fail;
1452
1453   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1454   Inst.addOperand(MCOperand::CreateReg(Reg));
1455   return MCDisassembler::Success;
1456 }
1457
1458 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1459                                                unsigned RegNo,
1460                                                uint64_t Address,
1461                                                const void *Decoder) {
1462   if (RegNo >= 4)
1463     return MCDisassembler::Fail;
1464
1465   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1466   Inst.addOperand(MCOperand::CreateReg(Reg));
1467   return MCDisassembler::Success;
1468 }
1469
1470 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1471                                                unsigned RegNo,
1472                                                uint64_t Address,
1473                                                const void *Decoder) {
1474   if (RegNo > 31)
1475     return MCDisassembler::Fail;
1476
1477   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1478   Inst.addOperand(MCOperand::CreateReg(Reg));
1479   return MCDisassembler::Success;
1480 }
1481
1482 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1483                                                unsigned RegNo,
1484                                                uint64_t Address,
1485                                                const void *Decoder) {
1486   if (RegNo > 31)
1487     return MCDisassembler::Fail;
1488
1489   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1490   Inst.addOperand(MCOperand::CreateReg(Reg));
1491   return MCDisassembler::Success;
1492 }
1493
1494 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1495                                                unsigned RegNo,
1496                                                uint64_t Address,
1497                                                const void *Decoder) {
1498   if (RegNo > 31)
1499     return MCDisassembler::Fail;
1500
1501   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1502   Inst.addOperand(MCOperand::CreateReg(Reg));
1503   return MCDisassembler::Success;
1504 }
1505
1506 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1507                                                unsigned RegNo,
1508                                                uint64_t Address,
1509                                                const void *Decoder) {
1510   if (RegNo > 31)
1511     return MCDisassembler::Fail;
1512
1513   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1514   Inst.addOperand(MCOperand::CreateReg(Reg));
1515   return MCDisassembler::Success;
1516 }
1517
1518 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1519                                                unsigned RegNo,
1520                                                uint64_t Address,
1521                                                const void *Decoder) {
1522   if (RegNo > 7)
1523     return MCDisassembler::Fail;
1524
1525   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1526   Inst.addOperand(MCOperand::CreateReg(Reg));
1527   return MCDisassembler::Success;
1528 }
1529
1530 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1531                                             unsigned RegNo,
1532                                             uint64_t Address,
1533                                             const void *Decoder) {
1534   if (RegNo > 31)
1535     return MCDisassembler::Fail;
1536
1537   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1538   Inst.addOperand(MCOperand::CreateReg(Reg));
1539   return MCDisassembler::Success;
1540 }
1541
1542 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1543                                        unsigned Offset,
1544                                        uint64_t Address,
1545                                        const void *Decoder) {
1546   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1547   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1548   return MCDisassembler::Success;
1549 }
1550
1551 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1552                                      unsigned Insn,
1553                                      uint64_t Address,
1554                                      const void *Decoder) {
1555
1556   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1557   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1558   return MCDisassembler::Success;
1559 }
1560
1561 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1562                                          unsigned Offset,
1563                                          uint64_t Address,
1564                                          const void *Decoder) {
1565   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1566
1567   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1568   return MCDisassembler::Success;
1569 }
1570
1571 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1572                                          unsigned Offset,
1573                                          uint64_t Address,
1574                                          const void *Decoder) {
1575   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1576
1577   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1578   return MCDisassembler::Success;
1579 }
1580
1581 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1582                                           unsigned Offset,
1583                                           uint64_t Address,
1584                                           const void *Decoder) {
1585   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1586   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1587   return MCDisassembler::Success;
1588 }
1589
1590 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1591                                            unsigned Offset,
1592                                            uint64_t Address,
1593                                            const void *Decoder) {
1594   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1595   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1596   return MCDisassembler::Success;
1597 }
1598
1599 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1600                                          unsigned Offset,
1601                                          uint64_t Address,
1602                                          const void *Decoder) {
1603   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1604   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1605   return MCDisassembler::Success;
1606 }
1607
1608 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1609                                        unsigned Insn,
1610                                        uint64_t Address,
1611                                        const void *Decoder) {
1612   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1613   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1614   return MCDisassembler::Success;
1615 }
1616
1617 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1618                                        unsigned Value,
1619                                        uint64_t Address,
1620                                        const void *Decoder) {
1621   if (Value == 0)
1622     Inst.addOperand(MCOperand::CreateImm(1));
1623   else if (Value == 0x7)
1624     Inst.addOperand(MCOperand::CreateImm(-1));
1625   else
1626     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1627   return MCDisassembler::Success;
1628 }
1629
1630 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1631                                     unsigned Value,
1632                                     uint64_t Address,
1633                                     const void *Decoder) {
1634   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1635   return MCDisassembler::Success;
1636 }
1637
1638 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1639                                   unsigned Value,
1640                                   uint64_t Address,
1641                                   const void *Decoder) {
1642   if (Value == 0x7F)
1643     Inst.addOperand(MCOperand::CreateImm(-1));
1644   else
1645     Inst.addOperand(MCOperand::CreateImm(Value));
1646   return MCDisassembler::Success;
1647 }
1648
1649 static DecodeStatus DecodeSimm4(MCInst &Inst,
1650                                 unsigned Value,
1651                                 uint64_t Address,
1652                                 const void *Decoder) {
1653   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1654   return MCDisassembler::Success;
1655 }
1656
1657 static DecodeStatus DecodeSimm16(MCInst &Inst,
1658                                  unsigned Insn,
1659                                  uint64_t Address,
1660                                  const void *Decoder) {
1661   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1662   return MCDisassembler::Success;
1663 }
1664
1665 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1666                                  unsigned Insn,
1667                                  uint64_t Address,
1668                                  const void *Decoder) {
1669   // We add one to the immediate field as it was encoded as 'imm - 1'.
1670   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1671   return MCDisassembler::Success;
1672 }
1673
1674 static DecodeStatus DecodeInsSize(MCInst &Inst,
1675                                   unsigned Insn,
1676                                   uint64_t Address,
1677                                   const void *Decoder) {
1678   // First we need to grab the pos(lsb) from MCInst.
1679   int Pos = Inst.getOperand(2).getImm();
1680   int Size = (int) Insn - Pos + 1;
1681   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1682   return MCDisassembler::Success;
1683 }
1684
1685 static DecodeStatus DecodeExtSize(MCInst &Inst,
1686                                   unsigned Insn,
1687                                   uint64_t Address,
1688                                   const void *Decoder) {
1689   int Size = (int) Insn  + 1;
1690   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1691   return MCDisassembler::Success;
1692 }
1693
1694 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1695                                      uint64_t Address, const void *Decoder) {
1696   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1697   return MCDisassembler::Success;
1698 }
1699
1700 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1701                                      uint64_t Address, const void *Decoder) {
1702   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1703   return MCDisassembler::Success;
1704 }
1705
1706 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1707                                   uint64_t Address, const void *Decoder) {
1708   int32_t DecodedValue;
1709   switch (Insn) {
1710   case 0: DecodedValue = 256; break;
1711   case 1: DecodedValue = 257; break;
1712   case 510: DecodedValue = -258; break;
1713   case 511: DecodedValue = -257; break;
1714   default: DecodedValue = SignExtend32<9>(Insn); break;
1715   }
1716   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1717   return MCDisassembler::Success;
1718 }
1719
1720 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1721                                     uint64_t Address, const void *Decoder) {
1722   // Insn must be >= 0, since it is unsigned that condition is always true.
1723   assert(Insn < 16);
1724   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1725                              255, 32768, 65535};
1726   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1727   return MCDisassembler::Success;
1728 }
1729
1730 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1731                                     uint64_t Address, const void *Decoder) {
1732   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1733   return MCDisassembler::Success;
1734 }
1735
1736 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1737                                          unsigned Insn,
1738                                          uint64_t Address,
1739                                          const void *Decoder) {
1740   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1741                      Mips::S6, Mips::FP};
1742   unsigned RegNum;
1743
1744   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1745   // Empty register lists are not allowed.
1746   if (RegLst == 0)
1747     return MCDisassembler::Fail;
1748
1749   RegNum = RegLst & 0xf;
1750   for (unsigned i = 0; i < RegNum; i++)
1751     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1752
1753   if (RegLst & 0x10)
1754     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1755
1756   return MCDisassembler::Success;
1757 }
1758
1759 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1760                                            uint64_t Address,
1761                                            const void *Decoder) {
1762   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1763   unsigned RegNum;
1764
1765   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1766   // Empty register lists are not allowed.
1767   if (RegLst == 0)
1768     return MCDisassembler::Fail;
1769
1770   RegNum = RegLst & 0x3;
1771   for (unsigned i = 0; i < RegNum - 1; i++)
1772     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1773
1774   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1775
1776   return MCDisassembler::Success;
1777 }
1778
1779 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1780                                      uint64_t Address, const void *Decoder) {
1781   Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1782   return MCDisassembler::Success;
1783 }