lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disassembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disassembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disassembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 234                                           unsigned Offset,
 235                                           uint64_t Address,
 236                                           const void *Decoder);
 237
 238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 241                                            unsigned Offset,
 242                                            uint64_t Address,
 243                                            const void *Decoder);
 244
 245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 246 // shifted left by 1 bit.
 247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 248                                          unsigned Offset,
 249                                          uint64_t Address,
 250                                          const void *Decoder);
 251
 252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 253 // shifted left by 1 bit.
 254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 255                                        unsigned Insn,
 256                                        uint64_t Address,
 257                                        const void *Decoder);
 258
 259 static DecodeStatus DecodeMem(MCInst &Inst,
 260                               unsigned Insn,
 261                               uint64_t Address,
 262                               const void *Decoder);
 263
 264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 265                               unsigned Insn,
 266                               uint64_t Address,
 267                               const void *Decoder);
 268
 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeSyncI(MCInst &Inst,
 275                                 unsigned Insn,
 276                                 uint64_t Address,
 277                                 const void *Decoder);
 278
 279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 280                                     uint64_t Address, const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 283                                     unsigned Insn,
 284                                     uint64_t Address,
 285                                     const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 288                                           unsigned Insn,
 289                                           uint64_t Address,
 290                                           const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 293                                           unsigned Insn,
 294                                           uint64_t Address,
 295                                           const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 298                                      unsigned Insn,
 299                                      uint64_t Address,
 300                                      const void *Decoder);
 301
 302 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 303                                      unsigned Insn,
 304                                      uint64_t Address,
 305                                      const void *Decoder);
 306
 307 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 308                                uint64_t Address,
 309                                const void *Decoder);
 310
 311 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 312                                uint64_t Address,
 313                                const void *Decoder);
 314
 315 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 316                                uint64_t Address,
 317                                const void *Decoder);
 318
 319 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 320                                uint64_t Address,
 321                                const void *Decoder);
 322
 323 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 324                                        unsigned Insn,
 325                                        uint64_t Address,
 326                                        const void *Decoder);
 327
 328 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 329                                        unsigned Value,
 330                                        uint64_t Address,
 331                                        const void *Decoder);
 332
 333 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 334                                     unsigned Value,
 335                                     uint64_t Address,
 336                                     const void *Decoder);
 337
 338 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 339                                   unsigned Value,
 340                                   uint64_t Address,
 341                                   const void *Decoder);
 342
 343 static DecodeStatus DecodeSimm4(MCInst &Inst,
 344                                 unsigned Value,
 345                                 uint64_t Address,
 346                                 const void *Decoder);
 347
 348 static DecodeStatus DecodeSimm16(MCInst &Inst,
 349                                  unsigned Insn,
 350                                  uint64_t Address,
 351                                  const void *Decoder);
 352
 353 // Decode the immediate field of an LSA instruction which
 354 // is off by one.
 355 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 356                                  unsigned Insn,
 357                                  uint64_t Address,
 358                                  const void *Decoder);
 359
 360 static DecodeStatus DecodeInsSize(MCInst &Inst,
 361                                   unsigned Insn,
 362                                   uint64_t Address,
 363                                   const void *Decoder);
 364
 365 static DecodeStatus DecodeExtSize(MCInst &Inst,
 366                                   unsigned Insn,
 367                                   uint64_t Address,
 368                                   const void *Decoder);
 369
 370 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 371                                      uint64_t Address, const void *Decoder);
 372
 373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 374                                      uint64_t Address, const void *Decoder);
 375
 376 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 377                                   uint64_t Address, const void *Decoder);
 378
 379 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 380                                     uint64_t Address, const void *Decoder);
 381
 382 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 383                                    uint64_t Address, const void *Decoder);
 384
 385 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 386                                      uint64_t Address, const void *Decoder);
 387
 388 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 389 /// handle.
 390 template <typename InsnType>
 391 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 392                                    const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                       const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                        const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                        const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                       const void *Decoder);
 418
 419 template <typename InsnType>
 420 static DecodeStatus
 421 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 422                        const void *Decoder);
 423
 424 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 425                                          uint64_t Address,
 426                                          const void *Decoder);
 427
 428 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 429                                            uint64_t Address,
 430                                            const void *Decoder);
 431
 432 namespace llvm {
 433 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 434               TheMips64elTarget;
 435 }
 436
 437 static MCDisassembler *createMipsDisassembler(
 438                        const Target &T,
 439                        const MCSubtargetInfo &STI,
 440                        MCContext &Ctx) {
 441   return new MipsDisassembler(STI, Ctx, true);
 442 }
 443
 444 static MCDisassembler *createMipselDisassembler(
 445                        const Target &T,
 446                        const MCSubtargetInfo &STI,
 447                        MCContext &Ctx) {
 448   return new MipsDisassembler(STI, Ctx, false);
 449 }
 450
 451 static MCDisassembler *createMips64Disassembler(
 452                        const Target &T,
 453                        const MCSubtargetInfo &STI,
 454                        MCContext &Ctx) {
 455   return new Mips64Disassembler(STI, Ctx, true);
 456 }
 457
 458 static MCDisassembler *createMips64elDisassembler(
 459                        const Target &T,
 460                        const MCSubtargetInfo &STI,
 461                        MCContext &Ctx) {
 462   return new Mips64Disassembler(STI, Ctx, false);
 463 }
 464
 465 extern "C" void LLVMInitializeMipsDisassembler() {
 466   // Register the disassembler.
 467   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 468                                          createMipsDisassembler);
 469   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 470                                          createMipselDisassembler);
 471   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 472                                          createMips64Disassembler);
 473   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 474                                          createMips64elDisassembler);
 475 }
 476
 477 #include "MipsGenDisassemblerTables.inc"
 478
 479 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 480   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 481   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 482   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 483 }
 484
 485 template <typename InsnType>
 486 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 487                                    const void *Decoder) {
 488   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 489   // The size of the n field depends on the element size
 490   // The register class also depends on this.
 491   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 492   unsigned NSize = 0;
 493   DecodeFN RegDecoder = nullptr;
 494   if ((tmp & 0x18) == 0x00) { // INSVE_B
 495     NSize = 4;
 496     RegDecoder = DecodeMSA128BRegisterClass;
 497   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 498     NSize = 3;
 499     RegDecoder = DecodeMSA128HRegisterClass;
 500   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 501     NSize = 2;
 502     RegDecoder = DecodeMSA128WRegisterClass;
 503   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 504     NSize = 1;
 505     RegDecoder = DecodeMSA128DRegisterClass;
 506   } else
 507     llvm_unreachable("Invalid encoding");
 508
 509   assert(NSize != 0 && RegDecoder != nullptr);
 510
 511   // $wd
 512   tmp = fieldFromInstruction(insn, 6, 5);
 513   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 514     return MCDisassembler::Fail;
 515   // $wd_in
 516   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 517     return MCDisassembler::Fail;
 518   // $n
 519   tmp = fieldFromInstruction(insn, 16, NSize);
 520   MI.addOperand(MCOperand::CreateImm(tmp));
 521   // $ws
 522   tmp = fieldFromInstruction(insn, 11, 5);
 523   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 524     return MCDisassembler::Fail;
 525   // $n2
 526   MI.addOperand(MCOperand::CreateImm(0));
 527
 528   return MCDisassembler::Success;
 529 }
 530
 531 template <typename InsnType>
 532 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 533                                           uint64_t Address,
 534                                           const void *Decoder) {
 535   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 536   // (otherwise we would have matched the ADDI instruction from the earlier
 537   // ISA's instead).
 538   //
 539   // We have:
 540   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 541   //      BOVC if rs >= rt
 542   //      BEQZALC if rs == 0 && rt != 0
 543   //      BEQC if rs < rt && rs != 0
 544
 545   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 546   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 547   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 548   bool HasRs = false;
 549
 550   if (Rs >= Rt) {
 551     MI.setOpcode(Mips::BOVC);
 552     HasRs = true;
 553   } else if (Rs != 0 && Rs < Rt) {
 554     MI.setOpcode(Mips::BEQC);
 555     HasRs = true;
 556   } else
 557     MI.setOpcode(Mips::BEQZALC);
 558
 559   if (HasRs)
 560     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 561                                        Rs)));
 562
 563   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 564                                      Rt)));
 565   MI.addOperand(MCOperand::CreateImm(Imm));
 566
 567   return MCDisassembler::Success;
 568 }
 569
 570 template <typename InsnType>
 571 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 572                                            uint64_t Address,
 573                                            const void *Decoder) {
 574   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 575   // (otherwise we would have matched the ADDI instruction from the earlier
 576   // ISA's instead).
 577   //
 578   // We have:
 579   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 580   //      BNVC if rs >= rt
 581   //      BNEZALC if rs == 0 && rt != 0
 582   //      BNEC if rs < rt && rs != 0
 583
 584   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 585   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 586   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 587   bool HasRs = false;
 588
 589   if (Rs >= Rt) {
 590     MI.setOpcode(Mips::BNVC);
 591     HasRs = true;
 592   } else if (Rs != 0 && Rs < Rt) {
 593     MI.setOpcode(Mips::BNEC);
 594     HasRs = true;
 595   } else
 596     MI.setOpcode(Mips::BNEZALC);
 597
 598   if (HasRs)
 599     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 600                                        Rs)));
 601
 602   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 603                                      Rt)));
 604   MI.addOperand(MCOperand::CreateImm(Imm));
 605
 606   return MCDisassembler::Success;
 607 }
 608
 609 template <typename InsnType>
 610 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 611                                            uint64_t Address,
 612                                            const void *Decoder) {
 613   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 614   // (otherwise we would have matched the BLEZL instruction from the earlier
 615   // ISA's instead).
 616   //
 617   // We have:
 618   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 619   //      Invalid if rs == 0
 620   //      BLEZC   if rs == 0  && rt != 0
 621   //      BGEZC   if rs == rt && rt != 0
 622   //      BGEC    if rs != rt && rs != 0  && rt != 0
 623
 624   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 625   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 626   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 627   bool HasRs = false;
 628
 629   if (Rt == 0)
 630     return MCDisassembler::Fail;
 631   else if (Rs == 0)
 632     MI.setOpcode(Mips::BLEZC);
 633   else if (Rs == Rt)
 634     MI.setOpcode(Mips::BGEZC);
 635   else {
 636     HasRs = true;
 637     MI.setOpcode(Mips::BGEC);
 638   }
 639
 640   if (HasRs)
 641     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 642                                        Rs)));
 643
 644   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 645                                      Rt)));
 646
 647   MI.addOperand(MCOperand::CreateImm(Imm));
 648
 649   return MCDisassembler::Success;
 650 }
 651
 652 template <typename InsnType>
 653 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 654                                            uint64_t Address,
 655                                            const void *Decoder) {
 656   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 657   // (otherwise we would have matched the BGTZL instruction from the earlier
 658   // ISA's instead).
 659   //
 660   // We have:
 661   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 662   //      Invalid if rs == 0
 663   //      BGTZC   if rs == 0  && rt != 0
 664   //      BLTZC   if rs == rt && rt != 0
 665   //      BLTC    if rs != rt && rs != 0  && rt != 0
 666
 667   bool HasRs = false;
 668
 669   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 670   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 671   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 672
 673   if (Rt == 0)
 674     return MCDisassembler::Fail;
 675   else if (Rs == 0)
 676     MI.setOpcode(Mips::BGTZC);
 677   else if (Rs == Rt)
 678     MI.setOpcode(Mips::BLTZC);
 679   else {
 680     MI.setOpcode(Mips::BLTC);
 681     HasRs = true;
 682   }
 683
 684   if (HasRs)
 685     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 686                                               Rs)));
 687
 688   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 689                                      Rt)));
 690
 691   MI.addOperand(MCOperand::CreateImm(Imm));
 692
 693   return MCDisassembler::Success;
 694 }
 695
 696 template <typename InsnType>
 697 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 698                                           uint64_t Address,
 699                                           const void *Decoder) {
 700   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 701   // (otherwise we would have matched the BGTZ instruction from the earlier
 702   // ISA's instead).
 703   //
 704   // We have:
 705   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 706   //      BGTZ    if rt == 0
 707   //      BGTZALC if rs == 0 && rt != 0
 708   //      BLTZALC if rs != 0 && rs == rt
 709   //      BLTUC   if rs != 0 && rs != rt
 710
 711   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 712   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 713   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 714   bool HasRs = false;
 715   bool HasRt = false;
 716
 717   if (Rt == 0) {
 718     MI.setOpcode(Mips::BGTZ);
 719     HasRs = true;
 720   } else if (Rs == 0) {
 721     MI.setOpcode(Mips::BGTZALC);
 722     HasRt = true;
 723   } else if (Rs == Rt) {
 724     MI.setOpcode(Mips::BLTZALC);
 725     HasRs = true;
 726   } else {
 727     MI.setOpcode(Mips::BLTUC);
 728     HasRs = true;
 729     HasRt = true;
 730   }
 731
 732   if (HasRs)
 733     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 734                                        Rs)));
 735
 736   if (HasRt)
 737     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 738                                        Rt)));
 739
 740   MI.addOperand(MCOperand::CreateImm(Imm));
 741
 742   return MCDisassembler::Success;
 743 }
 744
 745 template <typename InsnType>
 746 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 747                                            uint64_t Address,
 748                                            const void *Decoder) {
 749   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 750   // (otherwise we would have matched the BLEZL instruction from the earlier
 751   // ISA's instead).
 752   //
 753   // We have:
 754   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 755   //      Invalid   if rs == 0
 756   //      BLEZALC   if rs == 0  && rt != 0
 757   //      BGEZALC   if rs == rt && rt != 0
 758   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 759
 760   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 761   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 762   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 763   bool HasRs = false;
 764
 765   if (Rt == 0)
 766     return MCDisassembler::Fail;
 767   else if (Rs == 0)
 768     MI.setOpcode(Mips::BLEZALC);
 769   else if (Rs == Rt)
 770     MI.setOpcode(Mips::BGEZALC);
 771   else {
 772     HasRs = true;
 773     MI.setOpcode(Mips::BGEUC);
 774   }
 775
 776   if (HasRs)
 777     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 778                                        Rs)));
 779   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 780                                      Rt)));
 781
 782   MI.addOperand(MCOperand::CreateImm(Imm));
 783
 784   return MCDisassembler::Success;
 785 }
 786
 787 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 788 /// according to the given endianess.
 789 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 790                                       uint64_t &Size, uint32_t &Insn,
 791                                       bool IsBigEndian) {
 792   // We want to read exactly 2 Bytes of data.
 793   if (Bytes.size() < 2) {
 794     Size = 0;
 795     return MCDisassembler::Fail;
 796   }
 797
 798   if (IsBigEndian) {
 799     Insn = (Bytes[0] << 8) | Bytes[1];
 800   } else {
 801     Insn = (Bytes[1] << 8) | Bytes[0];
 802   }
 803
 804   return MCDisassembler::Success;
 805 }
 806
 807 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 808 /// according to the given endianess
 809 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 810                                       uint64_t &Size, uint32_t &Insn,
 811                                       bool IsBigEndian, bool IsMicroMips) {
 812   // We want to read exactly 4 Bytes of data.
 813   if (Bytes.size() < 4) {
 814     Size = 0;
 815     return MCDisassembler::Fail;
 816   }
 817
 818   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 819   // always precede the low 16 bits in the instruction stream (that is, they
 820   // are placed at lower addresses in the instruction stream).
 821   //
 822   // microMIPS byte ordering:
 823   //   Big-endian:    0 | 1 | 2 | 3
 824   //   Little-endian: 1 | 0 | 3 | 2
 825
 826   if (IsBigEndian) {
 827     // Encoded as a big-endian 32-bit word in the stream.
 828     Insn =
 829         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 830   } else {
 831     if (IsMicroMips) {
 832       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 833              (Bytes[1] << 24);
 834     } else {
 835       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 836              (Bytes[3] << 24);
 837     }
 838   }
 839
 840   return MCDisassembler::Success;
 841 }
 842
 843 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 844                                               ArrayRef<uint8_t> Bytes,
 845                                               uint64_t Address,
 846                                               raw_ostream &VStream,
 847                                               raw_ostream &CStream) const {
 848   uint32_t Insn;
 849   DecodeStatus Result;
 850
 851   if (IsMicroMips) {
 852     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 853
 854     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 855     // Calling the auto-generated decoder function.
 856     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 857                                this, STI);
 858     if (Result != MCDisassembler::Fail) {
 859       Size = 2;
 860       return Result;
 861     }
 862
 863     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 864     if (Result == MCDisassembler::Fail)
 865       return MCDisassembler::Fail;
 866
 867     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 868     // Calling the auto-generated decoder function.
 869     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 870                                this, STI);
 871     if (Result != MCDisassembler::Fail) {
 872       Size = 4;
 873       return Result;
 874     }
 875     return MCDisassembler::Fail;
 876   }
 877
 878   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 879   if (Result == MCDisassembler::Fail)
 880     return MCDisassembler::Fail;
 881
 882   if (hasCOP3()) {
 883     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 884     Result =
 885         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 886     if (Result != MCDisassembler::Fail) {
 887       Size = 4;
 888       return Result;
 889     }
 890   }
 891
 892   if (hasMips32r6() && isGP64()) {
 893     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 894     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 895                                Address, this, STI);
 896     if (Result != MCDisassembler::Fail) {
 897       Size = 4;
 898       return Result;
 899     }
 900   }
 901
 902   if (hasMips32r6()) {
 903     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 904     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 905                                Address, this, STI);
 906     if (Result != MCDisassembler::Fail) {
 907       Size = 4;
 908       return Result;
 909     }
 910   }
 911
 912   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 913   // Calling the auto-generated decoder function.
 914   Result =
 915       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 916   if (Result != MCDisassembler::Fail) {
 917     Size = 4;
 918     return Result;
 919   }
 920
 921   return MCDisassembler::Fail;
 922 }
 923
 924 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 925                                                 ArrayRef<uint8_t> Bytes,
 926                                                 uint64_t Address,
 927                                                 raw_ostream &VStream,
 928                                                 raw_ostream &CStream) const {
 929   uint32_t Insn;
 930
 931   DecodeStatus Result =
 932       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 933   if (Result == MCDisassembler::Fail)
 934     return MCDisassembler::Fail;
 935
 936   // Calling the auto-generated decoder function.
 937   Result =
 938       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 939   if (Result != MCDisassembler::Fail) {
 940     Size = 4;
 941     return Result;
 942   }
 943   // If we fail to decode in Mips64 decoder space we can try in Mips32
 944   Result =
 945       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 946   if (Result != MCDisassembler::Fail) {
 947     Size = 4;
 948     return Result;
 949   }
 950
 951   return MCDisassembler::Fail;
 952 }
 953
 954 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 955                                                  unsigned RegNo,
 956                                                  uint64_t Address,
 957                                                  const void *Decoder) {
 958
 959   return MCDisassembler::Fail;
 960
 961 }
 962
 963 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 964                                              unsigned RegNo,
 965                                              uint64_t Address,
 966                                              const void *Decoder) {
 967
 968   if (RegNo > 31)
 969     return MCDisassembler::Fail;
 970
 971   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 972   Inst.addOperand(MCOperand::CreateReg(Reg));
 973   return MCDisassembler::Success;
 974 }
 975
 976 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 977                                                unsigned RegNo,
 978                                                uint64_t Address,
 979                                                const void *Decoder) {
 980   if (RegNo > 7)
 981     return MCDisassembler::Fail;
 982   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 983   Inst.addOperand(MCOperand::CreateReg(Reg));
 984   return MCDisassembler::Success;
 985 }
 986
 987 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 988                                                    unsigned RegNo,
 989                                                    uint64_t Address,
 990                                                    const void *Decoder) {
 991   if (RegNo > 7)
 992     return MCDisassembler::Fail;
 993   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 994   Inst.addOperand(MCOperand::CreateReg(Reg));
 995   return MCDisassembler::Success;
 996 }
 997
 998 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 999                                              unsigned RegNo,
1000                                              uint64_t Address,
1001                                              const void *Decoder) {
1002   if (RegNo > 31)
1003     return MCDisassembler::Fail;
1004   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1005   Inst.addOperand(MCOperand::CreateReg(Reg));
1006   return MCDisassembler::Success;
1007 }
1008
1009 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1010                                            unsigned RegNo,
1011                                            uint64_t Address,
1012                                            const void *Decoder) {
1013   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1014     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1015
1016   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1017 }
1018
1019 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1020                                             unsigned RegNo,
1021                                             uint64_t Address,
1022                                             const void *Decoder) {
1023   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1024 }
1025
1026 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1027                                              unsigned RegNo,
1028                                              uint64_t Address,
1029                                              const void *Decoder) {
1030   if (RegNo > 31)
1031     return MCDisassembler::Fail;
1032
1033   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1034   Inst.addOperand(MCOperand::CreateReg(Reg));
1035   return MCDisassembler::Success;
1036 }
1037
1038 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1039                                              unsigned RegNo,
1040                                              uint64_t Address,
1041                                              const void *Decoder) {
1042   if (RegNo > 31)
1043     return MCDisassembler::Fail;
1044
1045   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1046   Inst.addOperand(MCOperand::CreateReg(Reg));
1047   return MCDisassembler::Success;
1048 }
1049
1050 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1051                                            unsigned RegNo,
1052                                            uint64_t Address,
1053                                            const void *Decoder) {
1054   if (RegNo > 31)
1055     return MCDisassembler::Fail;
1056   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1057   Inst.addOperand(MCOperand::CreateReg(Reg));
1058   return MCDisassembler::Success;
1059 }
1060
1061 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1062                                            unsigned RegNo,
1063                                            uint64_t Address,
1064                                            const void *Decoder) {
1065   if (RegNo > 7)
1066     return MCDisassembler::Fail;
1067   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1068   Inst.addOperand(MCOperand::CreateReg(Reg));
1069   return MCDisassembler::Success;
1070 }
1071
1072 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1073                                              uint64_t Address,
1074                                              const void *Decoder) {
1075   if (RegNo > 31)
1076     return MCDisassembler::Fail;
1077
1078   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1079   Inst.addOperand(MCOperand::CreateReg(Reg));
1080   return MCDisassembler::Success;
1081 }
1082
1083 static DecodeStatus DecodeMem(MCInst &Inst,
1084                               unsigned Insn,
1085                               uint64_t Address,
1086                               const void *Decoder) {
1087   int Offset = SignExtend32<16>(Insn & 0xffff);
1088   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1089   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1090
1091   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1092   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1093
1094   if(Inst.getOpcode() == Mips::SC ||
1095      Inst.getOpcode() == Mips::SCD){
1096     Inst.addOperand(MCOperand::CreateReg(Reg));
1097   }
1098
1099   Inst.addOperand(MCOperand::CreateReg(Reg));
1100   Inst.addOperand(MCOperand::CreateReg(Base));
1101   Inst.addOperand(MCOperand::CreateImm(Offset));
1102
1103   return MCDisassembler::Success;
1104 }
1105
1106 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1107                               unsigned Insn,
1108                               uint64_t Address,
1109                               const void *Decoder) {
1110   int Offset = SignExtend32<16>(Insn & 0xffff);
1111   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1112   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1113
1114   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1115
1116   Inst.addOperand(MCOperand::CreateReg(Base));
1117   Inst.addOperand(MCOperand::CreateImm(Offset));
1118   Inst.addOperand(MCOperand::CreateImm(Hint));
1119
1120   return MCDisassembler::Success;
1121 }
1122
1123 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1124                                     unsigned Insn,
1125                                     uint64_t Address,
1126                                     const void *Decoder) {
1127   int Offset = SignExtend32<12>(Insn & 0xfff);
1128   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1129   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1130
1131   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1132
1133   Inst.addOperand(MCOperand::CreateReg(Base));
1134   Inst.addOperand(MCOperand::CreateImm(Offset));
1135   Inst.addOperand(MCOperand::CreateImm(Hint));
1136
1137   return MCDisassembler::Success;
1138 }
1139
1140 static DecodeStatus DecodeSyncI(MCInst &Inst,
1141                               unsigned Insn,
1142                               uint64_t Address,
1143                               const void *Decoder) {
1144   int Offset = SignExtend32<16>(Insn & 0xffff);
1145   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1146
1147   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1148
1149   Inst.addOperand(MCOperand::CreateReg(Base));
1150   Inst.addOperand(MCOperand::CreateImm(Offset));
1151
1152   return MCDisassembler::Success;
1153 }
1154
1155 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1156                                     uint64_t Address, const void *Decoder) {
1157   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1158   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1159   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1160
1161   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1162   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1163
1164   Inst.addOperand(MCOperand::CreateReg(Reg));
1165   Inst.addOperand(MCOperand::CreateReg(Base));
1166
1167   // The immediate field of an LD/ST instruction is scaled which means it must
1168   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1169   // data format.
1170   // .b - 1 byte
1171   // .h - 2 bytes
1172   // .w - 4 bytes
1173   // .d - 8 bytes
1174   switch(Inst.getOpcode())
1175   {
1176   default:
1177     assert (0 && "Unexpected instruction");
1178     return MCDisassembler::Fail;
1179     break;
1180   case Mips::LD_B:
1181   case Mips::ST_B:
1182     Inst.addOperand(MCOperand::CreateImm(Offset));
1183     break;
1184   case Mips::LD_H:
1185   case Mips::ST_H:
1186     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1187     break;
1188   case Mips::LD_W:
1189   case Mips::ST_W:
1190     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1191     break;
1192   case Mips::LD_D:
1193   case Mips::ST_D:
1194     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1195     break;
1196   }
1197
1198   return MCDisassembler::Success;
1199 }
1200
1201 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1202                                     unsigned Insn,
1203                                     uint64_t Address,
1204                                     const void *Decoder) {
1205   unsigned Offset = Insn & 0xf;
1206   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1207   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1208
1209   switch (Inst.getOpcode()) {
1210     case Mips::LBU16_MM:
1211     case Mips::LHU16_MM:
1212     case Mips::LW16_MM:
1213       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1214             == MCDisassembler::Fail)
1215         return MCDisassembler::Fail;
1216       break;
1217     case Mips::SB16_MM:
1218     case Mips::SH16_MM:
1219     case Mips::SW16_MM:
1220       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1221             == MCDisassembler::Fail)
1222         return MCDisassembler::Fail;
1223       break;
1224   }
1225
1226   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1227         == MCDisassembler::Fail)
1228     return MCDisassembler::Fail;
1229
1230   switch (Inst.getOpcode()) {
1231     case Mips::LBU16_MM:
1232       if (Offset == 0xf)
1233         Inst.addOperand(MCOperand::CreateImm(-1));
1234       else
1235         Inst.addOperand(MCOperand::CreateImm(Offset));
1236       break;
1237     case Mips::SB16_MM:
1238       Inst.addOperand(MCOperand::CreateImm(Offset));
1239       break;
1240     case Mips::LHU16_MM:
1241     case Mips::SH16_MM:
1242       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1243       break;
1244     case Mips::LW16_MM:
1245     case Mips::SW16_MM:
1246       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1247       break;
1248   }
1249
1250   return MCDisassembler::Success;
1251 }
1252
1253 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1254                                           unsigned Insn,
1255                                           uint64_t Address,
1256                                           const void *Decoder) {
1257   unsigned Offset = Insn & 0x1F;
1258   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1259
1260   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1261
1262   Inst.addOperand(MCOperand::CreateReg(Reg));
1263   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1264   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1265
1266   return MCDisassembler::Success;
1267 }
1268
1269 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1270                                           unsigned Insn,
1271                                           uint64_t Address,
1272                                           const void *Decoder) {
1273   unsigned Offset = Insn & 0x7F;
1274   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1275
1276   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1277
1278   Inst.addOperand(MCOperand::CreateReg(Reg));
1279   Inst.addOperand(MCOperand::CreateReg(Mips::GP));
1280   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1281
1282   return MCDisassembler::Success;
1283 }
1284
1285 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1286                                      unsigned Insn,
1287                                      uint64_t Address,
1288                                      const void *Decoder) {
1289   int Offset = SignExtend32<12>(Insn & 0x0fff);
1290   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1291   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1292
1293   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1294   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1295
1296   switch (Inst.getOpcode()) {
1297   case Mips::SWM32_MM:
1298   case Mips::LWM32_MM:
1299     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1300         == MCDisassembler::Fail)
1301       return MCDisassembler::Fail;
1302     Inst.addOperand(MCOperand::CreateReg(Base));
1303     Inst.addOperand(MCOperand::CreateImm(Offset));
1304     break;
1305   case Mips::SC_MM:
1306     Inst.addOperand(MCOperand::CreateReg(Reg));
1307     // fallthrough
1308   default:
1309     Inst.addOperand(MCOperand::CreateReg(Reg));
1310     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1311       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1312
1313     Inst.addOperand(MCOperand::CreateReg(Base));
1314     Inst.addOperand(MCOperand::CreateImm(Offset));
1315   }
1316
1317   return MCDisassembler::Success;
1318 }
1319
1320 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1321                                      unsigned Insn,
1322                                      uint64_t Address,
1323                                      const void *Decoder) {
1324   int Offset = SignExtend32<16>(Insn & 0xffff);
1325   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1326   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1327
1328   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1329   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1330
1331   Inst.addOperand(MCOperand::CreateReg(Reg));
1332   Inst.addOperand(MCOperand::CreateReg(Base));
1333   Inst.addOperand(MCOperand::CreateImm(Offset));
1334
1335   return MCDisassembler::Success;
1336 }
1337
1338 static DecodeStatus DecodeFMem(MCInst &Inst,
1339                                unsigned Insn,
1340                                uint64_t Address,
1341                                const void *Decoder) {
1342   int Offset = SignExtend32<16>(Insn & 0xffff);
1343   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1344   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1345
1346   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1347   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1348
1349   Inst.addOperand(MCOperand::CreateReg(Reg));
1350   Inst.addOperand(MCOperand::CreateReg(Base));
1351   Inst.addOperand(MCOperand::CreateImm(Offset));
1352
1353   return MCDisassembler::Success;
1354 }
1355
1356 static DecodeStatus DecodeFMem2(MCInst &Inst,
1357                                unsigned Insn,
1358                                uint64_t Address,
1359                                const void *Decoder) {
1360   int Offset = SignExtend32<16>(Insn & 0xffff);
1361   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1362   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1363
1364   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1365   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1366
1367   Inst.addOperand(MCOperand::CreateReg(Reg));
1368   Inst.addOperand(MCOperand::CreateReg(Base));
1369   Inst.addOperand(MCOperand::CreateImm(Offset));
1370
1371   return MCDisassembler::Success;
1372 }
1373
1374 static DecodeStatus DecodeFMem3(MCInst &Inst,
1375                                unsigned Insn,
1376                                uint64_t Address,
1377                                const void *Decoder) {
1378   int Offset = SignExtend32<16>(Insn & 0xffff);
1379   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1380   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1381
1382   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1383   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1384
1385   Inst.addOperand(MCOperand::CreateReg(Reg));
1386   Inst.addOperand(MCOperand::CreateReg(Base));
1387   Inst.addOperand(MCOperand::CreateImm(Offset));
1388
1389   return MCDisassembler::Success;
1390 }
1391
1392 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1393                                     unsigned Insn,
1394                                     uint64_t Address,
1395                                     const void *Decoder) {
1396   int Offset = SignExtend32<11>(Insn & 0x07ff);
1397   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1398   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1399
1400   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1401   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1402
1403   Inst.addOperand(MCOperand::CreateReg(Reg));
1404   Inst.addOperand(MCOperand::CreateReg(Base));
1405   Inst.addOperand(MCOperand::CreateImm(Offset));
1406
1407   return MCDisassembler::Success;
1408 }
1409 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1410                                        unsigned Insn,
1411                                        uint64_t Address,
1412                                        const void *Decoder) {
1413   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1414   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1415   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1416
1417   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1418   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1419
1420   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1421     Inst.addOperand(MCOperand::CreateReg(Rt));
1422   }
1423
1424   Inst.addOperand(MCOperand::CreateReg(Rt));
1425   Inst.addOperand(MCOperand::CreateReg(Base));
1426   Inst.addOperand(MCOperand::CreateImm(Offset));
1427
1428   return MCDisassembler::Success;
1429 }
1430
1431 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1432                                               unsigned RegNo,
1433                                               uint64_t Address,
1434                                               const void *Decoder) {
1435   // Currently only hardware register 29 is supported.
1436   if (RegNo != 29)
1437     return  MCDisassembler::Fail;
1438   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1439   return MCDisassembler::Success;
1440 }
1441
1442 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1443                                               unsigned RegNo,
1444                                               uint64_t Address,
1445                                               const void *Decoder) {
1446   if (RegNo > 30 || RegNo %2)
1447     return MCDisassembler::Fail;
1448
1449   ;
1450   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1451   Inst.addOperand(MCOperand::CreateReg(Reg));
1452   return MCDisassembler::Success;
1453 }
1454
1455 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1456                                                 unsigned RegNo,
1457                                                 uint64_t Address,
1458                                                 const void *Decoder) {
1459   if (RegNo >= 4)
1460     return MCDisassembler::Fail;
1461
1462   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1463   Inst.addOperand(MCOperand::CreateReg(Reg));
1464   return MCDisassembler::Success;
1465 }
1466
1467 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1468                                                unsigned RegNo,
1469                                                uint64_t Address,
1470                                                const void *Decoder) {
1471   if (RegNo >= 4)
1472     return MCDisassembler::Fail;
1473
1474   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1475   Inst.addOperand(MCOperand::CreateReg(Reg));
1476   return MCDisassembler::Success;
1477 }
1478
1479 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1480                                                unsigned RegNo,
1481                                                uint64_t Address,
1482                                                const void *Decoder) {
1483   if (RegNo >= 4)
1484     return MCDisassembler::Fail;
1485
1486   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1487   Inst.addOperand(MCOperand::CreateReg(Reg));
1488   return MCDisassembler::Success;
1489 }
1490
1491 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1492                                                unsigned RegNo,
1493                                                uint64_t Address,
1494                                                const void *Decoder) {
1495   if (RegNo > 31)
1496     return MCDisassembler::Fail;
1497
1498   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1499   Inst.addOperand(MCOperand::CreateReg(Reg));
1500   return MCDisassembler::Success;
1501 }
1502
1503 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1504                                                unsigned RegNo,
1505                                                uint64_t Address,
1506                                                const void *Decoder) {
1507   if (RegNo > 31)
1508     return MCDisassembler::Fail;
1509
1510   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1511   Inst.addOperand(MCOperand::CreateReg(Reg));
1512   return MCDisassembler::Success;
1513 }
1514
1515 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1516                                                unsigned RegNo,
1517                                                uint64_t Address,
1518                                                const void *Decoder) {
1519   if (RegNo > 31)
1520     return MCDisassembler::Fail;
1521
1522   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1523   Inst.addOperand(MCOperand::CreateReg(Reg));
1524   return MCDisassembler::Success;
1525 }
1526
1527 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1528                                                unsigned RegNo,
1529                                                uint64_t Address,
1530                                                const void *Decoder) {
1531   if (RegNo > 31)
1532     return MCDisassembler::Fail;
1533
1534   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1535   Inst.addOperand(MCOperand::CreateReg(Reg));
1536   return MCDisassembler::Success;
1537 }
1538
1539 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1540                                                unsigned RegNo,
1541                                                uint64_t Address,
1542                                                const void *Decoder) {
1543   if (RegNo > 7)
1544     return MCDisassembler::Fail;
1545
1546   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1547   Inst.addOperand(MCOperand::CreateReg(Reg));
1548   return MCDisassembler::Success;
1549 }
1550
1551 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1552                                             unsigned RegNo,
1553                                             uint64_t Address,
1554                                             const void *Decoder) {
1555   if (RegNo > 31)
1556     return MCDisassembler::Fail;
1557
1558   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1559   Inst.addOperand(MCOperand::CreateReg(Reg));
1560   return MCDisassembler::Success;
1561 }
1562
1563 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1564                                        unsigned Offset,
1565                                        uint64_t Address,
1566                                        const void *Decoder) {
1567   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1568   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1569   return MCDisassembler::Success;
1570 }
1571
1572 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1573                                      unsigned Insn,
1574                                      uint64_t Address,
1575                                      const void *Decoder) {
1576
1577   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1578   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1579   return MCDisassembler::Success;
1580 }
1581
1582 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1583                                          unsigned Offset,
1584                                          uint64_t Address,
1585                                          const void *Decoder) {
1586   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1587
1588   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1589   return MCDisassembler::Success;
1590 }
1591
1592 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1593                                          unsigned Offset,
1594                                          uint64_t Address,
1595                                          const void *Decoder) {
1596   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1597
1598   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1599   return MCDisassembler::Success;
1600 }
1601
1602 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1603                                           unsigned Offset,
1604                                           uint64_t Address,
1605                                           const void *Decoder) {
1606   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1607   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1608   return MCDisassembler::Success;
1609 }
1610
1611 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1612                                            unsigned Offset,
1613                                            uint64_t Address,
1614                                            const void *Decoder) {
1615   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1616   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1617   return MCDisassembler::Success;
1618 }
1619
1620 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1621                                          unsigned Offset,
1622                                          uint64_t Address,
1623                                          const void *Decoder) {
1624   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1625   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1626   return MCDisassembler::Success;
1627 }
1628
1629 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1630                                        unsigned Insn,
1631                                        uint64_t Address,
1632                                        const void *Decoder) {
1633   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1634   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1635   return MCDisassembler::Success;
1636 }
1637
1638 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1639                                        unsigned Value,
1640                                        uint64_t Address,
1641                                        const void *Decoder) {
1642   if (Value == 0)
1643     Inst.addOperand(MCOperand::CreateImm(1));
1644   else if (Value == 0x7)
1645     Inst.addOperand(MCOperand::CreateImm(-1));
1646   else
1647     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1648   return MCDisassembler::Success;
1649 }
1650
1651 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1652                                     unsigned Value,
1653                                     uint64_t Address,
1654                                     const void *Decoder) {
1655   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1656   return MCDisassembler::Success;
1657 }
1658
1659 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1660                                   unsigned Value,
1661                                   uint64_t Address,
1662                                   const void *Decoder) {
1663   if (Value == 0x7F)
1664     Inst.addOperand(MCOperand::CreateImm(-1));
1665   else
1666     Inst.addOperand(MCOperand::CreateImm(Value));
1667   return MCDisassembler::Success;
1668 }
1669
1670 static DecodeStatus DecodeSimm4(MCInst &Inst,
1671                                 unsigned Value,
1672                                 uint64_t Address,
1673                                 const void *Decoder) {
1674   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1675   return MCDisassembler::Success;
1676 }
1677
1678 static DecodeStatus DecodeSimm16(MCInst &Inst,
1679                                  unsigned Insn,
1680                                  uint64_t Address,
1681                                  const void *Decoder) {
1682   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1683   return MCDisassembler::Success;
1684 }
1685
1686 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1687                                  unsigned Insn,
1688                                  uint64_t Address,
1689                                  const void *Decoder) {
1690   // We add one to the immediate field as it was encoded as 'imm - 1'.
1691   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1692   return MCDisassembler::Success;
1693 }
1694
1695 static DecodeStatus DecodeInsSize(MCInst &Inst,
1696                                   unsigned Insn,
1697                                   uint64_t Address,
1698                                   const void *Decoder) {
1699   // First we need to grab the pos(lsb) from MCInst.
1700   int Pos = Inst.getOperand(2).getImm();
1701   int Size = (int) Insn - Pos + 1;
1702   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1703   return MCDisassembler::Success;
1704 }
1705
1706 static DecodeStatus DecodeExtSize(MCInst &Inst,
1707                                   unsigned Insn,
1708                                   uint64_t Address,
1709                                   const void *Decoder) {
1710   int Size = (int) Insn  + 1;
1711   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1712   return MCDisassembler::Success;
1713 }
1714
1715 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1716                                      uint64_t Address, const void *Decoder) {
1717   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1718   return MCDisassembler::Success;
1719 }
1720
1721 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1722                                      uint64_t Address, const void *Decoder) {
1723   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1724   return MCDisassembler::Success;
1725 }
1726
1727 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1728                                   uint64_t Address, const void *Decoder) {
1729   int32_t DecodedValue;
1730   switch (Insn) {
1731   case 0: DecodedValue = 256; break;
1732   case 1: DecodedValue = 257; break;
1733   case 510: DecodedValue = -258; break;
1734   case 511: DecodedValue = -257; break;
1735   default: DecodedValue = SignExtend32<9>(Insn); break;
1736   }
1737   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1738   return MCDisassembler::Success;
1739 }
1740
1741 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1742                                     uint64_t Address, const void *Decoder) {
1743   // Insn must be >= 0, since it is unsigned that condition is always true.
1744   assert(Insn < 16);
1745   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1746                              255, 32768, 65535};
1747   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1748   return MCDisassembler::Success;
1749 }
1750
1751 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1752                                     uint64_t Address, const void *Decoder) {
1753   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1754   return MCDisassembler::Success;
1755 }
1756
1757 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1758                                          unsigned Insn,
1759                                          uint64_t Address,
1760                                          const void *Decoder) {
1761   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1762                      Mips::S6, Mips::FP};
1763   unsigned RegNum;
1764
1765   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1766   // Empty register lists are not allowed.
1767   if (RegLst == 0)
1768     return MCDisassembler::Fail;
1769
1770   RegNum = RegLst & 0xf;
1771   for (unsigned i = 0; i < RegNum; i++)
1772     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1773
1774   if (RegLst & 0x10)
1775     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1776
1777   return MCDisassembler::Success;
1778 }
1779
1780 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1781                                            uint64_t Address,
1782                                            const void *Decoder) {
1783   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1784   unsigned RegNum;
1785
1786   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1787   // Empty register lists are not allowed.
1788   if (RegLst == 0)
1789     return MCDisassembler::Fail;
1790
1791   RegNum = RegLst & 0x3;
1792   for (unsigned i = 0; i < RegNum - 1; i++)
1793     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1794
1795   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1796
1797   return MCDisassembler::Success;
1798 }
1799
1800 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1801                                      uint64_t Address, const void *Decoder) {
1802   Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1803   return MCDisassembler::Success;
1804 }